diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index d94ca726..3894d740 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -27,6 +27,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `mip` register
 - Use CSR helper macros to define `mstatus` register
 - Use CSR helper macros to define `mstatush` register
+- Use CSR helper macros to define `mtvec` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mtvec.rs b/riscv/src/register/mtvec.rs
index c4fc7375..8fa599ac 100644
--- a/riscv/src/register/mtvec.rs
+++ b/riscv/src/register/mtvec.rs
@@ -63,3 +63,41 @@ impl Mtvec {
         }
     }
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mtvec() {
+        let mut m = Mtvec::from_bits(0);
+
+        (1..=usize::BITS)
+            .map(|r| (((1u128 << r) - 1) as usize) & !TRAP_MASK)
+            .for_each(|address| {
+                m.set_address(address);
+                assert_eq!(m.address(), address);
+
+                assert_eq!(m.try_set_address(address), Ok(()));
+                assert_eq!(m.address(), address);
+            });
+
+        (1..=usize::BITS)
+            .filter_map(|r| match ((1u128 << r) - 1) as usize {
+                addr if (addr & TRAP_MASK) != 0 => Some(addr),
+                _ => None,
+            })
+            .for_each(|address| {
+                assert_eq!(
+                    m.try_set_address(address),
+                    Err(Error::InvalidFieldVariant {
+                        field: "mtvec::address",
+                        value: address,
+                    })
+                );
+            });
+
+        test_csr_field!(m, trap_mode: TrapMode::Direct);
+        test_csr_field!(m, trap_mode: TrapMode::Vectored);
+    }
+}