some questions

[bigplanewangyue]

Hi author, I would like to ask how this simulator can implement similar to cuda's __ldcg() that can bypass L1 cache and cache data into L2 only and measure the latency of hit and miss of L2 cache, in your example I just see that I can measure the average access time and the number in hit and miss and how to measure the latency of accessing the memory of the remote GPU in a multi-GPU environment, is this achievable in this simulator?

[syifan]

Are you OK will fully remove L1 in the configuration so that the CUs are directly connected to L2 caches?