different access counts to a cache

[Soilorian]

Hello Mr. Sun, hope you are well

during my exploration on mgpu-sim and working with the mem.trace file I've noticed something strange. I was comparing the results of my analysis on this file and the pre made hit and miss count by using the -report-cache-hit-rate flag and I see some differences.
for example, on fir benchmark after building and running the code with the following command

./fir -timing -trace-mem -report-cache-hit-rate

there is a contradiction.

if we see the metrics file we see that for a specific cache like GPU[1].SA[3].L1SCache we see a total of 275 requests

but by simply counting the lines which match end.*GPU[1].SA[3].L1SCache regex pattern in the mem.trace file, we see a total of 320 matches

so either the metrics didn't catch all of the requests going to this cache or mem.trace file contains some redundant requests( I also checked, the requests didn't have the same id so they are not duplicate) what is the reason for this?

[syifan]

Yes. I tried the same command and can confirm that I can recreate the same problem. It is a bug. I wonder if you can help us look into the problem. Limiting the program to a really small problem size should allow us to find the bug easy.

[syifan]

I have created this issue #85

[Soilorian]

sure, I'll do my best to find the cause of this bug

[syifan]

Thank you very much!

[Soilorian]

Hello,

I hope you’re doing well.

I have identified the cause of the problem we've been discussing. If you review the following lines in the MGPU-Sim codebase:

Line 472 of report.go
Line 475 of report.go

You’ll notice that the code is retrieving the number of read-mshr-miss but representing it as read-mshr-hit. This discrepancy is likely the reason why certain types of requests were not accounted for in the reports.

[syifan]

This is wonderful. Could you submit a pull request to solve the problem?

Thanks,
Yifan