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crude65816.fs
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crude65816.fs
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\ A Crude 65816 Emulator
\ Copyright 2015, 2016 Scot W. Stevenson <scot.stevenson@gmail.com>
\ Written with gforth 0.7
\ First version: 09. Jan 2015
\ This version: 22. Dec 2016
\ This program is free software: you can redistribute it and/or modify
\ it under the terms of the GNU General Public License as published by
\ the Free Software Foundation, either version 3 of the License, or
\ (at your option) any later version.
\ This program is distributed in the hope that it will be useful,
\ but WITHOUT ANY WARRANTY; without even the implied warranty of
\ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\ GNU General Public License for more details.
\ You should have received a copy of the GNU General Public License
\ along with this program. If not, see <http://www.gnu.org/licenses/>.
cr .( A Crude 65816 Emulator in Forth)
cr .( Version ALPHA 22. Dec 2016)
cr .( Copyright 2015 Scot W. Stevenson <scot.stevenson@gmail.com> )
cr .( This program comes with ABSOLUTELY NO WARRANTY) cr
\ ---- DEFINITIONS ----
cr .( Defining general stuff ...)
hex
1000000 constant 16M
\ ---- HARDWARE: CPU ----
cr .( Setting up CPU ... )
\ Names follow the convention from the WDC data sheet. We use uppercase letters.
\ P is generated through "P>", not stored, as are A and the B register
variable PC \ Program counter (16 bit)
variable C \ C register (16 bit); MSB is B, LSB is A
variable X \ X register (8\16 bit)
variable Y \ Y register (8\16 bit)
variable D \ Direct register (Zero Page on 6502) (16 bit)
variable S \ Stack Pointer (8/16 bit)
variable DBR \ Data Bank register ("B") (8 bit)
variable PBR \ Program Bank register ("K") (8 bit)
variable current-opcode
\ Vectors for interrupts
00fffc constant reset-v \ same for emulated and native modes
defer abort-v 00ffe8 constant abort-v.n 00fff8 constant abort-v.e
defer cop-v 00ffe4 constant cop-v.n 00fff4 constant cop-v.e
defer irq-v 00ffee constant irq-v.n 00fffe constant irq-v.e
defer nmi-v 00ffea constant nmi-v.n 00fffa constant nmi-v.e
defer brk-v 00ffe6 constant brk-v.n 00fffe constant brk-v.e
\ ---- HELPER FUNCTIONS ----
cr .( Creating helper functions ...)
\ These all assume HEX
\ mask addresses / hex numbers
defer mask.a defer mask.xy
: mask8 ( u -- u8 ) 0ff and ;
: mask16 ( u -- u16 ) 0ffff and ;
: mask24 ( u -- u24 ) 0ffffff and ;
\ Print byte as bits, does not add space, returns as HEX
: .8bits ( u -- )
2 base ! s>d <# # # # # # # # # #> type hex ;
\ Format numbers to two, four, and six places, assumes HEX
: .byte ( n -- ) s>d <# # # #> type space ;
: .word ( n -- ) s>d <# # # # # #> type space ;
: .longword ( n -- ) s>d <# # # # # # # #> type space ;
\ return least, most significant byte of 16-bit number
: lsb ( u -- u8 ) mask8 ;
: msb ( u -- u8 ) 0ff00 and 8 rshift ;
: bank ( u -- u8 ) 10 rshift mask8 ;
\ Extend the sign of an 8-bit/16-bit number in a way we don't have to care about
\ how large the cell size on the Forth machine is. Assumes that TRUE flag is
\ some form of FFFF. MASK8/MASK16 is paranoid. Assumes HEX.
: signextend ( u8 -- u ) mask8 dup 80 and 0<> 8 lshift or ;
: signextend.l ( u16 -- u ) mask16 dup 8000 and 0<> 10 lshift or ;
\ Accumulator manipulation
\ Because we are paranoid, we tend to MASK16 all registers before we store them
\ in their variables
: C>A ( u16 -- u8 ) lsb ; \ gives us A from C during 8 to 16 bit switch
: C>B ( u16 -- u8 ) msb ; \ gives us B from C during 8 to 16 bit switch
: A ( -- u8 ) C @ C>A ; \ A is a word, not variable
: B ( -- u8 ) C @ C>B ; \ B is a word, not variable
\ Save A into C, protecting B
: A>C! ( u8 -- ) B 8 lshift or mask16 C ! ;
\ Take values from TOS and store them in the Accumulator depending on their size
defer >C
: 8>C! ( u8 -- ) mask8 B 8 lshift or C ! ;
: 16>C! ( u16 -- ) mask16 C ! ;
\ Takes C and puts it TOS depending on the size of the accumulator
defer C>
: C>8 ( -- u8 ) A ;
: C>16 ( -- u16 ) C @ mask16 ; \ MASK is paranoid
\ 16 bit addresses and endian conversion
: 16>lsb/msb ( u16 -- lsb msb ) dup lsb swap msb ;
: lsb/msb>16 ( lsb msb -- u16 ) 8 lshift or ;
: msb/lsb>16 ( msb lsb -- u16 ) swap lsb/msb>16 ;
\ 24 bit to three bytes
: 24>bank/msb/lsb ( u24 -- bank msb lsb )
dup 16>lsb/msb ( u24 lsb msb )
swap rot ( msb lsb u24 )
bank -rot ; ( bank msb lsb )
: 24>lsb/msb/bank ( u24 -- lsb msb bank )
dup 16>lsb/msb ( n lsb msb )
rot bank ; ( lsb msb bank)
\ Program Counter. Automatically wraps at 16 bit
: PC+1 ( -- ) PC @ 1+ mask16 PC ! ;
: PC+2 ( -- ) PC @ 2 + mask16 PC ! ;
\ Make 24 bit value the new 24 bit address
: 24>PC24! ( 65addr24 -- ) 24>lsb/msb/bank PBR ! lsb/msb>16 PC ! ;
\ Convert various combinations to full 24 bit address. Assumes HEX
\ Paranoid: Makes sure that 16 bit address is really only 16 bit
: mem16/bank>24 ( 65addr16 bank -- 65addr24 )
swap mask16 swap 10 lshift or ;
: mem16/PBR>24 ( 65addr16 -- 65addr24 ) PBR @ mem16/bank>24 ;
: mem16/DBR>24 ( 65addr16 -- 65addr24 ) DBR @ mem16/bank>24 ;
\ Create a full 24 bit address that is in bank zero. In other words, wrap to
\ bank zero
: mem16/bank00>24 ( 65addr16 -- 65addr24 ) 00 mem16/bank>24 ;
: lsb/msb/bank>24 ( lsb msb bank -- 65addr24 )
-rot lsb/msb>16 swap mem16/bank>24 ;
\ Advance PC depending on what size our registers are
defer PC+a defer PC+xy
\ Get full 24 bit current address (PC plus PBR)
: PC24 ( -- 65addr24) PC @ PBR @ mem16/bank>24 ;
\ Increase a full 24 bit address by n, but wrap so that the bank byte is not
\ affected; that is, increase the "PC" part by one and wrap to bank
: 65addr+/wrap ( n 65addr24 -- 65addr24+1 )
>r dup mask16 r> + mask16 swap bank mem16/bank>24 ;
\ ---- MEMORY ----
cr .( Creating memory ...)
\ All accesses to memory are always full 24 bit. Stack follows little-endian
\ format with bank on top, then msb and lsb ( lsb msb bank -- ). However, we use
\ the "normal" number for all calculations, so we need to convert all fetches.
\ Also, we just allot the whole possible memory range. Note that this will fail
\ unless you called Gforth with "-m 1G" or something of that size like you were
\ told in the MANUAL.txt . You did read the manual, didn't you?
create memory 16M allot
: loadrom ( 65addr24 addr u -- )
r/o open-file drop ( 65addr fileid )
slurp-fid ( 65addr addr u )
rot memory + swap ( addr 65addrROM u )
move ;
\ load ROM files into memory
cr .( Loading ROM files to memory ...)
include config.fs
\ set up I/O stuff. Must be loaded after config.fs
cr .( Setting up I/O system ...)
include io.fs
\ -- FETCH FROM MEMORY --
\ Fetching data from memory depends on two things: The size of the register in
\ question (8/16 bit) and the memory structure based on banks. We adapt to the
\ size of the register by DEFERing the general routine and switching what it
\ refers to when the m- and x-flags are switched
\ Simple FETCH are the basic routines that do not affect the PC and ignore
\ wrapping. Used as the basis for all other fetch versions. FETCH8 includes the
\ check for special addresses (I/O chips, etc) so all other store words must be
\ based on it. Note we have to include this even for stack accesses because
\ somebody might be crazy enough to put the stack over the I/O addresses in bank
\ 00
: fetch8 ( 65addr24 -- u8 )
special-fetch? dup 0= if ( 65addr24 0|xt)
drop memory + c@ else \ c@ means no MASK8 is required
nip execute then ;
: fetch16 ( 65addr24 -- u16 )
dup fetch8 swap 1+ fetch8 lsb/msb>16 ;
: fetch24 ( 65addr24 -- u24 )
dup fetch8 over 1+ fetch8 rot 2 + fetch8 lsb/msb/bank>24 ;
\ FETCH/WRAP ("fetch with wrap") take an address and walks through it
\ byte-for-byte in case there is a bank boundry that is crossed. These are used
\ for LDA instructions, for example. These do not touch the PC, use FETCHPC for
\ that
defer fetch/wrap.a defer fetch/wrap.xy
: fetch/wrap8 ( 65addr24 -- u8) fetch8 ;
: fetch/wrap16 ( 65addr24 -- u16 )
dup fetch8 swap 1 65addr+/wrap fetch8 lsb/msb>16 ;
: fetch/wrap24 ( 65addr24 -- u24 )
dup fetch16 swap 2 65addr+/wrap fetch8 mem16/bank>24 ;
\ FETCHPC advances the PC while making sure we wrap at the bank boundry. Used
\ to get the opcodes of the instructions.
defer fetchPC.a defer fetchPC.xy
: fetchPC8 ( -- u8 ) PC @ PBR @ mem16/bank>24 fetch8 PC+1 ;
: fetchPC16 ( -- u16 ) fetchPC8 fetchPC8 lsb/msb>16 ;
: fetchPC24 ( -- u24 ) fetchPC16 fetchPC8 mem16/bank>24 ;
\ -- STORE IN MEMORY --
\ See remarks on fetching data from memory
\ Simply store routines that do not affect the PC and ignore wrapping. STORE8
\ includes the check for special addresses (I/O chips, etc) so all other store
\ words must be based on it.
defer store.a defer store.xy
: store8 ( u8 65addr24 -- )
special-store? dup 0= if ( u8 65addr24 0|xt)
drop memory + c! else \ C! means that no MASK is required
nip execute then ;
: store16 ( u16 65addr24 -- )
2dup swap lsb swap store8 swap msb swap 1+ store8 ;
: store24 ( u24 65addr24 -- ) \ This is only used for debugging
dup 3 + swap >r >r \ Create and save loop parameters
24>bank/msb/lsb
r> r> do i store8 loop ;
\ STORE/WRAP ("store with wrap") stores a byte or a double byte on
\ a byte-for-byte basis for cases when a bank-boundry can be crossed. These are
\ used for STA instructions (duh). These do not touch the PC. There is no need
\ for a STORE/WRAP24
defer store/wrap.a defer store/wrap.xy
: store/wrap8 ( u8 65addr24 -- ) store8 ;
: store/wrap16 ( u16 65addr24 -- )
2dup swap lsb swap store8 \ LSB
swap msb swap 1 65addr+/wrap store8 ; \ MSB
\ ---- FLAGS ----
cr .( Setting up flag routines ... )
\ make flag routines easier for humans to work with
: set? ( addr -- f ) @ ;
: clear? ( addr -- f ) @ invert ;
: set ( addr -- ) true swap ! ;
: clear ( addr -- ) false swap ! ;
\ All 65816 are fully-formed Forth flags, that is, one cell wide. There is no
\ flag in bit 5 in emulation mode. The convention is to use lowercase letters
\ for the flags to avoid confusion with the register names
create flags
false , false , false , false , false , false , false , false ,
\ We start with n-flag, not c-flag, as first (LSBit) entry in the table to make
\ creating P> with loops easier.
: n-flag ( -- addr ) flags ; \ bit 7
: v-flag ( -- addr ) flags cell + ; \ bit 6
: m-flag ( -- addr ) flags 2 cells + ; \ bit 5 in native mode
: x-flag ( -- addr ) flags 3 cells + ; \ bit 4 in native mode
: b-flag ( -- addr ) flags 3 cells + ; \ bit 4 in emulated mode
: d-flag ( -- addr ) flags 4 cells + ; \ bit 3
: i-flag ( -- addr ) flags 5 cells + ; \ bit 2
: z-flag ( -- addr ) flags 6 cells + ; \ bit 1
: c-flag ( -- addr ) flags 7 cells + ; \ bit 0
\ And then there's this guy. Emulation flag is not part of the status byte
variable e-flag
\ We don't use bit 5 in emulation mode, but it looks weird if it is set when we
\ switch from 16-bit A in native to emulation mode, so we take care of it
\ TODO check hardware to see what actually happens during these switches
: unused-flag ( -- addr ) flags 2 cells + ;
\ These are used to make a flag reflect the set/clear status of a bit in a byte
\ or word provided. Mask byte or word with AND to isolate single bits and then
\ use there
: test&set-c ( u -- ) 0<> c-flag ! ;
: test&set-n ( u -- ) 0<> n-flag ! ;
: test&set-v ( u -- ) 0<> v-flag ! ;
: test&set-z ( u -- ) 0= z-flag ! ;
defer mask-n.a defer mask-n.xy
: mask-n.8 ( u8 -- u8 ) 80 and ;
: mask-n.16 ( u16 -- u16 ) 8000 and ;
defer mask-v.a
: mask-v.8 ( u8 -- u8 ) 40 and ;
: mask-v.16 ( u16 -- u16 ) 4000 and ;
: mask-c ( u -- u ) 1 and ;
\ ---- TEST AND SET FLAGS ----
\ The basic, unspecific routines consume TOS, the register functions do not
\ Carry Flag
: check-c ( n n -- ) < invert c-flag ! ;
\ Negative Flag
: check-n8 ( n -- ) mask-n.8 test&set-n ;
: check-n16 ( n -- ) mask-n.16 test&set-n ;
: check-n.a ( -- ) C> mask-n.a test&set-n ;
\ Zero Flag. We don't need a separate test routine for X and Y because they are
\ always tested together with the Negative flag
: check-z.a ( -- ) C> test&set-z ;
\ Common combinations
: check-nz.a ( -- ) check-n.a check-z.a ;
: check-nz.xy ( X|Y -- ) dup mask-n.xy test&set-n test&set-z ;
: check-nz.x ( -- ) X @ check-nz.xy ;
: check-nz.y ( -- ) Y @ check-nz.xy ;
defer check-nz.TOS \ Used for LSR and other instructions that don't work on C
: check-nz.8 ( n8 -- ) dup check-n8 test&set-z ;
: check-nz.16 ( n16 -- ) dup check-n16 test&set-z ;
\ Routines to find out if addition produced a carry flag
defer carry?
: carry?.8 ( u -- f ) 100 and 0<> ;
: carry?.16 ( u -- f ) 10000 and 0<> ;
\ Create status byte out of flag array. We don't care if we are in emulation or
\ native mode
: P> ( -- u8 )
00 \ initialize P> byte
8 0 ?do
1 lshift \ next bit; note first shift is a dummy
flags i cells + @ \ loop thru flag table, from high bit to low
1 and + \ get last bit of Forth flag
loop ;
\ --- BCD ROUTINES ---
cr .( Setting up BCD routines ...)
\ BCD is required for decimal mode addition and subtraction operations. It is
\ also a pain in the rear. See http://www.6502.org/tutorials/decimal_mode.html
\ and https://en.wikipedia.org/wiki/Binary-coded_decimal for the background on
\ these routines. Check the Known Issues section of MANUAL.txt for known
\ problems with these routines
\ TODO We should be able to simplify and condense these once they are very,
\ very throughly tested
\ -- 8 bits --
\ Nine's complement of a nibble, for BCD subtraction
: 9s-comp ( u -- u ) 9 swap - ;
: byte>nibbles ( u -- nh nl ) dup 0f0 and 4 rshift swap 0f and ;
: nibbles>byte ( nh nl -- u ) swap 4 lshift or ;
\ Split up a byte into nibbles that are nine's complement, used for BCD
\ subtraction
: byte>9s-nibbles ( u -- nh nl )
dup 0f0 and 4 rshift 9s-comp
swap 0f and 9s-comp ;
\ Split up two bytes and interweave their nibbles so they are ready for addition
: nibbleweave-add ( u1 u2 -- n2h n1h n1l n2l)
byte>nibbles rot byte>nibbles rot ;
\ Split up two bytes and interweave their nibbles so they are ready for
\ subtraction (more exactly, addition with nine's complement)
: nibbleweave-sub ( u1 u2 -- n1h n2h n1l n2l)
byte>9s-nibbles rot byte>nibbles rot
>r -rot swap rot r> ; \ order is important for subtraction
\ Add two nibbles in BCD style. Intialize the carry with zero. Results in the
\ sum of the two nibbles (nr) and the "carry nibble" (nc) that is reused
: bcd-add-nibble ( n1 n2 c -- nc nr) + + dup 9 > if 6 + then byte>nibbles ;
\ Add two nibbles in BCD style. Intialize the carry with zero. Results in the
\ sum of the two nibbles (nr) and the "carry nibble" (nc) that is reused
: bcd-sub-nibble ( n1 n2 c -- nc nr) + + dup 9 > if 6 + then byte>nibbles ;
\ Add two bytes BCD style, including the c-flag. We use this routine for the
\ 8-bit ADC routine when the d-flag ist set
: bcd-add-bytes ( u1 u2 -- ur )
nibbleweave-add c-flag @ mask-c
bcd-add-nibble >r ( n2h n1h nc -- R: nl )
bcd-add-nibble r> nibbles>byte ( nc nr )
swap test&set-c ;
\ Subtract two bytes BCD style, including the c-flag. We use this routine
\ for the 8-bit SBC routine when the d-flag ist set
: bcd-sub-bytes ( u1 u2 -- ur )
swap \ We fetch the operand before we get the accumulator
nibbleweave-sub c-flag @ mask-c
bcd-sub-nibble >r ( n2h n1h nc -- R: nl )
bcd-sub-nibble r> nibbles>byte ( nc nr )
swap test&set-c ;
\ -- 16 bits --
: word>bytes ( w -- uh ul ) dup 0ff00 and 8 rshift swap 0ff and ;
: bytes>word ( uh ul -- w ) swap 8 lshift or ;
\ Split up two words and interweave their words so they are ready for addition
: byteweave-add ( w1 w2 -- u2h u1h u1l u2l) word>bytes rot word>bytes rot ;
\ Add two words BCD style, including the c-flag. We use this routine for the
\ 16-bit ADC routine when the d-flag ist set
: bcd-add-words ( w1 w2 -- w2 )
byteweave-add bcd-add-bytes >r bcd-add-bytes r> bytes>word ;
\ Split up two words and interweave their words so they are ready for
\ subtraction (rather, addition with nine's complement)
: byteweave-sub ( w1 w2 -- u1h u2h u1l u2l)
word>bytes rot word>bytes -rot swap rot ;
\
\ Subtract two words BCD style, including the c-flag. We use this routine
\ for the 16-bit SBC routine when the d-flag ist set
: bcd-sub-words ( w1 w2 -- w2 )
byteweave-sub swap bcd-sub-bytes >r swap bcd-sub-bytes r> bytes>word ;
\ --- COMPARE INSTRUCTIONS ---
\ See http://www.6502.org/tutorials/compare_beyond.html for discussion
defer cmp.a defer cmp.xy
: cmp8 ( AXY u8 -- ) 2dup check-c - check-nz.8 ;
: cmp16 ( CXY u16 -- ) 2dup check-c - check-nz.16 ;
\ --- BRANCHING ---
cr .( Setting up branching ...)
: takebranch ( -- ) PC24 fetch8 signextend 1+ PC @ + PC ! ;
: branch-if-true ( f -- ) if takebranch else PC+1 then ;
\ --- STACK STUFF ----
cr .( Setting up stack ...)
\ Stack wrapping is just about as much fun as Direct Page wrapping. When S is
\ increased or decreased, we wrap to bank 00, page 01 if two conditions are
\ true: We are in emulated mode and we're dealing with an "old" instruction
\ that was already available on the 65C02. Otherwise, we just wrap to bank 0.
\ See http://6502.org/tutorials/65c816opcodes.html#5.22 for details. Remember
\ S points to the next empty stack entry
defer S++ defer S--
\ There are 10 old instructions that affect the stack and 11 new ones. Searching
\ through the old ones is slightly more efficient
create old-s-opcodes
08 c, ( php) 20 c, ( jsr) 48 c, ( pha) 5a c, ( phy) 0da c, ( phx)
28 c, ( plp) 60 c, ( rts) 68 c, ( pla) 7a c, ( ply) 0fa c, ( plx)
: new-s-opcode? ( -- f )
true current-opcode @ ( f u8)
0a 0 do
dup old-s-opcodes i + c@
= if nip false swap then
loop drop ;
\ Increase and decrease stack pointer in native mode or if emulated mode with
\ new instructions. We wrap to bank 0. This is the fast, easy case we like.
: S++.n ( -- ) S @ 1+ mask16 S ! ;
: S--.n ( -- ) S @ 1- mask16 S ! ;
\ Increase or decrease the stack pointer by one, wrapping to page 01 and bank 00
\ boundries
: S++/wrap ( -- ) S @ 1+ mask8 0100 or S ! ; \ mask8 includes wrap to bank
: S--/wrap ( -- ) S @ 1- mask8 0100 or S ! ; \ mask8 includes wrap to bank
\ If this is a new opcode, we have to wrap to page 01
: S++.e ( -- ) new-s-opcode? if S++.n else S++/wrap then ;
: S--.e ( -- ) new-s-opcode? if S--.n else S--/wrap then ;
\ Push stuff to stack. Use the naked STORE8 routine here because we don't want
\ to touch the PC and S++ handles all the wrapping problems. PUSH8 is the base
\ word for all other forms.
defer push.a defer push.xy
: push8 ( n8 -- ) S @ store8 S-- ;
: push16 ( n16 -- ) 16>lsb/msb push8 push8 ;
: push24 ( n24 -- ) 24>bank/msb/lsb rot push8 swap push8 push8 ;
\ Pull stuff from stack. Use the naked FETCH8 routine here because we don't
\ want to touch the PC and S++ handles the wrapping problems. PULL8 is the base
\ word for all other forms
defer pull.a defer pull.xy
: pull8 ( -- n8 ) S++ S @ fetch8 ;
: pull16 ( -- n16 ) pull8 pull8 lsb/msb>16 ;
: pull24 ( -- n24 ) pull8 pull8 pull8 lsb/msb/bank>24 ;
\ --- INTERRUPT ROUTINES ---
cr .( Setting up interrupt routines ...)
\ We do not use the BRK command to drop out of a running loop during emulation,
\ this is the job of WAI and STP.
defer brk.a
: brk-core ( -- )
." *** BRK encountered at " PC24 .longword ." ***"
d-flag clear PC+1 PC @ push16 P> push8 i-flag set
brk-v fetch/wrap16 PC ! ;
: brk.n ( -- ) PBR @ push8 0 PBR ! brk-core ;
: brk.e ( -- ) b-flag set brk-core ;
\ COP is used as in textbook
defer cop.a
: cop.e ( -- )
." *** COP encountered at " PC24 .longword ." ***"
PC @ 2 + mask16 push16
P> push8
i-flag set
d-flag clear
cop-v fetch/wrap16 PC ! ;
: cop.n ( -- ) PBR @ push8 0 PBR ! cop.e ;
\ ---- REGISTER MODE SWITCHES ----
\ We use two internal flags to remember the width of the registers. Don't use
\ the x and m flags directly because this can screw up the status byte P>
variable a16flag a16flag clear
variable xy16flag xy16flag clear
\ Switch accumulator 8<->16 bit (p. 51 in Manual)
: a:16 ( -- )
['] fetch/wrap16 is fetch/wrap.a
['] fetchPC16 is fetchPC.a
['] store16 is store.a
['] store/wrap16 is store/wrap.a
['] 16>C! is >C
['] C>16 is C>
['] PC+2 is PC+a
['] check-nz.8 is check-nz.TOS
['] cmp16 is cmp.a
['] push16 is push.a
['] pull16 is pull.a
['] mask16 is mask.a
['] mask-n.16 is mask-n.a
['] mask-v.16 is mask-v.a
['] carry?.16 is carry?
a16flag set ;
: a:8 ( -- )
['] fetch/wrap8 is fetch/wrap.a
['] fetchPC8 is fetchPC.a
['] store8 is store.a
['] store/wrap8 is store/wrap.a
['] 8>C! is >C
['] C>8 is C>
['] PC+1 is PC+a
['] check-nz.8 is check-nz.TOS
['] cmp8 is cmp.a
['] push8 is push.a
['] pull8 is pull.a
['] mask8 is mask.a
['] mask-n.8 is mask-n.a
['] mask-v.8 is mask-v.a
['] carry?.8 is carry?
a16flag clear ;
\ Switch X and Y 8<->16 bit (p. 51 in Manual)
: xy:16 ( -- )
['] fetch/wrap16 is fetch/wrap.xy
['] fetchPC16 is fetchPC.xy
['] store16 is store.xy
['] store/wrap16 is store/wrap.xy
['] mask16 is mask.xy
['] mask-n.16 is mask-n.xy
['] PC+2 is PC+xy
['] cmp16 is cmp.xy
['] push16 is push.xy
['] pull16 is pull.xy
X @ 0FFFF AND X ! Y @ 0FFFF AND Y ! \ paranoid
xy16flag set ;
: xy:8 ( -- )
['] fetch/wrap8 is fetch/wrap.xy
['] fetchPC8 is fetchPC.xy
['] store8 is store.xy
['] store/wrap8 is store/wrap.xy
['] mask8 is mask.xy
['] mask-n.8 is mask-n.xy
['] PC+1 is PC+xy
['] cmp8 is cmp.xy
['] push8 is push.xy
['] pull8 is pull.xy
X @ 00FF AND X ! Y @ 00FF AND Y !
xy16flag clear ;
\ --- STATUS BYTE ---
\ These routines must come after mode switches for the registers
\ In native mode, changing m and x flags might change the size of these
\ registers
: flag-modeswitch ( -- )
e-flag set? if unused-flag clear else
m-flag set? if a:8 else a:16 then
x-flag set? if xy:8 else xy:16 then
then ;
: >P ( u8 -- )
0 7 ?do
dup 1 and \ get lowest bit
0= if false else true then \ convert to Forth flag
flags i cells + ! \ store in flag array
1 rshift
-1 +loop
flag-modeswitch ;
\ Return from interrupt. This needs to come after the status byte routines but
\ before the switch of the processor modes
defer rti.a
: rti-core ( -- ) pull8 >P pull16 PC ! ;
: rti.e ( -- ) rti-core ;
: rti.n ( -- ) rti-core pull8 PBR ! ;
\ SEP, REP. These need to come after the status byte routines but before the
\ switch of the processor modes
defer sep.a
: sep.n ( n8 -- ) P> fetchPC8 or >P ;
: sep.e ( n8 -- ) fetchPC8 0cf and P> or >P ; \ Mask with 11001111
defer rep.a
: rep.n ( n8 -- ) fetchPC8 invert P> and >P ;
: rep.e ( n8 -- ) fetchPC8 0cf and invert P> and >P ; \ Mask with 11001111
\ switch processor modes (native/emulated). See p. 45 and 61
: native ( -- )
e-flag clear
m-flag set
x-flag set
['] S++.n is S++
['] S--.n is S--
['] brk.n is brk.a
['] cop.n is cop.a
['] rti.n is rti.a
['] rep.n is rep.a
['] sep.n is sep.a
['] abort-v.n is abort-v
['] cop-v.n is cop-v
['] irq-v.n is irq-v
['] nmi-v.n is nmi-v
['] brk-v.n is brk-v ;
: emulated ( -- ) \ p. 45
\ TODO What happens with status bit 5 ?
\ PBR and DBR switch unchanged
e-flag set
b-flag clear \ TODO Make sure this is really what happens
unused-flag clear \ Make sure unused status bit 5 is not set
a:8 xy:8
S @ 00FF AND 0100 OR S ! \ stack pointer to 0100
0000 D ! \ direct page register initialized to zero
['] S++.e is S++
['] S--.e is S--
['] brk.e is brk.a
['] cop.e is cop.a
['] rti.e is rti.a
['] rep.e is rep.a
['] sep.e is sep.a
['] abort-v.e is abort-v
['] cop-v.e is cop-v
['] irq-v.e is irq-v
['] nmi-v.e is nmi-v
['] brk-v.e is brk-v ;
\ ---- ADDRESSING MODES ---
cr .( Defining addressing modes ...)
\ Mode words leave the correct address as TOS before the PC. Note that the
\ mnemonics for Absolute Mode have no suffix, but we use MODE.ABS for clarity.
\ Not all modes are listed here, because some are easier to code by hand. Nodes
\ advance the PC so we don't have to include that in the operand code; since the
\ PC is usually TOS, this requires some stack manipulation. Register
\ manipulation should come before the mode word (eg "Y @ MODE.ABS.DBR"), not
\ behind it.
\ Examples for the modes are given for the traditional syntax and for Typist's
\ Assembler
\ Absolute: "LDA $1000" / "lda 1000" #
\ We need two different versions, one for instructions that affect data and take
\ the DBR, and one for instructions that affect programs and take the PBR
: mode.abs.DBR ( -- 65addr24 ) fetchPC16 mem16/DBR>24 ;
: mode.abs.PBR ( -- 65addr24 ) fetchPC16 mem16/PBR>24 ;
\ Absolute Indirect: "JMP ($1000)" / "jmp.i 1000"
: mode.i ( -- 65addr24)
fetchPC16 00 mem16/bank>24 fetch/wrap16 mem16/PBR>24 ;
\ Absolute Indirect LONG: "JMP [$1000]" / "jmp.il 1000"
: mode.il ( -- 65addr24) fetchPC16 00 mem16/bank>24 fetch/wrap24 ;
\ Absolute Indexed X/Y (pp. 289-290): "LDA $1000,X" / "lda.x 1000"
\ Assumes that X will be the correct width (8 or 16 bit)
\ These DO NOT wrap to bank, so do not mask
: mode.x ( -- 65addr24 ) mode.abs.DBR X @ + ;
: mode.y ( -- 65addr24 ) mode.abs.DBR Y @ + ;
\ Absolute X Indexed Indirect (p. 291): "JMP ($1000,X)" / "jmp.xi 1000"
: mode.xi ( -- 65addr24 )
fetchPC16 X @ + mask16 PBR @ mem16/bank>24
fetch/wrap16 ;
\ Absolute Long: "LDA $100000" / "lda.l 100000"
: mode.l ( -- 65addr24) fetchPC24 ;
\ Absolute Long X Indexed: "LDA $100000,X" / "lda.lx 100000"
\ assumes that X will be the correct width (8 or 16 bit)
\ This DOES NOT wrap to bank
: mode.lx ( -- 65addr24) mode.l X @ + ;
\ Immediate Mode: "LDA #$10" / "lda.# 10"
\ Note that this mode does not advance the PC as it is used with A and XY so we
\ have to include a PC+a or PC+xy in the instructions themselves. Failure to do
\ so was a common error during development
: mode.imm ( -- 65addr24 ) PC24 ;
\ -- DIRECT PAGE MODES --
\ DP modes are a serious pain because of emulation mode and the difference
\ between page and bank wrapping. See
\ http://forum.6502.org/viewtopic.php?f=8&t=3459&start=30#p40855 .
\ TODO consider using a DEFER statement instead to distinguish between emulated
\ and native modes for speed, keeping the tests in emulated mode only; compare
\ code for stack handling
\ We only wrap to the current page if all following three conditions are true:
\ We are in emulation mode, the LSB of D is zero (that is, D is on a page
\ boundry), and we are dealing with an old opcode that was available on the
\ 65c02. TEST 1 is already defined via e-flag
: on-page-boundry? ( 65addr -- f ) mask8 0= ; \ TEST 2
\ The new DP opcodes with indexing which are never ever wrapped to the page
\ all have the LSB of 7, that is, 07, 17, etc in HEX. This means we don't have
\ to check them in a table, but can use a function. Life is good.
: old-dp-opcode? ( -- f )
current-opcode @ 0F and 7 = invert ; \ TEST 3
\ We do the e-flag test first because we assume that most people are going to
\ run the MPU in native mode and we get to quit earlier then
: wrap2page? ( -- f )
e-flag set? D @ on-page-boundry? and old-dp-opcode? and ;
\ Given the result of adding D with the byte from the operand as well as the
\ X or Y index, wrap correctly to page if necessary
: add&wrap ( u16 u8|u16 -- u16 )
wrap2page?
if over + mask8 \ discard MSB of addition, keeping LSB
swap 0ff00 and \ keep MSB of D, thereby wrapping
or else \ put LSB and MSB back together
+ then ; \ no page wrap, so just add; caller will wrap to bank
\ If this wraps the page, it means by definition that the LSB of D was not zero,
\ and so the legacy rules don't apply one way or another, so we don't need to do
\ any fancy testing. MASK16 is paranoid
: mode.d-core ( -- 65addr16 ) fetchPC8 D @ + mask16 ;
\ Direct Page (DP) (pp. 94, 155, 278): "LDA $10" / "lda.d 10"
\ Note that D can be relocated in emulated mode as well, see
\ http://forum.6502.org/viewtopic.php?f=8&t=3459&p=40389#p40370
: mode.d ( -- 65addr24) mode.d-core mem16/bank00>24 ;
\ DP Indexed X/Y (p. 299): "LDA $10,X" / "lda.dx 10"
: mode.dx ( -- 65addr24) mode.d-core X @ add&wrap mem16/bank00>24 ;
: mode.dy ( -- 65addr24) mode.d-core Y @ add&wrap mem16/bank00>24 ;
\ DP Indirect (p. 302): "LDA ($10)" / "lda.di 10"
\ Note this uses the Data Bank Register DBR, not PBR
: mode.di ( -- 65addr24)
mode.d-core mem16/bank00>24 fetch/wrap16 DBR @ mem16/bank>24 ;
\ DP Indirect X Indexed (p. 300): "LDA ($10,X)" / "lda.dxi 10"
: mode.dxi ( -- 65addr24)
mode.dx fetch/wrap16 DBR @ mem16/bank>24 ;
\ DP Indirect Y Indexed (p. 304): "LDA ($10),Y" / "lda.diy 10"
\ Does not need a "PC+1" because this is contained in MODE.DI
\ HIER TESTING
: mode.diy ( -- 65addr24) mode.di Y @ + ;
\ DP Indirect Long: "LDA [$10]" / "lda.dil 10"
: mode.dil ( -- 65addr24) mode.d-core mem16/bank00>24 fetch/wrap24 ;
\
\ DP Indirect Long Y Addressing : "LDA [$10],y" / "lda.dily 10"
: mode.dily ( -- 65addr24) mode.dil Y @ + ;
\ -- STACK MODES --
\ Stack Relative (p. 324): "LDA $10,S" / "lda.s 10"
: mode.s ( -- 65addr24 ) fetchPC8 S @ + mem16/bank00>24 ;
\ Stack Relative Y Indexed: "LDA (10,S),Y" / "lda.siy 10"
\ No "PC+1" because this is handled by MODE.S
: mode.siy ( -- 65addr24 ) mode.s Y @ + DBR @ mem16/bank>24 ;
\ ---- OUTPUT FUNCTIONS ----
cr .( Creating output functions ...)
\ Print state of machine
: .state ( -- )
\ Print status line
cr ." PC K "
a16flag clear? e-flag set? or if
." B A " else ." C " then
xy16flag clear? e-flag set? or if
." X Y " else ." X Y " then
e-flag set? if
." S D B NV-BDIZC" else
." S D B NVMXDIZC" then cr
\ Print PC and Program Bank Register
PC @ .word PBR @ .byte
\ print BA or C
a16flag clear? e-flag set? or if
B .byte A .byte else
C @ .word then
\ print X and Y
Y @ X @ xy16flag clear? if .byte .byte else .word .word then
\ print Stack Pointer, Direct Page Register, Status Register
S @ .word D @ .word DBR @ .byte P> .8bits space
e-flag set? if ." emulated" else ." native" then cr ;
\ Dump memory with 65816 addresses. Note you can also use the DUMP built-in
\ word from Forth with "<65ADDR> memory + <BYTES> DUMP"
: 65dump ( 65addr24 u -- )
cr 8 spaces ." 0 1 2 3 4 5 6 7 8 9 A B C D E F"
over + swap
dup 10 mod 0<> if
dup 0fffff0 and cr .longword space
dup 0f and 3 * spaces then
?do
i 10 mod 0= if cr i mask24 .longword space then
i fetch8 .byte
loop cr ;
\ Print Direct Page contents. We use D as a base regardless of which mode we are
\ in; see MODE.D for discussion of what happens with D in emulation mode.
\ Assumes HEX.
: .direct ( -- ) D @ 100 65dump ;
\ Print stack if we are in emulated mode
: stackempty? ( -- f ) S @ 01ff = ;
: .stack ( -- )
cr e-flag clear? if
." Can't dump stack when in native mode"
else
stackempty? if
." Stack is empty (S is 01FF in emulated mode)" cr else
0200 S @ 1+ ?do i dup . space fetch8 .byte cr loop
then then ;
\ ---- BLOCK MOVE INSTRUCTIONS ----
\ It would be really, really nice if we could just use Forth's MOVE word for
\ this. However, MVP and MVN both wrap at the block boundry, so that won't work,
\ see http://6502.org/tutorials/65c816opcodes.html#5.19 . Because we assume
\ MOVE is a lot faster than a loop, we use it for the cases where there is no
\ wrapping, and fall back on slower loop constructs otherwise. Remember
\ C is number of bytes to be moved minus one, and the first operand is the
\ destinantion bank byte, not the source. The return values are faked.
\ TODO Since we're only moving 64k max and this is a rare instruction,
\ get rid of two-mode system and just do everything the slow way
\ TODO Factor words once we know they are working
: move-without-wrap? ( -- f )
X @ C @ + 0ffff <=
Y @ C @ + 0ffff <= and ;
\ This is the best case, because fastest
: no-wrap-move ( dest src -- )
X @ swap mem16/bank>24 memory + \ full source address
swap Y @ swap mem16/bank>24 memory + \ full destination address
C @ 1+ move ;
\ Move core routine, used by both MVN and MVP
: move-core ( dbb sbb -- )
X @ i + mask16 ( dbb sbb s16 ) \ get source addres w/o bank byte
over mem16/bank>24 ( dbb sbb src ) \ calculate new every time
fetch8 rot ( sbb u8 dbb )
Y @ i + mask16 ( sbb u8 dbb d16 )
over mem16/bank>24 ( sbb u8 dbb dest )
swap -rot ( sbb dbb u8 dest )
store8 swap ; ( dbb sbb )
\ MVN starts with the first byte and works forward to avoid overwriting data
: mvn-slow ( dbb sbb -- ) C> 1+ 0 ?do move-core loop ;
\ MVP starts with the last byte and works backwards to avoid overwriting data
: mvp-slow ( dbb sbb -- ) 0 C> 1+ ?do move-core -1 +loop ;
: mvn-core ( -- )
fetchPC8 dup >r \ destination bank byte (!)
fetchPC8 \ source bank byte
move-without-wrap? if no-wrap-move else mvn-slow then
0ffff C ! 1 X +! 1 Y +! r> DBR ! ; \ we fake the loop results
: mvp-core ( -- )
fetchPC8 dup >r \ destination bank byte (!)
fetchPC8 \ source bank byte
move-without-wrap? if no-wrap-move else mvp-slow then
0ffff C ! 1 X +! 1 Y +! r> DBR ! ; \ we fake the loop results
\ ---- OPCODE CORE ROUTINES ----
cr .( Defining core routines for opcodes )
\ TODO Rewrite/optimize/refract these
\ These all work in both 8- and 16-bit modes
: and-core ( 65addr -- ) fetch/wrap.a mask.a C> and >C check-nz.a ;
: eor-core ( 65addr -- ) fetch/wrap.a mask.a C> xor >C check-nz.a ;
: ora-core ( 65addr -- ) fetch/wrap.a mask.a C> or >C check-nz.a ;
\ ASL-CORE is used for all, ASL-MEM for memory shifts
: asl-core ( u -- u ) dup mask-n.a test&set-c 1 lshift ;
: asl-mem ( addr -- )
dup fetch/wrap.a asl-core dup check-nz.TOS swap store/wrap.a ;
\ LSR-CORE is used for all, LSR-MEM for memory shifts
: lsr-core ( u -- u ) dup mask-c test&set-c 1 rshift ;
: lsr-mem ( addr -- )
dup fetch/wrap.a lsr-core dup check-nz.TOS swap store/wrap.a ;
\ ROL-CORE is used for all, ROL-MEM for memory shifts
: rol-core ( u -- u )
c-flag @ mask-c swap dup mask-n.a test&set-c 1 lshift or ;
: rol-mem ( addr -- )
dup fetch/wrap.a rol-core dup check-nz.TOS swap store/wrap.a ;
\ ROR-CORE is used for all, ROR-MEM for memory shifts
: ror-core ( u -- u )
c-flag @ mask-n.a swap dup mask-c test&set-c 1 rshift or ;
: ror-mem ( addr -- )
dup fetch/wrap.a ror-core dup check-nz.TOS swap store/wrap.a ;
: bit-core ( 65addr -- ) fetch/wrap.a
dup mask-n.a test&set-n dup mask-v.a test&set-v C> and test&set-z ;
: trb-core ( 65addr -- )
dup fetch/wrap.a
dup C> and test&set-z
C> true mask.a xor and swap store/wrap.a ;
: tsb-core ( 65addr -- )
dup fetch/wrap.a
dup C> and test&set-z
C> or swap store/wrap.a ;
\ INC and DEC for the Accumulator
: inc.accu ( -- ) C> 1+ mask.a >C check-nz.a ;
: dec.accu ( -- ) C> 1- mask.a >C check-nz.a ;
\ INC and DEC for memory
: inc.mem ( 65addr -- )
dup fetch/wrap.a 1+ mask.a dup check-nz.TOS swap store/wrap.a ;
: dec.mem ( 65addr -- )
dup fetch/wrap.a 1- mask.a dup check-nz.TOS swap store/wrap.a ;
: cmp-core ( u 65addr -- ) fetch/wrap.a cmp.a ;
: cpxy-core ( u 65addr -- ) fetch/wrap.xy cmp.xy ;
: lda-core ( 65addr -- ) fetch/wrap.a >C check-nz.a ;
: ldx-core ( 65addr -- ) fetch/wrap.xy X ! check-nz.x ;
: ldy-core ( 65addr -- ) fetch/wrap.xy Y ! check-nz.y ;
\ -- Addition routines --
\ Use this for both ADC and SBC
: adc-sbc-core ( u -- )
dup >r \ save operand for Overflow calculation
C> dup >r \ save accumulator for Overflow calculation
+ c-flag @ mask-c + dup >C carry? test&set-c check-nz.a