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Add generic delay #37

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sgherbst opened this issue Jun 5, 2021 · 0 comments

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sgherbst commented Jun 5, 2021

This can mainly be done by pulling in code from DragonPHY: https://github.com/StanfordVLSI/dragonphy2/blob/master/dragonphy/fpga_models/clk_delay_core.py

That delay is for a clock value signal (one cycle early), so it should probably be made more generic to handle both clock values and regular signals.

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