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DontStepOnWhiteTiles.prjx
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DontStepOnWhiteTiles.prjx
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KEY LIBERO "11.9"
KEY CAPTURE "11.9.3.5"
KEY DEFAULT_IMPORT_LOC "C:\Libero_projects\test_fabric2\hdl"
KEY DEFAULT_OPEN_LOC ""
KEY ProjectID "0"
KEY HDLTechnology "VERILOG"
KEY VERILOGMODE "VERILOG2001"
KEY VHDLMODE "VHDL2008"
KEY UseConstraintFlowTechnology "FALSE"
KEY VendorTechnology_Family "SmartFusion"
KEY VendorTechnology_Die "IP4X3M1"
KEY VendorTechnology_Package "fg484"
KEY VendorTechnology_Speed "STD"
KEY VendorTechnology_DieVoltage "1.5"
KEY VendorTechnology_PART_RANGE "COM"
KEY VendorTechnology_DSW_VCCA_VOLTAGE_RAMP_RATE ""
KEY VendorTechnology_IO_DEFT_STD "LVTTL"
KEY VendorTechnology_OPCONR ""
KEY VendorTechnology_PLL_SUPPLY ""
KEY VendorTechnology_RAD_EXPOSURE ""
KEY VendorTechnology_RESERVEMIGRATIONPINS "1"
KEY VendorTechnology_RESTRICTPROBEPINS "1"
KEY VendorTechnology_RESTRICTSPIPINS "0"
KEY VendorTechnology_SYSTEM_CONTROLLER_SUSPEND_MODE ""
KEY VendorTechnology_TARGETDEVICESFORMIGRATION "IP4X3M1"
KEY VendorTechnology_TEMPR "COM"
KEY VendorTechnology_UNUSED_MSS_IO_RESISTOR_PULL "None"
KEY VendorTechnology_VCCI_1.5_VOLTR "COM"
KEY VendorTechnology_VCCI_1.8_VOLTR "COM"
KEY VendorTechnology_VCCI_2.5_VOLTR "COM"
KEY VendorTechnology_VCCI_3.3_VOLTR "COM"
KEY VendorTechnology_VOLTR "COM"
KEY ProjectLocation "C:\Users\10339\source\repos\eecs373Project\DontStepOnWhiteTiles"
KEY ProjectDescription ""
KEY Pa4PeripheralNewSeq "GOOD"
KEY SimulationType "VERILOG"
KEY Vendor "Actel"
KEY ActiveRoot "DSWT::work"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST LIBRARIES
MSS_BFM_LIB
COREAPB3_LIB
ENDLIST
LIST LIBRARY_MSS_BFM_LIB
ALIAS=..\component\Actel\SmartFusionMSS\MSS\2.5.200\mti\user_verilog\MSS_BFM_LIB
COMPILE_OPTION=REFRESH_AND_COMPILE
CUSTOMPATH=false
ENDLIST
LIST LIBRARY_COREAPB3_LIB
ALIAS=COREAPB3_LIB
COMPILE_OPTION=COMPILE
CUSTOMPATH=false
ENDLIST
LIST FileManager
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IS_READONLY="TRUE"
IS_INCLUDED="TRUE"
ENDFILE
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ENDFILE
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IS_READONLY="TRUE"
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IS_READONLY="TRUE"
ENDFILE
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ENDFILE
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ENDFILE
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ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
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IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.200\MSS.cxf,actgen_cxf"
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STATE="utd"
TIME="1551204711"
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PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.200\MSS.cxf"
BEGIN_USE_CONSTRAINT
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END_USE_CONSTRAINT
USE_FOR_ANY_TOOL="FALSE"
IS_READONLY="TRUE"
ENDFILE
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VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
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BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER"
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ENDFILE
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IS_READONLY="TRUE"
ENDFILE
VALUE "<project>\constraint\DontStepOnWhiteTiles.pdc,pdc"
STATE="utd"
TIME="1555618216"
SIZE="2077"
ENDFILE
VALUE "<project>\designer\impl1\DSWT.adb,adb"
STATE="utd"
TIME="1555889727"
SIZE="2883072"
ENDFILE
VALUE "<project>\designer\impl1\DSWT.fdb,fdb"
STATE="utd"
TIME="1555979947"
SIZE="107372"
ENDFILE
VALUE "<project>\designer\impl1\DSWT.ide_des,ide_des"
STATE="utd"
TIME="1555889728"
SIZE="1113"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_compile_log.rpt,log"
STATE="utd"
TIME="1555792841"
SIZE="29661"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_fp\DSWT.pdb,pdb"
STATE="utd"
TIME="1555889182"
SIZE="111274"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_fp\DSWT.pro,pro"
STATE="utd"
TIME="1555889221"
SIZE="2442"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_fp\projectData\DSWT.pdb,pdb"
STATE="utd"
TIME="1555889221"
SIZE="111274"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_placeroute_log.rpt,log"
STATE="utd"
TIME="1555979930"
SIZE="2659"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_prgdata_log.rpt,log"
STATE="utd"
TIME="1555979948"
SIZE="762"
ENDFILE
VALUE "<project>\designer\impl1\DSWT_verifytiming_log.rpt,log"
STATE="utd"
TIME="1555979937"
SIZE="1174"
ENDFILE
VALUE "<project>\hdl\get_data.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="1013"
ENDFILE
VALUE "<project>\hdl\get_health.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="2071"
ENDFILE
VALUE "<project>\hdl\get_sq.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="1588"
ENDFILE
VALUE "<project>\hdl\proj_veri.v,hdl"
STATE="utd"
TIME="1555614590"
SIZE="12526"
ENDFILE
VALUE "<project>\hdl\score_control2.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="1916"
ENDFILE
VALUE "<project>\hdl\sram_control.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="1936"
ENDFILE
VALUE "<project>\hdl\vga640x480.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="3529"
ENDFILE
VALUE "<project>\hdl\write_pos.v,hdl"
STATE="utd"
TIME="1555612118"
SIZE="741"
ENDFILE
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
STATE="utd"
TIME="1554178210"
SIZE="1229"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
STATE="utd"
TIME="1551204711"
SIZE="41"
PARENT="<project>\component\Actel\SmartFusionMSS\MSS\2.5.200\MSS.cxf"
ENDFILE
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
STATE="utd"
TIME="1537302260"
SIZE="8016"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd"
TIME="1555979807"
SIZE="637"
PARENT="<project>\component\work\DSWT\DSWT.cxf"
ENDFILE
VALUE "<project>\simulation\test.bfm,sim"
STATE="utd"
TIME="1555979781"
SIZE="5497"
PARENT="<project>\component\work\DSWT_MSS\DSWT_MSS.cxf"
ENDFILE
VALUE "<project>\simulation\user.bfm,sim"
STATE="utd"
TIME="1553547890"
SIZE="670"
PARENT="<project>\component\work\DSWT_MSS\DSWT_MSS.cxf"
ENDFILE
VALUE "<project>\smartgen\sram\sram.cxf,actgen_cxf"
STATE="utd"
TIME="1554424195"
SIZE="2157"
ENDFILE
VALUE "<project>\smartgen\sram\sram.gen,gen"
STATE="utd"
TIME="1554424194"
SIZE="675"
PARENT="<project>\smartgen\sram\sram.cxf"
ENDFILE
VALUE "<project>\smartgen\sram\sram.log,log"
STATE="utd"
TIME="1554424195"
SIZE="3332"
PARENT="<project>\smartgen\sram\sram.cxf"
ENDFILE
VALUE "<project>\smartgen\sram\sram.v,hdl"
STATE="utd"
TIME="1554424195"
SIZE="12052"
PARENT="<project>\smartgen\sram\sram.cxf"
ENDFILE
VALUE "<project>\synthesis\DontStepOnWhiteTiles.edn,syn_edn"
STATE="utd"
TIME="1555037728"
SIZE="1450601"
ENDFILE
VALUE "<project>\synthesis\DontStepOnWhiteTiles.so,so"
STATE="utd"
TIME="1555037728"
SIZE="273"
ENDFILE
VALUE "<project>\synthesis\DontStepOnWhiteTiles_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1555037728"
SIZE="536"
ENDFILE
VALUE "<project>\synthesis\DontStepOnWhiteTiles_syn.prj,prj"
STATE="utd"
TIME="1555269748"
SIZE="3588"
ENDFILE
VALUE "<project>\synthesis\DSWT.edn,syn_edn"
STATE="utd"
TIME="1555792827"
SIZE="2193438"
ENDFILE
VALUE "<project>\synthesis\DSWT.so,so"
STATE="utd"
TIME="1555792827"
SIZE="241"
ENDFILE
VALUE "<project>\synthesis\DSWT_sdc.sdc,syn_sdc"
STATE="utd"
TIME="1555792827"
SIZE="536"
ENDFILE
VALUE "<project>\synthesis\DSWT_syn.prj,prj"
STATE="utd"
TIME="1555792828"
SIZE="3609"
ENDFILE
VALUE "<project>\synthesis\proj_top.so,so"
STATE="utd"
TIME="1555269846"
SIZE="249"
ENDFILE
VALUE "<project>\synthesis\proj_top_syn.prj,prj"
STATE="utd"
TIME="1555269846"
SIZE="3494"
ENDFILE
ENDLIST
LIST UsedFile
ENDLIST
LIST NewModulesInfo
LIST "DSWT::work"
FILE "<project>\component\work\DSWT\DSWT.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\DSWT\DSWT.pdc,pdc"
ENDLIST
LIST SynthesisConstraints
VALUE "<project>\component\work\DSWT_MSS\mss_tshell_syn.sdc,sdc"
ENDLIST
LIST ProjectState5.1
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\DSWT.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\DSWT.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
LIST PinReports
VALUE "<project>\designer\impl1\DSWT_report_pin_byname.txt,log"
VALUE "<project>\designer\impl1\DSWT_report_pin_bynumber.txt,log"
ENDLIST
ENDLIST
LIST "DSWT_MSS::work"
FILE "<project>\component\work\DSWT_MSS\DSWT_MSS.v,hdl"
LIST Other_Association
VALUE "<project>\component\work\DSWT_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\DSWT_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB"
FILE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3.v,hdl"
LIST Other_Association
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
ENDLIST
LIST AssociatedStimulus
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
ENDLIST
ENDLIST
LIST AssociatedStimulus
LIST CoreAPB3
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
ENDLIST
ENDLIST
LIST Other_Association
LIST DSWT
VALUE "<project>\simulation\subsystem.bfm,sim"
VALUE "<project>\component\work\DSWT\DSWT.pdc,pdc"
ENDLIST
LIST DSWT_MSS
VALUE "<project>\component\work\DSWT_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\simulation\user.bfm,sim"
VALUE "<project>\simulation\test.bfm,sim"
VALUE "<project>\component\work\DSWT_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
VALUE "<project>\simulation\CompileDssBfm.tcl,sim"
ENDLIST
LIST CoreAPB3
VALUE "<project>\simulation\bfmtovec_compile.tcl,sim"
VALUE "<project>\simulation\coreapb3_usertb_master.bfm,sim"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v,tb_hdl"
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\mti\scripts\wave_user.do,do"
ENDLIST
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=true
IncludeWaveDo=false
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
DoFileParams=
DisplayDUTWave=false
LogAllSignals=false
DisablePulseFiltering=false
DumpVCD=false
VCDFileName=power.vcd
VHDL2008=false
Verilog2001=false
SystemVerilog=false
TimeUnit=1
TimeUnitBase=ns
Precision=100
PrecisionBase=ps
ENDLIST
LIST ModelSimLibPath
UseCustomPath=FALSE
LibraryPath=
ENDLIST
LIST GlobalFlowOptions
GenerateHDLAfterSynthesis=FALSE
GenerateHDLAfterPhySynthesis=FALSE
RunDRCAfterSynthesis=TRUE
AutoCheckConstraints=TRUE
UpdateModelSimIni=TRUE
NoIOMode=FALSE
PeriInitStandalone=FALSE
EnableViewDraw=FALSE
UpdateViewDrawIni=TRUE
GenerateHDLFromSchematic=TRUE
VmNetlistFlowOn=FALSE
EnableDesignSeparationOn=FALSE
EnableSETMitigationOn=FALSE
DisplayFanoutLimit=10
AbortFlowOnPDCErrorsOn=TRUE
AbortFlowOnSDCErrorsOn=TRUE
InstantiateInSmartDesign=FALSE
FlashProInputFile=fdb
SmartGenCompileReport=T
ENDLIST
LIST PhySynthesisOptions
ENDLIST
LIST Profiles
NAME="SoftConsolev3.4"
FUNCTION="SoftwareIDE"
TOOL="SoftConsole"
LOCATION="C:\Program Files (x86)\Microsemi\SoftConsole v3.4\Eclipse\eclipse.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Synplify Pro ME"
FUNCTION="Synthesis"
TOOL="Synplify Pro ME"
LOCATION="C:\Microsemi\Libero_SoC_v11.9\SynplifyPro\bin\synplify_pro.exe"
PARAM="-licensetype synplifypro_actel -batch -log synplify.log"
BATCH=1
LICENSE=""
IS32BIT="1"
EndProfile
NAME="ModelSim ME"
FUNCTION="Simulation"
TOOL="ModelSim"
LOCATION="C:\Microsemi\Libero_SoC_v11.9\Modelsim\win32acoem\modelsim.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="FPExpress"
FUNCTION="Program"
TOOL="FlashPro"
LOCATION="C:\Microsemi\Libero_SoC_v11.9\Designer\bin\FPExpress.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
NAME="Identify Debugger"
FUNCTION="IdentifyDebugger"
TOOL="Identify Debugger"
LOCATION="C:\Microsemi\Libero_SoC_v11.9\Identify\bin\identify_debugger.exe"
PARAM=""
BATCH=0
LICENSE=""
IS32BIT="1"
EndProfile
ENDLIST
LIST ProjectState5.1
LIST "DSWT::work"
LIST Impl1
LiberoState=Post_Layout
ideSYNTHESIS(<project>\synthesis\DSWT.edn,syn_edn)=StateSuccess
ideDESIGNER(<project>\designer\impl1\DSWT.adb,adb)=StateSuccess
LIST FlowOptions
UsePhySynth=FALSE
UseSynth=TRUE
UseFhbAutoInst=FALSE
ENDLIST
Used_File_List
ENDUsed_File_List
ENDLIST
ENDLIST
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST CDBOrder
ENDLIST
LIST UserCustomizedFileList
ENDLIST
LIST OpenedFileList
ORIENTATION;HORIZONTAL
Reports;Reports;0
ReportsCurrentItem;Generate Programming Data:DSWT_prgdata_log.rpt
StartPage;StartPage;0
SmartDesign;DSWT;0
ACTIVEVIEW;DSWT
ENDLIST
LIST ModuleSubBlockList
LIST "BIBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "BIBUF_OPEND_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "Core_Control::work","hdl\proj_veri.v","FALSE","FALSE"
SUBBLOCK "get_data::work","hdl\get_data.v","FALSE","FALSE"
SUBBLOCK "get_health::work","hdl\get_health.v","FALSE","FALSE"
SUBBLOCK "get_score::work","hdl\score_control2.v","FALSE","FALSE"
SUBBLOCK "get_sq::work","hdl\get_sq.v","FALSE","FALSE"
SUBBLOCK "vga640x480::work","hdl\vga640x480.v","FALSE","FALSE"
ENDLIST
LIST "DESIGN_FIRMWARE::work","component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf","TRUE","FALSE"
SUBBLOCK "HAL::work","","FALSE","FALSE"
SUBBLOCK "MSS_GPIO_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_IAP_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_NVM_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_PDMA_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_RTC_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_SPI_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_Timer_Driver::work","","FALSE","FALSE"
SUBBLOCK "MSS_UART_Driver::work","","FALSE","FALSE"
SUBBLOCK "SmartFusion_CMSIS_PAL::work","","FALSE","FALSE"
ENDLIST
LIST "DESIGN_IO::work","component\work\DESIGN_IO\DESIGN_IO.cxf","TRUE","FALSE"
ENDLIST
LIST "DSWT::work","component\work\DSWT\DSWT.v","TRUE","FALSE"
SUBBLOCK "Core_Control::work","hdl\proj_veri.v","FALSE","FALSE"
SUBBLOCK "DSWT_MSS::work","component\work\DSWT_MSS\DSWT_MSS.v","TRUE","FALSE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3.v","FALSE","FALSE"
ENDLIST
LIST "DSWT_MSS::work","component\work\DSWT_MSS\DSWT_MSS.v","TRUE","FALSE"
SUBBLOCK "BIBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
SUBBLOCK "DSWT_MSS_tmp_MSS_CCC_0_MSS_CCC::work","component\work\DSWT_MSS\MSS_CCC_0\DSWT_MSS_tmp_MSS_CCC_0_MSS_CCC.v","FALSE","FALSE"
SUBBLOCK "INBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
SUBBLOCK "MSS_APB::work","component\work\DSWT_MSS\mss_tshell.v","FALSE","FALSE"
SUBBLOCK "OUTBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
SUBBLOCK "TRIBUFF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "DSWT_MSS_tmp_MSS_CCC_0_MSS_CCC::work","component\work\DSWT_MSS\MSS_CCC_0\DSWT_MSS_tmp_MSS_CCC_0_MSS_CCC.v","FALSE","FALSE"
SUBBLOCK "MSS_CCC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "get_data::work","hdl\get_data.v","FALSE","FALSE"
ENDLIST
LIST "get_health::work","hdl\get_health.v","FALSE","FALSE"
SUBBLOCK "get_data::work","hdl\get_data.v","FALSE","FALSE"
ENDLIST
LIST "get_score::work","hdl\score_control2.v","FALSE","FALSE"
SUBBLOCK "get_data::work","hdl\get_data.v","FALSE","FALSE"
ENDLIST
LIST "get_sq::work","hdl\get_sq.v","FALSE","FALSE"
SUBBLOCK "get_data::work","hdl\get_data.v","FALSE","FALSE"
ENDLIST
LIST "HAL::work","","FALSE","FALSE"
ENDLIST
LIST "INBUF_LVDS_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_LVPECL_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_MCCC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "INBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_ALL::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_APB::work","component\work\DSWT_MSS\mss_tshell.v","FALSE","FALSE"
ENDLIST
LIST "MSS_CCC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_GPIO_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_IAP_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_LPXTLOSC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSS_NVM_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_PDMA_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_RTC_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_SPI_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_Timer_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_UART_Driver::work","","FALSE","FALSE"
ENDLIST
LIST "MSS_XTLOSC::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "MSSINT::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "OUTBUF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "SmartFusion_CMSIS_PAL::work","","FALSE","FALSE"
ENDLIST
LIST "sram::work","smartgen\sram\sram.v","TRUE","FALSE"
ENDLIST
LIST "sram_control::work","hdl\sram_control.v","FALSE","FALSE"
ENDLIST
LIST "TRIBUFF_MSS::work","component\Actel\SmartFusionMSS\MSS\2.5.200\mss_comps.v","FALSE","FALSE"
ENDLIST
LIST "vga640x480::work","hdl\vga640x480.v","FALSE","FALSE"
ENDLIST
LIST "write_pos::work","hdl\write_pos.v","FALSE","FALSE"
ENDLIST
LIST "CAPB3II::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v","FALSE","FALSE"
ENDLIST
LIST "CAPB3O::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v","FALSE","FALSE"
ENDLIST
LIST "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3.v","FALSE","FALSE"
SUBBLOCK "CAPB3II::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3_muxptob3.v","FALSE","FALSE"
SUBBLOCK "CAPB3O::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3_iaddr_reg.v","FALSE","FALSE"
ENDLIST
LIST "BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
SUBBLOCK "BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
SUBBLOCK "BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
SUBBLOCK "BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_APBSLAVEEXT::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslaveext.v","FALSE","TRUE"
ENDLIST
LIST "BFM_MAIN::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_main.v","FALSE","TRUE"
ENDLIST
LIST "BFMA1l1OII::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_ahbtoapb.v","FALSE","TRUE"
ENDLIST
LIST "testbench::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\test\user\testbench.v","FALSE","TRUE"
SUBBLOCK "BFM_APB::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apb.v","FALSE","TRUE"
SUBBLOCK "BFM_APBSLAVE::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\amba_bfm\bfm_apbslave.v","FALSE","TRUE"
SUBBLOCK "CoreAPB3::COREAPB3_LIB","component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core_obfuscated\coreapb3.v","FALSE","FALSE"
ENDLIST
ENDLIST
LIST ActiveTestBenchList
ENDLIST
LIST IOTabList
ENDLIST
LIST FPTabList
ENDLIST
LIST TimingTabList
VALUE "component\work\DSWT_MSS\mss_tshell_syn.sdc"
ENDLIST
LIST FDCTabList
ENDLIST