DDR addr bus test fails

[rhaberkorn]

Booting a Seeed Studio Odyssey board with device trees generated from your IOC file results in the following error:

NOTICE:  CPU: STM32MP157CAC Rev.B
NOTICE:  Model: STMicroelectronics custom STM32CubeMX board - openstlinux-5.10-dunfell-mp1-21-11-17
WARNING: VDD unknown
INFO:    Reset reason (0x15):
INFO:      Power-on Reset (rst_por)
INFO:    FCONF: Reading TB_FW firmware configuration file from: 0x2ffe3000
INFO:    FCONF: Reading firmware configuration information for: stm32mp_io
INFO:    Using SDMMC
INFO:      Instance 1
INFO:    Boot used partition fsbl1
NOTICE:  BL2: v2.4-r1.0(debug):v2.4-dirty
NOTICE:  BL2: Built : 16:43:51, Nov 17 2020
INFO:    BL2: Doing platform setup
INFO:    RAM: DDR3-DDR3L 16bits 533000kHz
WARNING: Couldn't find property st,phy-cal in dtb
ERROR:   DDR addr bus test: can't access memory @ 0xc0000004
PANIC at PC : 0x2ffed853

Exception mode=0x00000016 at: 0x2ffed853

Did you encounter the same error? I think, you may have forgot to tune the DDR settings. See STM32CubeMX for STM32 configuration and initialization C code generation (p.192ff).

[rhaberkorn]

In fact, in order to tune the DDR settings, you need to flash the U-Boot SPL binaries according to the "basic" boot chain. This also does not work with the generated device trees, while it does work with the Odyssey upstream device trees (as can be patched in with the meta-st-odyssey layer). With your device trees, I simply get no output on the Debug UART (uart4).

Therefore I believe that a lot more is probably broken or incomplete in the IOC than only the DDR config.