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Investigate LLVM Codegen: Atomic Variables and Atomic Instructions #6

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skyzh opened this issue Feb 24, 2020 · 2 comments
Open

Investigate LLVM Codegen: Atomic Variables and Atomic Instructions #6

skyzh opened this issue Feb 24, 2020 · 2 comments
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@skyzh
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skyzh commented Feb 24, 2020

From my previous experience of RISC-V programming with Rust, I found that Rust won't generate amoswap instruction for spin lock. That's why I wrote __sync_lock_release and __sync_lock_test_and_set in arch.rs. On that, spin crate will generate non-atomic instruction for implementing the lock, which may cause significant slowdown. This affects all Atomic type in Rust.

@skyzh skyzh self-assigned this Feb 24, 2020
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skyzh commented Feb 25, 2020

Related pages: https://rcore-os.github.io/rCore_tutorial_doc/chapter3/part4.html

Maybe we should add '+a' option somewhere in Rust.

@skyzh skyzh added the bug Something isn't working label Feb 26, 2020
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skyzh commented Mar 18, 2020

It seems that rustc has already enabled atomic instruction.

riscv64gc target: https://github.com/rust-lang/rust/blob/master/src/librustc_target/spec/riscv64gc_unknown_none_elf.rs
riscv64imac target: https://github.com/rust-lang/rust/blob/master/src/librustc_target/spec/riscv64imac_unknown_none_elf.rs

Therefore, this should be a issue related to LLVM.

Author of one project similar to core-os proposed that: LLVM will generate lr/sc for atomic instructions. https://github.com/Jaic1/xv6-riscv-rust

Maybe we should wait for LLVM support for RISC-V atomic instruction.

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