-
Notifications
You must be signed in to change notification settings - Fork 24
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Investigate LLVM Codegen: Atomic Variables and Atomic Instructions #6
Comments
Related pages: https://rcore-os.github.io/rCore_tutorial_doc/chapter3/part4.html Maybe we should add '+a' option somewhere in Rust. |
It seems that rustc has already enabled atomic instruction. riscv64gc target: https://github.com/rust-lang/rust/blob/master/src/librustc_target/spec/riscv64gc_unknown_none_elf.rs Therefore, this should be a issue related to LLVM. Author of one project similar to core-os proposed that: LLVM will generate lr/sc for atomic instructions. https://github.com/Jaic1/xv6-riscv-rust Maybe we should wait for LLVM support for RISC-V atomic instruction. |
From my previous experience of RISC-V programming with Rust, I found that Rust won't generate
amoswap
instruction for spin lock. That's why I wrote__sync_lock_release
and__sync_lock_test_and_set
inarch.rs
. On that,spin
crate will generate non-atomic instruction for implementing the lock, which may cause significant slowdown. This affects allAtomic
type in Rust.The text was updated successfully, but these errors were encountered: