From 9cb481a83d9190ac4fd4d1900c9148ee1bd71613 Mon Sep 17 00:00:00 2001 From: Larry Ruckman Date: Wed, 23 Oct 2024 18:37:08 -0700 Subject: [PATCH] speed optimization --- .../dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd b/devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd index 84571493f7..090a1dddff 100644 --- a/devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd +++ b/devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd @@ -134,7 +134,7 @@ begin TPD_G => TPD_G, IN_POLARITY_G => '1', OUT_POLARITY_G => '0', - DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 2.0)) -- 500 ms reset + DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 100.0)) -- 10 ms reset port map ( arst => extRst, clk => stableClk, @@ -145,7 +145,7 @@ begin TPD_G => TPD_G, IN_POLARITY_G => '0', OUT_POLARITY_G => '1', - DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 2.0)) -- 500 ms reset + DURATION_G => getTimeRatio(STABLE_CLK_FREQ_G, 100.0)) -- 10 ms reset port map ( arst => extPhyRstN, clk => stableClk, @@ -155,7 +155,7 @@ begin generic map ( TPD_G => TPD_G, PHY_G => PHY_G, - DIV_G => getTimeRatio(STABLE_CLK_FREQ_G, 2*1.0E+6)) -- phyMdc = 1.0 MHz + DIV_G => getTimeRatio(STABLE_CLK_FREQ_G, 2*2.5E+6)) -- phyMdc = 2.5 MHz (nominal) port map ( clk => stableClk, rst => phyInitRst,