diff --git a/squishy/gateware/platform/resources/__init__.py b/squishy/gateware/platform/resources/__init__.py index 1fcbe034..a5621380 100644 --- a/squishy/gateware/platform/resources/__init__.py +++ b/squishy/gateware/platform/resources/__init__.py @@ -1,6 +1,8 @@ # SPDX-License-Identifier: BSD-3-Clause ''' +This module contains a collection of mostly Squishy-specific resources, for the generic SCSI bus resources see +:py:mod:`squishy.platform.resources.scsi`. ''' diff --git a/squishy/gateware/platform/resources/scsi.py b/squishy/gateware/platform/resources/scsi.py new file mode 100644 index 00000000..bd0468db --- /dev/null +++ b/squishy/gateware/platform/resources/scsi.py @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: BSD-3-Clause + +''' +This module contains resource definitions for the various SCSI bus types, as well as some Squishy-specific +SCSI interfaces. + + +''' + +from torii.build.dsl import Attrs, Pins, PinsN, Resource, Subsignal, DiffPairs, SubsigArgT, ResourceConn + +__all__ = ( + 'SquishySCSIPhy', +) + + +def SquishySCSIPhy( + name_or_number: str | int, number: int | None = None, *, + data_lower: str, data_upper: str, + atn: str, bsy: str, ack: str, rst: str, msg: str, sel: str, cd: str, req: str, io: str, + data_lower_dir: str, data_upper_dir: str, + target_dir: str, initiator_dir: str, bsy_dir: str, rst_dir: str, sel_dir: str, + scl: str, sda: str, + termpwr_en: str, prsnt: str, + lowspeed_ctrl: str, + phy_pwr_en: str, + conn: ResourceConn | None = None, attrs: Attrs | None = None +) -> Resource: + ios: list[SubsigArgT] = [ + # Data signals + Subsignal('data_lower', Pins(data_lower, dir = 'io', conn = conn, assert_width = 9)), + Subsignal('data_upper', Pins(data_upper, dir = 'io', conn = conn, assert_width = 9)), + Subsignal('atn', Pins(atn, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('bsy', Pins(bsy, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('ack', Pins(ack, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('rst', Pins(rst, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('msg', Pins(msg, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('sel', Pins(sel, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('cd', Pins(cd, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('req', Pins(req, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('io', Pins(io, dir = 'io', conn = conn, assert_width = 1)), + # Direction signals + Subsignal('data_lower_dir', Pins(data_lower_dir, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('data_upper_dir', Pins(data_upper_dir, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('trgt_dir', Pins(target_dir, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('init_dir', Pins(initiator_dir, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('bsy_dir', Pins(bsy_dir, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('rst_dir', Pins(rst_dir, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('sel_dir', Pins(sel_dir, dir = 'o', conn = conn, assert_width = 1)), + # PHY Control signals + Subsignal('scl', Pins(scl, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('sda', Pins(sda, dir = 'io', conn = conn, assert_width = 1)), + Subsignal('termpwr_en', Pins(termpwr_en, dir = 'o', conn = conn, assert_width = 1)), + Subsignal('prsnt', PinsN(prsnt, dir = 'i', conn = conn, assert_width = 1)), + Subsignal('ls_ctrl', Pins(lowspeed_ctrl, dir = 'io', conn = conn, assert_width = 6)), + Subsignal('pwr_en', Pins(phy_pwr_en, dir = 'o', conn = conn, assert_width = 1)), + ] + + if attrs is not None: + ios.append(attrs) + + return Resource.family(name_or_number, number, default_name = 'scsi_phy', ios = ios) diff --git a/squishy/gateware/platform/rev2.py b/squishy/gateware/platform/rev2.py index ae354129..918e7ba2 100644 --- a/squishy/gateware/platform/rev2.py +++ b/squishy/gateware/platform/rev2.py @@ -30,6 +30,7 @@ from . import SquishyPlatform from .resources import BankedHyperRAM, PDController, PhyADC, SquishySupervisor +from .resources.scsi import SquishySCSIPhy from ...core.flash import Geometry as FlashGeometry from ...core.config import ECP5PLLConfig, ECP5PLLOutput, FlashConfig @@ -272,42 +273,17 @@ class SquishyRev2(SquishyPlatform, ECP5Platform): attrs = Attrs(IO_TYPE = 'LVCMOS33') ), - # This will be replaced with a proper Squishy SCSI-PHY resource eventually:tm: - Resource('scsi_phy', 0, - # SCSI Bus # 0 1 2 3 4 5 6 7 P0 - Subsignal('data_lower', Pins('B5 A6 B6 A8 B8 A9 B9 A10 B10', dir = 'io')), - # 8 9 10 11 12 13 14 15 P1 - Subsignal('data_upper', Pins('A18 B18 A19 B19 A2 B1 A4 B2 A5', dir = 'io')), - Subsignal('atn', Pins('B11', dir = 'io')), - Subsignal('bsy', Pins('A11', dir = 'io')), - Subsignal('ack', Pins('C11', dir = 'io')), - Subsignal('rst', Pins('A13', dir = 'io')), - Subsignal('msg', Pins('B13', dir = 'io')), - Subsignal('sel', Pins('A15', dir = 'io')), - Subsignal('cd', Pins('B15', dir = 'io')), - Subsignal('req', Pins('A17', dir = 'io')), - Subsignal('io', Pins('B16', dir = 'io')), - - # PHY Direction Signals - Subsignal('data_lower_dir', Pins('B3', dir = 'o')), # DB[00..07], DP0 - Subsignal('data_upper_dir', Pins('C1', dir = 'o')), # DB[08..15], DP1 - Subsignal('trgt_dir', Pins('B17', dir = 'o')), # C/D, I/O, MSG, REQ - Subsignal('init_dir', Pins('B12', dir = 'o')), # ACK, ATN - Subsignal('bsy_dir', Pins('A12', dir = 'o')), # BSY - Subsignal('rst_dir', Pins('A14', dir = 'o')), # RST - Subsignal('sel_dir', Pins('A16', dir = 'o')), # SEL - - # PHY Control/Supervisory signals - Subsignal('scl', Pins('F2', dir = 'io')), - Subsignal('sda', Pins('E1', dir = 'io')), - Subsignal('termpwr_en', Pins('D1', dir = 'o')), - Subsignal('prsnt', PinsN('E2', dir = 'i')), - # Extra Signals - Subsignal('ls_ctrl', Pins('C2 C3 C16 C17 C14 C15', dir = 'io')), # LS_CTRL[0..5] Low-speed control lines - # This /might/ go better with the ADC? - Subsignal('pwr_en', PinsN('H2', dir = 'o')), - - Attrs(IO_TYPE = 'LVCMOS33', SLEWRATE = 'FAST') + SquishySCSIPhy('scsi_phy', 0, + # 0 1 2 3 4 5 6 7 P0 + data_lower = 'B5 A6 B6 A8 B8 A9 B9 A10 B10', + # 8 9 10 11 12 13 14 15 P1 + data_upper = 'A18 B18 A19 B19 A2 B1 A4 B2 A5', + atn = 'B11', bsy = 'A11', ack = 'C11', rst = 'A13', msg = 'B13', sel = 'A15', cd = 'B15', req = 'A17', io = '16', + data_lower_dir = 'B3', data_upper_dir = 'C1', + target_dir = 'B17', initiator_dir = 'B12', bsy_dir = 'A12', rst_dir = 'A14', sel_dir = 'A16', + scl = 'F2', sda = 'E1', termpwr_en = 'D1', prsnt = 'E2', + lowspeed_ctrl = 'C2 C3 C16 C17 C14 C15', phy_pwr_en = 'H2', + attrs = Attrs(IO_TYPE = 'LVCMOS33', SLEWRATE = 'FAST') ), # SCSI PHY Current ADC