From f3e229f545ba4c0acfddc8109c2a609135a2802b Mon Sep 17 00:00:00 2001
From: Steve Jenson <stevej@gmail.com>
Date: Thu, 24 Oct 2024 19:31:35 -0700
Subject: [PATCH] put whole design in reset

---
 test/test.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/test/test.py b/test/test.py
index d730e80..109ec73 100644
--- a/test/test.py
+++ b/test/test.py
@@ -18,6 +18,8 @@ async def test_rms_five_high_for_reset(dut):
         dut.ena.value = 1
         dut.ui_in.value = 0
         dut.uio_in.value = 0
+        dut.rst_n.value = 1
+        await ClockCycles(dut.clk, 1)
         dut.rst_n.value = 0
         await ClockCycles(dut.clk, 1)
         dut.rst_n.value = 1