[feature] Support for setting option bytes to STM32L41x_L42x

[ankurraji]

Feature Description

The support for setting option bytes for STM32L41x_L42x family is not present in the current version of st-link v1.8 command line tool. Although there is a configuration file for the processor family in the source code config/chips/L41x_L42x.chip , the values for option base and option size are set to 0, which results in the stlink_read_option_bytes32() and stlink_write_option_bytes32() not being executed.

file location - config/chips/L41x_L42x.chip
....
option_base 0x0
option_size 0x0

As the option bytes base is zero in the configuration file, the st link structure sl->option_base sets with a value 0. This results in the read/write operation exit every time with an error return code (-1).

file location - src/stlink-lib/option_bytes.c
....
int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) {
  if (sl->option_base == 0) {
    ELOG("Option bytes read is currently not supported for connected chip\n");
    return (-1);
  }
.....

• I made serious effort to avoid creating duplicate or nearly similar issue
• Programmer/board type: [STLINK V2 and V3 SET]
• Operating system an version: [Linux and Windows]
• stlink tools version and/or git commit hash: [v1.8]
• stlink commandline tool name: [st-flash]
• Target chip (and board, if applicable): [STM32L41x_L42x]

Debug Logs:

Here are some debug logs for the read operation if it is helpful.

Debug command line output: st-flash --debug --area=option read

st-flash 1.8.0
2024-07-08T17:52:14 DEBUG common.c: *** looking up stlink version ***
2024-07-08T17:52:14 DEBUG common.c: st vid         = 0x0483 (expect 0x0483)
2024-07-08T17:52:14 DEBUG common.c: stlink pid     = 0x374f
2024-07-08T17:52:14 DEBUG common.c: stlink version = 0x3
2024-07-08T17:52:14 DEBUG common.c: jtag version   = 0x9
2024-07-08T17:52:14 DEBUG common.c: swim version   = 0x1
2024-07-08T17:52:14 DEBUG common.c: stlink current mode: mass
2024-07-08T17:52:14 DEBUG usb.c: JTAG/SWD freq set to 0
2024-07-08T17:52:14 DEBUG common.c: stlink current mode: mass
2024-07-08T17:52:14 DEBUG common.c: *** stlink_enter_swd_mode ***
2024-07-08T17:52:14 DEBUG common.c: Loading device parameters....
2024-07-08T17:52:14 DEBUG common.c: *** stlink_core_id ***
2024-07-08T17:52:14 DEBUG common.c: core_id = 0x2ba01477
2024-07-08T17:52:14 DEBUG read_write.c: *** stlink_read_debug32  0x410fc241 at 0xe000ed00
2024-07-08T17:52:14 DEBUG read_write.c: *** stlink_read_debug32  0x10006464 at 0xe0042000
2024-07-08T17:52:14 DEBUG chipid.c: detected chip_id parameters
2024-07-08T17:52:14 DEBUG chipid.c: # Device Type: STM32L41x_L42x
2024-07-08T17:52:14 DEBUG chipid.c: # Reference Manual: RM0394
2024-07-08T17:52:14 DEBUG chipid.c: #
2024-07-08T17:52:14 DEBUG chipid.c: chip_id 0x464
2024-07-08T17:52:14 DEBUG chipid.c: flash_type 10
2024-07-08T17:52:14 DEBUG chipid.c: flash_size_reg 0x1fff75e0
2024-07-08T17:52:14 DEBUG chipid.c: flash_pagesize 0x800
2024-07-08T17:52:14 DEBUG chipid.c: sram_size 0xa000
2024-07-08T17:52:14 DEBUG chipid.c: bootrom_base 0x1fff0000
2024-07-08T17:52:14 DEBUG chipid.c: bootrom_size 0x7000
2024-07-08T17:52:14 DEBUG chipid.c: option_base 0x0
2024-07-08T17:52:14 DEBUG chipid.c: option_size 0x0
2024-07-08T17:52:14 DEBUG chipid.c: flags 2
2024-07-08T17:52:14 DEBUG chipid.c: otp_base 0
2024-07-08T17:52:14 DEBUG chipid.c: otp_size 0
2024-07-08T17:52:14 DEBUG read_write.c: *** stlink_read_debug32  0xffff0040 at 0x1fff75e0
2024-07-08T17:52:14 INFO common.c: STM32L41x_L42x: 40 KiB SRAM, 64 KiB flash in at least 2 KiB pages.
2024-07-08T17:52:14 DEBUG common.c: *** stlink_force_debug_mode ***
2024-07-08T17:52:14 DEBUG read_write.c: *** stlink_read_debug32  0x00001800 at 0xe0042008
2024-07-08T17:52:14 DEBUG read_write.c: *** stlink_write_debug32 0x00001800 to 0xe0042008
2024-07-08T17:52:14 DEBUG common.c: *** stlink_status ***
2024-07-08T17:52:14 DEBUG usb.c: core status: 01030003
2024-07-08T17:52:14 DEBUG common.c:   core status: halted
2024-07-08T17:52:14 DEBUG flash.c: @@@@ Read 0 (0) option bytes from          0
2024-07-08T17:52:14 ERROR option_bytes.c: Option bytes read is currently not supported for connected chip
could not read option bytes (-1)
2024-07-08T17:52:14 DEBUG common.c: *** stlink_exit_debug_mode ***
2024-07-08T17:52:14 DEBUG read_write.c: *** stlink_write_debug32 0xa05f0000 to 0xe000edf0
2024-07-08T17:52:14 DEBUG common.c: *** stlink_close ***

Expected :

It would be great to have support for st-link tool to set option bytes for STM32L41x_L42x MCU.

Thank you for taking the time ❤️