diff --git a/.ci/riscv-tests.sh b/.ci/riscv-tests.sh index 2b13c286..abf113c4 100755 --- a/.ci/riscv-tests.sh +++ b/.ci/riscv-tests.sh @@ -13,6 +13,7 @@ make clean make arch-test RISCV_DEVICE=I || exit 1 make arch-test RISCV_DEVICE=IM || exit 1 make arch-test RISCV_DEVICE=IC || exit 1 +make arch-test RISCV_DEVICE=FCZicsr || exit 1 make arch-test RISCV_DEVICE=IZifencei || exit 1 make arch-test RISCV_DEVICE=IZicsr || exit 1 make arch-test RISCV_DEVICE=FZicsr || exit 1 diff --git a/README.md b/README.md index 2946b716..43ef84b8 100644 --- a/README.md +++ b/README.md @@ -75,7 +75,7 @@ The image containing all the necessary tools for development and testing can be `rv32emu` is configurable, and you can override the below variable(s) to fit your expectations: * `ENABLE_EXT_M`: Standard Extension for Integer Multiplication and Division * `ENABLE_EXT_A`: Standard Extension for Atomic Instructions -* `ENABLE_EXT_C`: Standard Extension for Compressed Instructions (RV32C.F excluded) +* `ENABLE_EXT_C`: Standard Extension for Compressed Instructions (RV32C.D excluded) * `ENABLE_EXT_F`: Standard Extension for Single-Precision Floating Point Instructions * `ENABLE_Zicsr`: Control and Status Register (CSR) * `ENABLE_Zifencei`: Instruction-Fetch Fence diff --git a/mk/riscv-arch-test.mk b/mk/riscv-arch-test.mk index 5ab2409b..20e11037 100644 --- a/mk/riscv-arch-test.mk +++ b/mk/riscv-arch-test.mk @@ -1,9 +1,14 @@ ARCH_TEST_DIR ?= tests/riscv-arch-test +ARCH_TEST_SUITE ?= $(ARCH_TEST_DIR)/riscv-test-suite export RISCV_TARGET := tests/arch-test-target export TARGETDIR := $(shell pwd) export WORK := $(TARGETDIR)/build/arch-test export RISCV_DEVICE ?= IMCZicsrZifencei +ifeq ($(RISCV_DEVICE),FCZicsr) +ARCH_TEST_SUITE := tests/rv32fc-test-suite +endif + arch-test: $(BIN) ifeq ($(CROSS_COMPILE),) $(error GNU Toolchain for RISC-V is required to build architecture tests. Please check package installation) @@ -12,5 +17,5 @@ endif $(Q)python3 -B $(RISCV_TARGET)/setup.py --riscv_device=$(RISCV_DEVICE) $(Q)riscof run --work-dir=$(WORK) \ --config=$(RISCV_TARGET)/config.ini \ - --suite=$(ARCH_TEST_DIR)/riscv-test-suite \ - --env=$(ARCH_TEST_DIR)/riscv-test-suite/env + --suite=$(ARCH_TEST_SUITE) \ + --env=$(ARCH_TEST_DIR)/riscv-test-suite/env diff --git a/src/decode.c b/src/decode.c index 2003e6f8..f0c51373 100644 --- a/src/decode.c +++ b/src/decode.c @@ -1668,15 +1668,92 @@ static inline bool op_cbnez(rv_insn_t *ir, const uint32_t insn) #define op_cbnez OP_UNIMP #endif /* RV32_HAS(EXT_C) */ -/* TODO: RV32C.F support */ -#define op_cfldsp OP_UNIMP -#define op_cflwsp OP_UNIMP -#define op_cfswsp OP_UNIMP -#define op_cfsdsp OP_UNIMP -#define op_cfld OP_UNIMP -#define op_cflw OP_UNIMP +#if RV32_HAS(EXT_C) && RV32_HAS(EXT_F) +/* C.FLWSP: CI-format + * 15 13 12 11 7 6 2 1 0 + * | funct3 | imm | rd | imm | op | + */ +static inline bool op_cflwsp(rv_insn_t *ir, const uint32_t insn) +{ + /* inst funct3 imm rd imm op + * -------+------+-------+-----+-------------+-- + * C.FLWSP 001 uimm[5] rd uimm[4:2|7:6] 10 + */ + uint16_t tmp = 0; + tmp |= (insn & 0x70) >> 2; + tmp |= (insn & 0x0c) << 4; + tmp |= (insn & 0x1000) >> 7; + ir->imm = tmp; + ir->rd = c_decode_rd(insn); + ir->opcode = rv_insn_cflwsp; + return true; +} + +/* C.FSWSP: CSS-Format + * 15 13 12 7 6 2 1 0 + * | funct3 | imm | rs2 | op | + */ +static inline bool op_cfswsp(rv_insn_t *ir, const uint32_t insn) +{ + /* inst funct3 imm rs2 op + * -------+------+-------------+---+-- + * C.FSWSP 111 uimm[5:2|7:6] rs2 10 + */ + ir->imm = (insn & 0x1e00) >> 7 | (insn & 0x180) >> 1; + ir->rs2 = c_decode_rs2(insn); + ir->opcode = rv_insn_cfswsp; + return true; +} + +/* C.FLW: CL-format + * 15 13 12 10 9 7 6 5 4 2 1 0 + * | funct3 | imm | rs1' | imm | rd' | op | + */ +static inline bool op_cflw(rv_insn_t *ir, const uint32_t insn) +{ + /* inst funct3 imm rs1' imm rd' op + * -----+------+---------+----+---------+---+-- + * C.FLW 010 uimm[5:3] rs1' uimm[7:6] rd' 00 + */ + uint16_t tmp = 0; + tmp |= (insn & 0b0000000001000000) >> 4; + tmp |= (insn & FC_IMM_12_10) >> 7; + tmp |= (insn & 0b0000000000100000) << 1; + ir->imm = tmp; + ir->rd = c_decode_rdc(insn) | 0x08; + ir->rs1 = c_decode_rs1c(insn) | 0x08; + ir->opcode = rv_insn_cflw; + return true; +} + +/* C.FSW: CS-format + * 15 13 12 10 9 7 6 5 4 2 1 0 + * | funct3 | imm | rs1' | imm | rs2' | op | + */ +static inline bool op_cfsw(rv_insn_t *ir, const uint32_t insn) +{ + /* inst funct3 imm rs1' imm rs2' op + * -----+------+---------+----+---------+----+-- + * C.FSW 110 uimm[5:3] rs1' uimm[2|6] rs2' 00 + */ + uint32_t tmp = 0; + /* ....xxxx....xxxx */ + tmp |= (insn & 0b0000000001000000) >> 4; + tmp |= (insn & FC_IMM_12_10) >> 7; + tmp |= (insn & 0b0000000000100000) << 1; + ir->imm = tmp; + ir->rs1 = c_decode_rs1c(insn) | 0x08; + ir->rs2 = c_decode_rs2c(insn) | 0x08; + ir->opcode = rv_insn_cfsw; + return true; +} + +#else /* !(RV32_HAS(EXT_C) && RV32_HAS(EXT_F)) */ #define op_cfsw OP_UNIMP -#define op_cfsd OP_UNIMP +#define op_cflw OP_UNIMP +#define op_cfswsp OP_UNIMP +#define op_cflwsp OP_UNIMP +#endif /* RV32_HAS(EXT_C) && RV32_HAS(EXT_F) */ /* handler for all unimplemented opcodes */ static inline bool op_unimp(rv_insn_t *ir UNUSED, uint32_t insn UNUSED) @@ -1710,11 +1787,11 @@ bool rv_decode(rv_insn_t *ir, uint32_t insn) static const decode_t rvc_jump_table[] = { // 00 01 10 11 OP(caddi4spn), OP(caddi), OP(cslli), OP(unimp), // 000 - OP(cfld), OP(cjal), OP(cfldsp), OP(unimp), // 001 + OP(unimp), OP(cjal), OP(unimp), OP(unimp), // 001 OP(clw), OP(cli), OP(clwsp), OP(unimp), // 010 OP(cflw), OP(clui), OP(cflwsp), OP(unimp), // 011 OP(unimp), OP(cmisc_alu), OP(ccr), OP(unimp), // 100 - OP(cfsd), OP(cj), OP(cfsdsp), OP(unimp), // 101 + OP(unimp), OP(cj), OP(unimp), OP(unimp), // 101 OP(csw), OP(cbeqz), OP(cswsp), OP(unimp), // 110 OP(cfsw), OP(cbnez), OP(cfswsp), OP(unimp), // 111 }; diff --git a/src/decode.h b/src/decode.h index 11458cf4..86b75ada 100644 --- a/src/decode.h +++ b/src/decode.h @@ -176,6 +176,13 @@ enum op_field { _(cjalr, 1, 2, 1, ENC(rs1, rs2, rd)) \ _(cadd, 0, 2, 1, ENC(rs1, rs2, rd)) \ _(cswsp, 0, 2, 1, ENC(rs2)) \ + /* RV32FC Instruction */ \ + IIF(RV32_HAS(EXT_F))( \ + _(cflwsp, 0, 2, 1, ENC(rd)) \ + _(cfswsp, 0, 2, 1, ENC(rs2)) \ + _(cflw, 0, 2, 1, ENC(rs1, rd)) \ + _(cfsw, 0, 2, 1, ENC(rs1, rs2)) \ + ) \ ) /* clang-format on */ diff --git a/src/rv32_constopt.c b/src/rv32_constopt.c index f1d2321b..14a957b3 100644 --- a/src/rv32_constopt.c +++ b/src/rv32_constopt.c @@ -979,3 +979,19 @@ CONSTOPT(cadd, { /* C.SWSP */ CONSTOPT(cswsp, {}) #endif + +/* RV32FC Standard Extension */ + +#if RV32_HAS(EXT_F) && RV32_HAS(EXT_C) +/* C.FLWSP */ +CONSTOPT(cflwsp, {}) + +/* C.FSWSP */ +CONSTOPT(cfswsp, {}) + +/* C.FLW */ +CONSTOPT(cflw, {}) + +/* C.FSW */ +CONSTOPT(cfsw, {}) +#endif diff --git a/src/rv32_template.c b/src/rv32_template.c index c8967fb2..a2b2bb2d 100644 --- a/src/rv32_template.c +++ b/src/rv32_template.c @@ -2276,3 +2276,53 @@ RVOP( st, S32, TMP1, TMP0, 0; })) #endif + +#if RV32_HAS(EXT_C) && RV32_HAS(EXT_F) +/* C.FLWSP */ +RVOP( + cflwsp, + { + const uint32_t addr = rv->X[rv_reg_sp] + ir->imm; + RV_EXC_MISALIGN_HANDLER(3, load, false, 1); + rv->F[ir->rd].v = rv->io.mem_read_w(addr); + }, + GEN({ + assert; /* FIXME: Implement */ + })) + +/* C.FSWSP */ +RVOP( + cfswsp, + { + const uint32_t addr = rv->X[rv_reg_sp] + ir->imm; + RV_EXC_MISALIGN_HANDLER(3, store, false, 1); + rv->io.mem_write_w(addr, rv->F[ir->rs2].v); + }, + GEN({ + assert; /* FIXME: Implement */ + })) + +/* C.FLW */ +RVOP( + cflw, + { + const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm; + RV_EXC_MISALIGN_HANDLER(3, load, false, 1); + rv->F[ir->rd].v = rv->io.mem_read_w(addr); + }, + GEN({ + assert; /* FIXME: Implement */ + })) + +/* C.FSW */ +RVOP( + cfsw, + { + const uint32_t addr = rv->X[ir->rs1] + (uint32_t) ir->imm; + RV_EXC_MISALIGN_HANDLER(3, store, false, 1); + rv->io.mem_write_w(addr, rv->F[ir->rs2].v); + }, + GEN({ + assert; /* FIXME: Implement */ + })) +#endif diff --git a/tests/rv32fc-test-suite/cflw-01.S b/tests/rv32fc-test-suite/cflw-01.S new file mode 100644 index 00000000..406e811f --- /dev/null +++ b/tests/rv32fc-test-suite/cflw-01.S @@ -0,0 +1,180 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Fri Jan 5 14:22:19 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/rv32fc_1.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flw instruction of the RISC-V RV32FC extension for the cflw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*F.*C.*);def TEST_CASE_1=True;",cflw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x3,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f15, rs1==x15,imm_val == 0, +// opcode: c.flw; op1:x15; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,89,x15,f15,0x0,c.flw,0,x4) + +inst_1: +// rd==f10, rs1==x14,imm_val == 0 and fcsr == 0, +// opcode: c.flw; op1:x14; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x14,f10,0x0,c.flw,0,x4) + +inst_2: +// rd==f13, rs1==x9,imm_val > 0, +// opcode: c.flw; op1:x9; dest:f13; immval:0x24; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,139,x9,f13,0x24,c.flw,0,x4) + +inst_3: +// rd==f12, rs1==x13,imm_val > 0 and fcsr == 0, imm_val == 108 +// opcode: c.flw; op1:x13; dest:f12; immval:0x6c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,0,x13,f12,0x6c,c.flw,0,x4) + +inst_4: +// rd==f14, rs1==x11,imm_val == 84, +// opcode: c.flw; op1:x11; dest:f14; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,50,x11,f14,0x54,c.flw,0,x4) + +inst_5: +// rd==f8, rs1==x12,imm_val == 120, +// opcode: c.flw; op1:x12; dest:f8; immval:0x78; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,100,x12,f8,0x78,c.flw,0,x4) + +inst_6: +// rd==f11, rs1==x8,imm_val == 116, +// opcode: c.flw; op1:x8; dest:f11; immval:0x74; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,34,x8,f11,0x74,c.flw,0,x4) + +inst_7: +// rd==f9, rs1==x10,imm_val == 92, +// opcode: c.flw; op1:x10; dest:f9; immval:0x5c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,116,x10,f9,0x5c,c.flw,0,x4) + +inst_8: +// imm_val == 60, +// opcode: c.flw; op1:x15; dest:f15; immval:0x3c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,146,x15,f15,0x3c,c.flw,0,x4) + +inst_9: +// imm_val == 4, +// opcode: c.flw; op1:x15; dest:f15; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,63,x15,f15,0x4,c.flw,0,x4) + +inst_10: +// imm_val == 8, +// opcode: c.flw; op1:x15; dest:f15; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,45,x15,f15,0x8,c.flw,0,x4) + +inst_11: +// imm_val == 16, +// opcode: c.flw; op1:x15; dest:f15; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,76,x15,f15,0x10,c.flw,0,x4) + +inst_12: +// imm_val == 32, +// opcode: c.flw; op1:x15; dest:f15; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,41,x15,f15,0x20,c.flw,0,x4) + +inst_13: +// imm_val == 64, +// opcode: c.flw; op1:x15; dest:f15; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,88,x15,f15,0x40,c.flw,0,x4) + +inst_14: +// imm_val == 40, +// opcode: c.flw; op1:x15; dest:f15; immval:0x28; align:0; flagreg:x4 +TEST_LOAD_F(x1,x2,52,x15,f15,0x28,c.flw,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: + + + + + + + + + + + + + + + +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 15*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/tests/rv32fc-test-suite/cflwsp-01.S b/tests/rv32fc-test-suite/cflwsp-01.S new file mode 100644 index 00000000..966b6471 --- /dev/null +++ b/tests/rv32fc-test-suite/cflwsp-01.S @@ -0,0 +1,248 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Fri Jan 5 17:13:10 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/rv32fc_1.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.flwsp instruction of the RISC-V RV32FC extension for the cflwsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*F.*C.*);def TEST_CASE_1=True;",cflwsp) + +RVTEST_FP_ENABLE() +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==f10,imm_val == 0, +// opcode: c.flwsp; dest:f10; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,18,x2,f10,0x0,c.flwsp,0,x4) + +inst_1: +// rd==f4,imm_val == 0 and fcsr == 0, +// opcode: c.flwsp; dest:f4; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f4,0x0,c.flwsp,0,x4) + +inst_2: +// rd==f26,imm_val > 0, +// opcode: c.flwsp; dest:f26; immval:0x2c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,114,x2,f26,0x2c,c.flwsp,0,x4) + +inst_3: +// rd==f29,imm_val > 0 and fcsr == 0, imm_val == 16 +// opcode: c.flwsp; dest:f29; immval:0x10; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f29,0x10,c.flwsp,0,x4) + +inst_4: +// rd==f20,imm_val == 248, +// opcode: c.flwsp; dest:f20; immval:0xf8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,24,x2,f20,0xf8,c.flwsp,0,x4) + +inst_5: +// rd==f5,imm_val == 244, +// opcode: c.flwsp; dest:f5; immval:0xf4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,116,x2,f5,0xf4,c.flwsp,0,x4) + +inst_6: +// rd==f12,imm_val == 236, +// opcode: c.flwsp; dest:f12; immval:0xec; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,94,x2,f12,0xec,c.flwsp,0,x4) + +inst_7: +// rd==f27,imm_val == 220, +// opcode: c.flwsp; dest:f27; immval:0xdc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,57,x2,f27,0xdc,c.flwsp,0,x4) + +inst_8: +// rd==f9,imm_val == 188, +// opcode: c.flwsp; dest:f9; immval:0xbc; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,73,x2,f9,0xbc,c.flwsp,0,x4) + +inst_9: +// rd==f6,imm_val == 124, +// opcode: c.flwsp; dest:f6; immval:0x7c; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,22,x2,f6,0x7c,c.flwsp,0,x4) + +inst_10: +// rd==f23,imm_val == 84, +// opcode: c.flwsp; dest:f23; immval:0x54; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,81,x2,f23,0x54,c.flwsp,0,x4) + +inst_11: +// rd==f31,imm_val == 168, +// opcode: c.flwsp; dest:f31; immval:0xa8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,109,x2,f31,0xa8,c.flwsp,0,x4) + +inst_12: +// rd==f11,imm_val == 4, +// opcode: c.flwsp; dest:f11; immval:0x4; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,140,x2,f11,0x4,c.flwsp,0,x4) + +inst_13: +// rd==f14,imm_val == 8, +// opcode: c.flwsp; dest:f14; immval:0x8; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,64,x2,f14,0x8,c.flwsp,0,x4) + +inst_14: +// rd==f25,imm_val == 32, +// opcode: c.flwsp; dest:f25; immval:0x20; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,42,x2,f25,0x20,c.flwsp,0,x4) + +inst_15: +// rd==f30,imm_val == 64, +// opcode: c.flwsp; dest:f30; immval:0x40; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,153,x2,f30,0x40,c.flwsp,0,x4) + +inst_16: +// rd==f21,imm_val == 128, +// opcode: c.flwsp; dest:f21; immval:0x80; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,46,x2,f21,0x80,c.flwsp,0,x4) + +inst_17: +// rd==f16, +// opcode: c.flwsp; dest:f16; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f16,0x0,c.flwsp,0,x4) + +inst_18: +// rd==f17, +// opcode: c.flwsp; dest:f17; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f17,0x0,c.flwsp,0,x4) + +inst_19: +// rd==f24, +// opcode: c.flwsp; dest:f24; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f24,0x0,c.flwsp,0,x4) + +inst_20: +// rd==f22, +// opcode: c.flwsp; dest:f22; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f22,0x0,c.flwsp,0,x4) + +inst_21: +// rd==f3, +// opcode: c.flwsp; dest:f3; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f3,0x0,c.flwsp,0,x4) + +inst_22: +// rd==f18, +// opcode: c.flwsp; dest:f18; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f18,0x0,c.flwsp,0,x4) + +inst_23: +// rd==f8, +// opcode: c.flwsp; dest:f8; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f8,0x0,c.flwsp,0,x4) + +inst_24: +// rd==f19, +// opcode: c.flwsp; dest:f19; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f19,0x0,c.flwsp,0,x4) + +inst_25: +// rd==f28, +// opcode: c.flwsp; dest:f28; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f28,0x0,c.flwsp,0,x4) + +inst_26: +// rd==f2, +// opcode: c.flwsp; dest:f2; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f2,0x0,c.flwsp,0,x4) + +inst_27: +// rd==f7, +// opcode: c.flwsp; dest:f7; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f7,0x0,c.flwsp,0,x4) + +inst_28: +// rd==f0, +// opcode: c.flwsp; dest:f0; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f0,0x0,c.flwsp,0,x4) + +inst_29: +// rd==f13, +// opcode: c.flwsp; dest:f13; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f13,0x0,c.flwsp,0,x4) + +inst_30: +// rd==f1, +// opcode: c.flwsp; dest:f1; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f1,0x0,c.flwsp,0,x4) + +inst_31: +// rd==f15, +// opcode: c.flwsp; dest:f15; immval:0x0; align:0; flagreg:x4 +TEST_LOAD_F(x1,x9,0,x2,f15,0x0,c.flwsp,0,x4) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 32*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/tests/rv32fc-test-suite/cfsw-01.S b/tests/rv32fc-test-suite/cfsw-01.S new file mode 100644 index 00000000..b7752985 --- /dev/null +++ b/tests/rv32fc-test-suite/cfsw-01.S @@ -0,0 +1,642 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Fri Jan 5 18:43:51 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/rv32fc_1.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fsw instruction of the RISC-V RV32FC extension for the cfsw covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*F.*C.*);def TEST_CASE_1=True;",cfsw) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rs2, rs1==x15, rs2==f11,imm_val == 0, rs2_val == -2 +// opcode:c.fsw; op1:x15; op2:f11; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x17,20,x15,f11,0x0,0*XLEN/8,c.fsw,0,x3,x2, 0*FLEN/8) + +inst_1: +// rs1==x9, rs2==f13,imm_val == 0 and fcsr == 0, rs2_val == 2097152 +// opcode:c.fsw; op1:x9; op2:f13; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x17,0,x9,f13,0x0,1*XLEN/8,c.fsw,0,x3,x2, 1*FLEN/8) + +inst_2: +// rs1==x11, rs2==f12,imm_val > 0, imm_val == 64, rs2_val == 16 +// opcode:c.fsw; op1:x11; op2:f12; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x17,85,x11,f12,0x40,2*XLEN/8,c.fsw,0,x3,x2, 2*FLEN/8) + +inst_3: +// rs1==x10, rs2==f8,imm_val > 0 and fcsr == 0, imm_val == 108, rs2_val == 33554432 +// opcode:c.fsw; op1:x10; op2:f8; immval:0x6c; align:0; flagreg:x3; +// valreg: x2; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x17,0,x10,f8,0x6c,3*XLEN/8,c.fsw,0,x3,x2, 3*FLEN/8) + +inst_4: +// rs1==x12, rs2==f15,rs2_val == (-2**(xlen-1)), imm_val == 92, rs2_val == -2147483648 +// opcode:c.fsw; op1:x12; op2:f15; immval:0x5c; align:0; flagreg:x3; +// valreg: x2; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x17,154,x12,f15,0x5c,4*XLEN/8,c.fsw,0,x3,x2, 4*FLEN/8) + +inst_5: +// rs1==x8, rs2==f9,rs2_val == (2**(xlen-1)-1), rs2_val == 2147483647, imm_val == 32 +// opcode:c.fsw; op1:x8; op2:f9; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x17,111,x8,f9,0x20,5*XLEN/8,c.fsw,0,x3,x2, 5*FLEN/8) + +inst_6: +// rs1==x14, rs2==f10,rs2_val == -3, +// opcode:c.fsw; op1:x14; op2:f10; immval:0x44; align:0; flagreg:x3; +// valreg: x2; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x17,4,x14,f10,0x44,6*XLEN/8,c.fsw,0,x3,x2, 6*FLEN/8) + +inst_7: +// rs1==x13, rs2==f14,rs2_val == -5, imm_val == 16 +// opcode:c.fsw; op1:x13; op2:f14; immval:0x10; align:0; flagreg:x3; +// valreg: x2; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x17,58,x13,f14,0x10,7*XLEN/8,c.fsw,0,x3,x2, 7*FLEN/8) + +inst_8: +// rs2_val == -9, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x38; align:0; flagreg:x3; +// valreg: x2; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x17,32,x15,f15,0x38,8*XLEN/8,c.fsw,0,x3,x2, 8*FLEN/8) + +inst_9: +// rs2_val == -17, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x17,77,x15,f15,0x14,9*XLEN/8,c.fsw,0,x3,x2, 9*FLEN/8) + +inst_10: +// rs2_val == -33, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x17,88,x15,f15,0x14,10*XLEN/8,c.fsw,0,x3,x2, 10*FLEN/8) + +inst_11: +// rs2_val == -65, +// opcode:c.fsw; op1:x15; op2:f15; immval:0xc; align:0; flagreg:x3; +// valreg: x2; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x17,140,x15,f15,0xc,11*XLEN/8,c.fsw,0,x3,x2, 11*FLEN/8) + +inst_12: +// rs2_val == -129, +// opcode:c.fsw; op1:x15; op2:f15; immval:0xc; align:0; flagreg:x3; +// valreg: x2; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x17,116,x15,f15,0xc,12*XLEN/8,c.fsw,0,x3,x2, 12*FLEN/8) + +inst_13: +// rs2_val == -257, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x17,119,x15,f15,0x40,13*XLEN/8,c.fsw,0,x3,x2, 13*FLEN/8) + +inst_14: +// rs2_val == -513, imm_val == 116 +// opcode:c.fsw; op1:x15; op2:f15; immval:0x74; align:0; flagreg:x3; +// valreg: x2; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x17,109,x15,f15,0x74,14*XLEN/8,c.fsw,0,x3,x2, 14*FLEN/8) + +inst_15: +// rs2_val == -1025, imm_val == 40 +// opcode:c.fsw; op1:x15; op2:f15; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x17,50,x15,f15,0x28,15*XLEN/8,c.fsw,0,x3,x2, 15*FLEN/8) + +inst_16: +// rs2_val == -2049, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x2c; align:0; flagreg:x3; +// valreg: x2; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x17,118,x15,f15,0x2c,16*XLEN/8,c.fsw,0,x3,x2, 16*FLEN/8) + +inst_17: +// rs2_val == -4097, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x4c; align:0; flagreg:x3; +// valreg: x2; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x17,113,x15,f15,0x4c,17*XLEN/8,c.fsw,0,x3,x2, 17*FLEN/8) + +inst_18: +// rs2_val == -8193, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x1c; align:0; flagreg:x3; +// valreg: x2; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x17,66,x15,f15,0x1c,18*XLEN/8,c.fsw,0,x3,x2, 18*FLEN/8) + +inst_19: +// rs2_val == -16385, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x24; align:0; flagreg:x3; +// valreg: x2; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x17,120,x15,f15,0x24,19*XLEN/8,c.fsw,0,x3,x2, 19*FLEN/8) + +inst_20: +// rs2_val == -32769, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x17,102,x15,f15,0x0,20*XLEN/8,c.fsw,0,x3,x2, 20*FLEN/8) + +inst_21: +// rs2_val == -65537, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x17,124,x15,f15,0x40,21*XLEN/8,c.fsw,0,x3,x2, 21*FLEN/8) + +inst_22: +// rs2_val == -131073, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x17,6,x15,f15,0x20,22*XLEN/8,c.fsw,0,x3,x2, 22*FLEN/8) + +inst_23: +// rs2_val == -262145, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x1c; align:0; flagreg:x3; +// valreg: x2; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x17,14,x15,f15,0x1c,23*XLEN/8,c.fsw,0,x3,x2, 23*FLEN/8) + +inst_24: +// rs2_val == -524289, imm_val == 4 +// opcode:c.fsw; op1:x15; op2:f15; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x17,46,x15,f15,0x4,24*XLEN/8,c.fsw,0,x3,x2, 24*FLEN/8) + +inst_25: +// rs2_val == -1048577, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x17,148,x15,f15,0x4,25*XLEN/8,c.fsw,0,x3,x2, 25*FLEN/8) + +inst_26: +// rs2_val == -2097153, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x17,130,x15,f15,0x40,26*XLEN/8,c.fsw,0,x3,x2, 26*FLEN/8) + +inst_27: +// rs2_val == -4194305, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x2c; align:0; flagreg:x3; +// valreg: x2; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x17,125,x15,f15,0x2c,27*XLEN/8,c.fsw,0,x3,x2, 27*FLEN/8) + +inst_28: +// rs2_val == -8388609, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x1c; align:0; flagreg:x3; +// valreg: x2; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x17,155,x15,f15,0x1c,28*XLEN/8,c.fsw,0,x3,x2, 28*FLEN/8) + +inst_29: +// rs2_val == -16777217, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x30; align:0; flagreg:x3; +// valreg: x2; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x17,155,x15,f15,0x30,29*XLEN/8,c.fsw,0,x3,x2, 29*FLEN/8) + +inst_30: +// rs2_val == -33554433, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x24; align:0; flagreg:x3; +// valreg: x2; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x17,45,x15,f15,0x24,30*XLEN/8,c.fsw,0,x3,x2, 30*FLEN/8) + +inst_31: +// rs2_val == -67108865, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x74; align:0; flagreg:x3; +// valreg: x2; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x17,115,x15,f15,0x74,31*XLEN/8,c.fsw,0,x3,x2, 31*FLEN/8) + +inst_32: +// rs2_val == -134217729, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 32*FLEN/8 +TEST_STORE_F(x1,x17,77,x15,f15,0x4,32*XLEN/8,c.fsw,0,x3,x2, 32*FLEN/8) + +inst_33: +// rs2_val == -268435457, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 33*FLEN/8 +TEST_STORE_F(x1,x17,115,x15,f15,0x14,33*XLEN/8,c.fsw,0,x3,x2, 33*FLEN/8) + +inst_34: +// rs2_val == -536870913, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x74; align:0; flagreg:x3; +// valreg: x2; valoffset: 34*FLEN/8 +TEST_STORE_F(x1,x17,21,x15,f15,0x74,34*XLEN/8,c.fsw,0,x3,x2, 34*FLEN/8) + +inst_35: +// rs2_val == -1073741825, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x5c; align:0; flagreg:x3; +// valreg: x2; valoffset: 35*FLEN/8 +TEST_STORE_F(x1,x17,116,x15,f15,0x5c,35*XLEN/8,c.fsw,0,x3,x2, 35*FLEN/8) + +inst_36: +// imm_val == 120, rs2_val == 65536 +// opcode:c.fsw; op1:x15; op2:f15; immval:0x78; align:0; flagreg:x3; +// valreg: x2; valoffset: 36*FLEN/8 +TEST_STORE_F(x1,x17,149,x15,f15,0x78,36*XLEN/8,c.fsw,0,x3,x2, 36*FLEN/8) + +inst_37: +// imm_val == 60, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x3c; align:0; flagreg:x3; +// valreg: x2; valoffset: 37*FLEN/8 +TEST_STORE_F(x1,x17,17,x15,f15,0x3c,37*XLEN/8,c.fsw,0,x3,x2, 37*FLEN/8) + +inst_38: +// rs2_val == 1, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 38*FLEN/8 +TEST_STORE_F(x1,x17,25,x15,f15,0x40,38*XLEN/8,c.fsw,0,x3,x2, 38*FLEN/8) + +inst_39: +// rs2_val == 4194304, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x44; align:0; flagreg:x3; +// valreg: x2; valoffset: 39*FLEN/8 +TEST_STORE_F(x1,x17,86,x15,f15,0x44,39*XLEN/8,c.fsw,0,x3,x2, 39*FLEN/8) + +inst_40: +// rs2_val == 8388608, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 40*FLEN/8 +TEST_STORE_F(x1,x17,125,x15,f15,0x0,40*XLEN/8,c.fsw,0,x3,x2, 40*FLEN/8) + +inst_41: +// rs2_val == 16777216, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x74; align:0; flagreg:x3; +// valreg: x2; valoffset: 41*FLEN/8 +TEST_STORE_F(x1,x17,69,x15,f15,0x74,41*XLEN/8,c.fsw,0,x3,x2, 41*FLEN/8) + +inst_42: +// rs2_val == 67108864, imm_val == 8 +// opcode:c.fsw; op1:x15; op2:f15; immval:0x8; align:0; flagreg:x3; +// valreg: x2; valoffset: 42*FLEN/8 +TEST_STORE_F(x1,x17,74,x15,f15,0x8,42*XLEN/8,c.fsw,0,x3,x2, 42*FLEN/8) + +inst_43: +// rs2_val == 134217728, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 43*FLEN/8 +TEST_STORE_F(x1,x17,46,x15,f15,0x4,43*XLEN/8,c.fsw,0,x3,x2, 43*FLEN/8) + +inst_44: +// rs2_val == 268435456, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 44*FLEN/8 +TEST_STORE_F(x1,x17,116,x15,f15,0x28,44*XLEN/8,c.fsw,0,x3,x2, 44*FLEN/8) + +inst_45: +// rs2_val == 536870912, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 45*FLEN/8 +TEST_STORE_F(x1,x17,149,x15,f15,0x0,45*XLEN/8,c.fsw,0,x3,x2, 45*FLEN/8) + +inst_46: +// rs2_val == 1073741824, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x3c; align:0; flagreg:x3; +// valreg: x2; valoffset: 46*FLEN/8 +TEST_STORE_F(x1,x17,124,x15,f15,0x3c,46*XLEN/8,c.fsw,0,x3,x2, 46*FLEN/8) + +inst_47: +// rs2_val == 1431655765, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 47*FLEN/8 +TEST_STORE_F(x1,x17,69,x15,f15,0x14,47*XLEN/8,c.fsw,0,x3,x2, 47*FLEN/8) + +inst_48: +// rs2_val == -1431655766, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x48; align:0; flagreg:x3; +// valreg: x2; valoffset: 48*FLEN/8 +TEST_STORE_F(x1,x17,19,x15,f15,0x48,48*XLEN/8,c.fsw,0,x3,x2, 48*FLEN/8) + +inst_49: +// imm_val == 84, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x54; align:0; flagreg:x3; +// valreg: x2; valoffset: 49*FLEN/8 +TEST_STORE_F(x1,x17,30,x15,f15,0x54,49*XLEN/8,c.fsw,0,x3,x2, 49*FLEN/8) + +inst_50: +// rs2_val == 0, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x1c; align:0; flagreg:x3; +// valreg: x2; valoffset: 50*FLEN/8 +TEST_STORE_F(x1,x17,64,x15,f15,0x1c,50*XLEN/8,c.fsw,0,x3,x2, 50*FLEN/8) + +inst_51: +// rs2_val == 2, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x2c; align:0; flagreg:x3; +// valreg: x2; valoffset: 51*FLEN/8 +TEST_STORE_F(x1,x17,4,x15,f15,0x2c,51*XLEN/8,c.fsw,0,x3,x2, 51*FLEN/8) + +inst_52: +// rs2_val == 4, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x8; align:0; flagreg:x3; +// valreg: x2; valoffset: 52*FLEN/8 +TEST_STORE_F(x1,x17,12,x15,f15,0x8,52*XLEN/8,c.fsw,0,x3,x2, 52*FLEN/8) + +inst_53: +// rs2_val == 8, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 53*FLEN/8 +TEST_STORE_F(x1,x17,9,x15,f15,0x14,53*XLEN/8,c.fsw,0,x3,x2, 53*FLEN/8) + +inst_54: +// rs2_val == 32, +// opcode:c.fsw; op1:x15; op2:f15; immval:0xc; align:0; flagreg:x3; +// valreg: x2; valoffset: 54*FLEN/8 +TEST_STORE_F(x1,x17,121,x15,f15,0xc,54*XLEN/8,c.fsw,0,x3,x2, 54*FLEN/8) + +inst_55: +// rs2_val == 64, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x7c; align:0; flagreg:x3; +// valreg: x2; valoffset: 55*FLEN/8 +TEST_STORE_F(x1,x17,106,x15,f15,0x7c,55*XLEN/8,c.fsw,0,x3,x2, 55*FLEN/8) + +inst_56: +// rs2_val == 128, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 56*FLEN/8 +TEST_STORE_F(x1,x17,136,x15,f15,0x14,56*XLEN/8,c.fsw,0,x3,x2, 56*FLEN/8) + +inst_57: +// rs2_val == 256, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x24; align:0; flagreg:x3; +// valreg: x2; valoffset: 57*FLEN/8 +TEST_STORE_F(x1,x17,30,x15,f15,0x24,57*XLEN/8,c.fsw,0,x3,x2, 57*FLEN/8) + +inst_58: +// rs2_val == 512, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 58*FLEN/8 +TEST_STORE_F(x1,x17,57,x15,f15,0x28,58*XLEN/8,c.fsw,0,x3,x2, 58*FLEN/8) + +inst_59: +// rs2_val == 1024, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x10; align:0; flagreg:x3; +// valreg: x2; valoffset: 59*FLEN/8 +TEST_STORE_F(x1,x17,2,x15,f15,0x10,59*XLEN/8,c.fsw,0,x3,x2, 59*FLEN/8) + +inst_60: +// rs2_val == 2048, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x24; align:0; flagreg:x3; +// valreg: x2; valoffset: 60*FLEN/8 +TEST_STORE_F(x1,x17,43,x15,f15,0x24,60*XLEN/8,c.fsw,0,x3,x2, 60*FLEN/8) + +inst_61: +// rs2_val == 4096, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x10; align:0; flagreg:x3; +// valreg: x2; valoffset: 61*FLEN/8 +TEST_STORE_F(x1,x17,37,x15,f15,0x10,61*XLEN/8,c.fsw,0,x3,x2, 61*FLEN/8) + +inst_62: +// rs2_val == 8192, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x18; align:0; flagreg:x3; +// valreg: x2; valoffset: 62*FLEN/8 +TEST_STORE_F(x1,x17,35,x15,f15,0x18,62*XLEN/8,c.fsw,0,x3,x2, 62*FLEN/8) + +inst_63: +// rs2_val == 16384, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x38; align:0; flagreg:x3; +// valreg: x2; valoffset: 63*FLEN/8 +TEST_STORE_F(x1,x17,32,x15,f15,0x38,63*XLEN/8,c.fsw,0,x3,x2, 63*FLEN/8) + +inst_64: +// rs2_val == 32768, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x38; align:0; flagreg:x3; +// valreg: x2; valoffset: 64*FLEN/8 +TEST_STORE_F(x1,x17,131,x15,f15,0x38,64*XLEN/8,c.fsw,0,x3,x2, 64*FLEN/8) + +inst_65: +// rs2_val == 131072, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 65*FLEN/8 +TEST_STORE_F(x1,x17,120,x15,f15,0x28,65*XLEN/8,c.fsw,0,x3,x2, 65*FLEN/8) + +inst_66: +// rs2_val == 262144, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 66*FLEN/8 +TEST_STORE_F(x1,x17,81,x15,f15,0x4,66*XLEN/8,c.fsw,0,x3,x2, 66*FLEN/8) + +inst_67: +// rs2_val == 524288, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x54; align:0; flagreg:x3; +// valreg: x2; valoffset: 67*FLEN/8 +TEST_STORE_F(x1,x17,0,x15,f15,0x54,67*XLEN/8,c.fsw,0,x3,x2, 67*FLEN/8) + +inst_68: +// rs2_val == 1048576, +// opcode:c.fsw; op1:x15; op2:f15; immval:0x48; align:0; flagreg:x3; +// valreg: x2; valoffset: 68*FLEN/8 +TEST_STORE_F(x1,x17,153,x15,f15,0x48,68*XLEN/8,c.fsw,0,x3,x2, 68*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2097152,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(16,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(33554432,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-2147483648,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2147483647,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-3,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-5,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-9,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-17,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-33,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-65,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-129,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-257,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-513,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-1025,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-2049,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-4097,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-8193,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-16385,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-32769,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-65537,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-131073,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-262145,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-524289,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-1048577,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-2097153,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-4194305,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-8388609,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-16777217,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-33554433,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-67108865,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-134217729,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-268435457,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-536870913,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-1073741825,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(65536,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-4194305,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(4194304,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(8388608,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(16777216,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(67108864,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(134217728,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(268435456,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(536870912,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1073741824,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1431655765,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(-1431655766,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(5,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(4,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(8,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(64,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(128,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(256,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(512,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1024,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(2048,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(4096,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(8192,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(16384,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(32768,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(131072,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(262144,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(524288,32,FLEN) +NAN_BOXED(0,32,FLEN) +NAN_BOXED(1048576,32,FLEN) +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 69*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/tests/rv32fc-test-suite/cfswsp-01.S b/tests/rv32fc-test-suite/cfswsp-01.S new file mode 100644 index 00000000..3931628c --- /dev/null +++ b/tests/rv32fc-test-suite/cfswsp-01.S @@ -0,0 +1,504 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.11.1 +// timestamp : Fri Jan 5 19:15:51 2024 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/dataset.cgf \ +// --cgf /home/fourcolor/Documents/riscv-ctg/sample_cgfs/rv32fc_1.cgf \ + \ +// -- xlen 32 \ +// --randomize \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.fswsp instruction of the RISC-V RV32FC extension for the cfswsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IFC") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*F.*C.*);def TEST_CASE_1=True;",cfswsp) + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x2,test_dataset_0) +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs2==f2,imm_val == 0, rs2_val == 1024 +// opcode:c.fswsp; op1:x2; op2:f2; op2val:0x400; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 0*FLEN/8 +TEST_STORE_F(x1,x9,46,x2,f2,0x0,0*XLEN/8,c.fswsp,0,x3,x2, 0*FLEN/8) + +inst_1: +// rs2==f25,imm_val == 0 and fcsr == 0, rs2_val == -513 +// opcode:c.fswsp; op1:x2; op2:f25; op2val:-0x201; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 1*FLEN/8 +TEST_STORE_F(x1,x9,0,x2,f25,0x0,1*XLEN/8,c.fswsp,0,x3,x2, 1*FLEN/8) + +inst_2: +// rs2==f10,imm_val > 0, imm_val == 4, rs2_val == 2 +// opcode:c.fswsp; op1:x2; op2:f10; op2val:0x2; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 2*FLEN/8 +TEST_STORE_F(x1,x9,43,x2,f10,0x4,2*XLEN/8,c.fswsp,0,x3,x2, 2*FLEN/8) + +inst_3: +// rs2==f4,imm_val > 0 and fcsr == 0, rs2_val == -129, imm_val == 244 +// opcode:c.fswsp; op1:x2; op2:f4; op2val:-0x81; immval:0xf4; align:0; flagreg:x3; +// valreg: x2; valoffset: 3*FLEN/8 +TEST_STORE_F(x1,x9,0,x2,f4,0xf4,3*XLEN/8,c.fswsp,0,x3,x2, 3*FLEN/8) + +inst_4: +// rs2==f20,rs2_val == -2, +// opcode:c.fswsp; op1:x2; op2:f20; op2val:-0x2; immval:0xfc; align:0; flagreg:x3; +// valreg: x2; valoffset: 4*FLEN/8 +TEST_STORE_F(x1,x9,148,x2,f20,0xfc,4*XLEN/8,c.fswsp,0,x3,x2, 4*FLEN/8) + +inst_5: +// rs2==f19,rs2_val == -3, +// opcode:c.fswsp; op1:x2; op2:f19; op2val:-0x3; immval:0xfc; align:0; flagreg:x3; +// valreg: x2; valoffset: 5*FLEN/8 +TEST_STORE_F(x1,x9,85,x2,f19,0xfc,5*XLEN/8,c.fswsp,0,x3,x2, 5*FLEN/8) + +inst_6: +// rs2==f21,rs2_val == -5, +// opcode:c.fswsp; op1:x2; op2:f21; op2val:-0x5; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 6*FLEN/8 +TEST_STORE_F(x1,x9,37,x2,f21,0x0,6*XLEN/8,c.fswsp,0,x3,x2, 6*FLEN/8) + +inst_7: +// rs2==f15,rs2_val == -9, +// opcode:c.fswsp; op1:x2; op2:f15; op2val:-0x9; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 7*FLEN/8 +TEST_STORE_F(x1,x9,57,x2,f15,0x28,7*XLEN/8,c.fswsp,0,x3,x2, 7*FLEN/8) + +inst_8: +// rs2==f27,rs2_val == -17, +// opcode:c.fswsp; op1:x2; op2:f27; op2val:-0x11; immval:0x44; align:0; flagreg:x3; +// valreg: x2; valoffset: 8*FLEN/8 +TEST_STORE_F(x1,x9,114,x2,f27,0x44,8*XLEN/8,c.fswsp,0,x3,x2, 8*FLEN/8) + +inst_9: +// rs2==f17,rs2_val == -33, imm_val == 188 +// opcode:c.fswsp; op1:x2; op2:f17; op2val:-0x21; immval:0xbc; align:0; flagreg:x3; +// valreg: x2; valoffset: 9*FLEN/8 +TEST_STORE_F(x1,x9,41,x2,f17,0xbc,9*XLEN/8,c.fswsp,0,x3,x2, 9*FLEN/8) + +inst_10: +// rs2==f9,rs2_val == -65, +// opcode:c.fswsp; op1:x2; op2:f9; op2val:-0x41; immval:0xbc; align:0; flagreg:x3; +// valreg: x2; valoffset: 10*FLEN/8 +TEST_STORE_F(x1,x9,65,x2,f9,0xbc,10*XLEN/8,c.fswsp,0,x3,x2, 10*FLEN/8) + +inst_11: +// rs2==f12,rs2_val == -257, +// opcode:c.fswsp; op1:x2; op2:f12; op2val:-0x101; immval:0xc; align:0; flagreg:x3; +// valreg: x2; valoffset: 11*FLEN/8 +TEST_STORE_F(x1,x9,12,x2,f12,0xc,11*XLEN/8,c.fswsp,0,x3,x2, 11*FLEN/8) + +inst_12: +// rs2==f7,rs2_val == -1025, +// opcode:c.fswsp; op1:x2; op2:f7; op2val:-0x401; immval:0x38; align:0; flagreg:x3; +// valreg: x2; valoffset: 12*FLEN/8 +TEST_STORE_F(x1,x9,88,x2,f7,0x38,12*XLEN/8,c.fswsp,0,x3,x2, 12*FLEN/8) + +inst_13: +// rs2==f23,rs2_val == -2049, +// opcode:c.fswsp; op1:x2; op2:f23; op2val:-0x801; immval:0xbc; align:0; flagreg:x3; +// valreg: x2; valoffset: 13*FLEN/8 +TEST_STORE_F(x1,x9,135,x2,f23,0xbc,13*XLEN/8,c.fswsp,0,x3,x2, 13*FLEN/8) + +inst_14: +// rs2==f14,rs2_val == -4097, +// opcode:c.fswsp; op1:x2; op2:f14; op2val:-0x1001; immval:0x44; align:0; flagreg:x3; +// valreg: x2; valoffset: 14*FLEN/8 +TEST_STORE_F(x1,x9,94,x2,f14,0x44,14*XLEN/8,c.fswsp,0,x3,x2, 14*FLEN/8) + +inst_15: +// rs2==f3,rs2_val == -8193, imm_val == 248 +// opcode:c.fswsp; op1:x2; op2:f3; op2val:-0x2001; immval:0xf8; align:0; flagreg:x3; +// valreg: x2; valoffset: 15*FLEN/8 +TEST_STORE_F(x1,x9,37,x2,f3,0xf8,15*XLEN/8,c.fswsp,0,x3,x2, 15*FLEN/8) + +inst_16: +// rs2==f22,rs2_val == -16385, imm_val == 84 +// opcode:c.fswsp; op1:x2; op2:f22; op2val:-0x4001; immval:0x54; align:0; flagreg:x3; +// valreg: x2; valoffset: 16*FLEN/8 +TEST_STORE_F(x1,x9,36,x2,f22,0x54,16*XLEN/8,c.fswsp,0,x3,x2, 16*FLEN/8) + +inst_17: +// rs2==f26,rs2_val == -32769, +// opcode:c.fswsp; op1:x2; op2:f26; op2val:-0x8001; immval:0x2c; align:0; flagreg:x3; +// valreg: x2; valoffset: 17*FLEN/8 +TEST_STORE_F(x1,x9,127,x2,f26,0x2c,17*XLEN/8,c.fswsp,0,x3,x2, 17*FLEN/8) + +inst_18: +// rs2==f29,rs2_val == -65537, +// opcode:c.fswsp; op1:x2; op2:f29; op2val:-0x10001; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 18*FLEN/8 +TEST_STORE_F(x1,x9,123,x2,f29,0x28,18*XLEN/8,c.fswsp,0,x3,x2, 18*FLEN/8) + +inst_19: +// rs2==f30,rs2_val == -131073, +// opcode:c.fswsp; op1:x2; op2:f30; op2val:-0x20001; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 19*FLEN/8 +TEST_STORE_F(x1,x9,18,x2,f30,0x0,19*XLEN/8,c.fswsp,0,x3,x2, 19*FLEN/8) + +inst_20: +// rs2==f1,rs2_val == -262145, imm_val == 64 +// opcode:c.fswsp; op1:x2; op2:f1; op2val:-0x40001; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 20*FLEN/8 +TEST_STORE_F(x1,x9,113,x2,f1,0x40,20*XLEN/8,c.fswsp,0,x3,x2, 20*FLEN/8) + +inst_21: +// rs2==f5,rs2_val == -524289, +// opcode:c.fswsp; op1:x2; op2:f5; op2val:-0x80001; immval:0x54; align:0; flagreg:x3; +// valreg: x2; valoffset: 21*FLEN/8 +TEST_STORE_F(x1,x9,144,x2,f5,0x54,21*XLEN/8,c.fswsp,0,x3,x2, 21*FLEN/8) + +inst_22: +// rs2==f13,rs2_val == -1048577, +// opcode:c.fswsp; op1:x2; op2:f13; op2val:-0x100001; immval:0x1c; align:0; flagreg:x3; +// valreg: x2; valoffset: 22*FLEN/8 +TEST_STORE_F(x1,x9,131,x2,f13,0x1c,22*XLEN/8,c.fswsp,0,x3,x2, 22*FLEN/8) + +inst_23: +// rs2==f0,rs2_val == -2097153, +// opcode:c.fswsp; op1:x2; op2:f0; op2val:-0x200001; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 23*FLEN/8 +TEST_STORE_F(x1,x9,9,x2,f0,0x14,23*XLEN/8,c.fswsp,0,x3,x2, 23*FLEN/8) + +inst_24: +// rs2==f31,rs2_val == -4194305, imm_val == 236 +// opcode:c.fswsp; op1:x2; op2:f31; op2val:-0x400001; immval:0xec; align:0; flagreg:x3; +// valreg: x2; valoffset: 24*FLEN/8 +TEST_STORE_F(x1,x9,25,x2,f31,0xec,24*XLEN/8,c.fswsp,0,x3,x2, 24*FLEN/8) + +inst_25: +// rs2==f16,rs2_val == -8388609, imm_val == 32 +// opcode:c.fswsp; op1:x2; op2:f16; op2val:-0x800001; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 25*FLEN/8 +TEST_STORE_F(x1,x9,107,x2,f16,0x20,25*XLEN/8,c.fswsp,0,x3,x2, 25*FLEN/8) + +inst_26: +// rs2==f8,rs2_val == -16777217, +// opcode:c.fswsp; op1:x2; op2:f8; op2val:-0x1000001; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 26*FLEN/8 +TEST_STORE_F(x1,x9,35,x2,f8,0x20,26*XLEN/8,c.fswsp,0,x3,x2, 26*FLEN/8) + +inst_27: +// rs2==f6,rs2_val == -33554433, imm_val == 220 +// opcode:c.fswsp; op1:x2; op2:f6; op2val:-0x2000001; immval:0xdc; align:0; flagreg:x3; +// valreg: x2; valoffset: 27*FLEN/8 +TEST_STORE_F(x1,x9,90,x2,f6,0xdc,27*XLEN/8,c.fswsp,0,x3,x2, 27*FLEN/8) + +inst_28: +// rs2==f28,rs2_val == -67108865, +// opcode:c.fswsp; op1:x2; op2:f28; op2val:-0x4000001; immval:0x48; align:0; flagreg:x3; +// valreg: x2; valoffset: 28*FLEN/8 +TEST_STORE_F(x1,x9,36,x2,f28,0x48,28*XLEN/8,c.fswsp,0,x3,x2, 28*FLEN/8) + +inst_29: +// rs2==f11,rs2_val == -134217729, imm_val == 168 +// opcode:c.fswsp; op1:x2; op2:f11; op2val:-0x8000001; immval:0xa8; align:0; flagreg:x3; +// valreg: x2; valoffset: 29*FLEN/8 +TEST_STORE_F(x1,x9,108,x2,f11,0xa8,29*XLEN/8,c.fswsp,0,x3,x2, 29*FLEN/8) + +inst_30: +// rs2==f18,rs2_val == -268435457, +// opcode:c.fswsp; op1:x2; op2:f18; op2val:-0x10000001; immval:0xc; align:0; flagreg:x3; +// valreg: x2; valoffset: 30*FLEN/8 +TEST_STORE_F(x1,x9,81,x2,f18,0xc,30*XLEN/8,c.fswsp,0,x3,x2, 30*FLEN/8) + +inst_31: +// rs2==f24,rs2_val == -536870913, +// opcode:c.fswsp; op1:x2; op2:f24; op2val:-0x20000001; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 31*FLEN/8 +TEST_STORE_F(x1,x9,92,x2,f24,0x28,31*XLEN/8,c.fswsp,0,x3,x2, 31*FLEN/8) + +inst_32: +// rs2_val == -1073741825, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:-0x40000001; immval:0xfc; align:0; flagreg:x3; +// valreg: x2; valoffset: 32*FLEN/8 +TEST_STORE_F(x1,x9,3,x2,f31,0xfc,32*XLEN/8,c.fswsp,0,x3,x2, 32*FLEN/8) + +inst_33: +// rs2_val == 2147483647, imm_val == 16, rs2_val == (2**(xlen-1)-1) +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x7fffffff; immval:0x10; align:0; flagreg:x3; +// valreg: x2; valoffset: 33*FLEN/8 +TEST_STORE_F(x1,x9,37,x2,f31,0x10,33*XLEN/8,c.fswsp,0,x3,x2, 33*FLEN/8) + +inst_34: +// imm_val == 124, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:-0x4; immval:0x7c; align:0; flagreg:x3; +// valreg: x2; valoffset: 34*FLEN/8 +TEST_STORE_F(x1,x9,108,x2,f31,0x7c,34*XLEN/8,c.fswsp,0,x3,x2, 34*FLEN/8) + +inst_35: +// rs2_val == 1, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x1; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 35*FLEN/8 +TEST_STORE_F(x1,x9,53,x2,f31,0x20,35*XLEN/8,c.fswsp,0,x3,x2, 35*FLEN/8) + +inst_36: +// rs2_val == 4, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x4; immval:0xbc; align:0; flagreg:x3; +// valreg: x2; valoffset: 36*FLEN/8 +TEST_STORE_F(x1,x9,60,x2,f31,0xbc,36*XLEN/8,c.fswsp,0,x3,x2, 36*FLEN/8) + +inst_37: +// rs2_val == 8, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x8; immval:0x30; align:0; flagreg:x3; +// valreg: x2; valoffset: 37*FLEN/8 +TEST_STORE_F(x1,x9,44,x2,f31,0x30,37*XLEN/8,c.fswsp,0,x3,x2, 37*FLEN/8) + +inst_38: +// rs2_val == 16, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x10; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 38*FLEN/8 +TEST_STORE_F(x1,x9,96,x2,f31,0x40,38*XLEN/8,c.fswsp,0,x3,x2, 38*FLEN/8) + +inst_39: +// rs2_val == 32, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x20; immval:0xf4; align:0; flagreg:x3; +// valreg: x2; valoffset: 39*FLEN/8 +TEST_STORE_F(x1,x9,55,x2,f31,0xf4,39*XLEN/8,c.fswsp,0,x3,x2, 39*FLEN/8) + +inst_40: +// rs2_val == 4194304, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x400000; immval:0x34; align:0; flagreg:x3; +// valreg: x2; valoffset: 40*FLEN/8 +TEST_STORE_F(x1,x9,54,x2,f31,0x34,40*XLEN/8,c.fswsp,0,x3,x2, 40*FLEN/8) + +inst_41: +// rs2_val == 8388608, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x800000; immval:0x4c; align:0; flagreg:x3; +// valreg: x2; valoffset: 41*FLEN/8 +TEST_STORE_F(x1,x9,99,x2,f31,0x4c,41*XLEN/8,c.fswsp,0,x3,x2, 41*FLEN/8) + +inst_42: +// rs2_val == 16777216, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x1000000; immval:0x0; align:0; flagreg:x3; +// valreg: x2; valoffset: 42*FLEN/8 +TEST_STORE_F(x1,x9,44,x2,f31,0x0,42*XLEN/8,c.fswsp,0,x3,x2, 42*FLEN/8) + +inst_43: +// rs2_val == 33554432, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x2000000; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 43*FLEN/8 +TEST_STORE_F(x1,x9,155,x2,f31,0x20,43*XLEN/8,c.fswsp,0,x3,x2, 43*FLEN/8) + +inst_44: +// rs2_val == 67108864, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x4000000; immval:0x3c; align:0; flagreg:x3; +// valreg: x2; valoffset: 44*FLEN/8 +TEST_STORE_F(x1,x9,78,x2,f31,0x3c,44*XLEN/8,c.fswsp,0,x3,x2, 44*FLEN/8) + +inst_45: +// rs2_val == 134217728, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x8000000; immval:0x38; align:0; flagreg:x3; +// valreg: x2; valoffset: 45*FLEN/8 +TEST_STORE_F(x1,x9,76,x2,f31,0x38,45*XLEN/8,c.fswsp,0,x3,x2, 45*FLEN/8) + +inst_46: +// rs2_val == 268435456, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x10000000; immval:0xec; align:0; flagreg:x3; +// valreg: x2; valoffset: 46*FLEN/8 +TEST_STORE_F(x1,x9,30,x2,f31,0xec,46*XLEN/8,c.fswsp,0,x3,x2, 46*FLEN/8) + +inst_47: +// rs2_val == 536870912, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x20000000; immval:0x3c; align:0; flagreg:x3; +// valreg: x2; valoffset: 47*FLEN/8 +TEST_STORE_F(x1,x9,102,x2,f31,0x3c,47*XLEN/8,c.fswsp,0,x3,x2, 47*FLEN/8) + +inst_48: +// rs2_val == 1073741824, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x40000000; immval:0x48; align:0; flagreg:x3; +// valreg: x2; valoffset: 48*FLEN/8 +TEST_STORE_F(x1,x9,21,x2,f31,0x48,48*XLEN/8,c.fswsp,0,x3,x2, 48*FLEN/8) + +inst_49: +// rs2_val == -2147483648, rs2_val == (-2**(xlen-1)) +// opcode:c.fswsp; op1:x2; op2:f31; op2val:-0x80000000; immval:0x20; align:0; flagreg:x3; +// valreg: x2; valoffset: 49*FLEN/8 +TEST_STORE_F(x1,x9,154,x2,f31,0x20,49*XLEN/8,c.fswsp,0,x3,x2, 49*FLEN/8) + +inst_50: +// imm_val == 8, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:-0x6; immval:0x8; align:0; flagreg:x3; +// valreg: x2; valoffset: 50*FLEN/8 +TEST_STORE_F(x1,x9,43,x2,f31,0x8,50*XLEN/8,c.fswsp,0,x3,x2, 50*FLEN/8) + +inst_51: +// imm_val == 128, rs2_val == 64 +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x40; immval:0x80; align:0; flagreg:x3; +// valreg: x2; valoffset: 51*FLEN/8 +TEST_STORE_F(x1,x9,112,x2,f31,0x80,51*XLEN/8,c.fswsp,0,x3,x2, 51*FLEN/8) + +inst_52: +// rs2_val == 1431655765, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x55555555; immval:0xf4; align:0; flagreg:x3; +// valreg: x2; valoffset: 52*FLEN/8 +TEST_STORE_F(x1,x9,151,x2,f31,0xf4,52*XLEN/8,c.fswsp,0,x3,x2, 52*FLEN/8) + +inst_53: +// rs2_val == -1431655766, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:-0x55555556; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 53*FLEN/8 +TEST_STORE_F(x1,x9,70,x2,f31,0x40,53*XLEN/8,c.fswsp,0,x3,x2, 53*FLEN/8) + +inst_54: +// rs2_val == 65536, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x10000; immval:0x44; align:0; flagreg:x3; +// valreg: x2; valoffset: 54*FLEN/8 +TEST_STORE_F(x1,x9,7,x2,f31,0x44,54*XLEN/8,c.fswsp,0,x3,x2, 54*FLEN/8) + +inst_55: +// rs2_val == 128, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x80; immval:0x40; align:0; flagreg:x3; +// valreg: x2; valoffset: 55*FLEN/8 +TEST_STORE_F(x1,x9,125,x2,f31,0x40,55*XLEN/8,c.fswsp,0,x3,x2, 55*FLEN/8) + +inst_56: +// rs2_val == 256, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x100; immval:0x44; align:0; flagreg:x3; +// valreg: x2; valoffset: 56*FLEN/8 +TEST_STORE_F(x1,x9,44,x2,f31,0x44,56*XLEN/8,c.fswsp,0,x3,x2, 56*FLEN/8) + +inst_57: +// rs2_val == 512, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x200; immval:0x3c; align:0; flagreg:x3; +// valreg: x2; valoffset: 57*FLEN/8 +TEST_STORE_F(x1,x9,60,x2,f31,0x3c,57*XLEN/8,c.fswsp,0,x3,x2, 57*FLEN/8) + +inst_58: +// rs2_val == 2048, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x800; immval:0x28; align:0; flagreg:x3; +// valreg: x2; valoffset: 58*FLEN/8 +TEST_STORE_F(x1,x9,40,x2,f31,0x28,58*XLEN/8,c.fswsp,0,x3,x2, 58*FLEN/8) + +inst_59: +// rs2_val == 8192, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x2000; immval:0x24; align:0; flagreg:x3; +// valreg: x2; valoffset: 59*FLEN/8 +TEST_STORE_F(x1,x9,113,x2,f31,0x24,59*XLEN/8,c.fswsp,0,x3,x2, 59*FLEN/8) + +inst_60: +// rs2_val == 0, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x0; immval:0xc; align:0; flagreg:x3; +// valreg: x2; valoffset: 60*FLEN/8 +TEST_STORE_F(x1,x9,25,x2,f31,0xc,60*XLEN/8,c.fswsp,0,x3,x2, 60*FLEN/8) + +inst_61: +// rs2_val == 4096, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x1000; immval:0xec; align:0; flagreg:x3; +// valreg: x2; valoffset: 61*FLEN/8 +TEST_STORE_F(x1,x9,141,x2,f31,0xec,61*XLEN/8,c.fswsp,0,x3,x2, 61*FLEN/8) + +inst_62: +// rs2_val == 16384, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x4000; immval:0x14; align:0; flagreg:x3; +// valreg: x2; valoffset: 62*FLEN/8 +TEST_STORE_F(x1,x9,82,x2,f31,0x14,62*XLEN/8,c.fswsp,0,x3,x2, 62*FLEN/8) + +inst_63: +// rs2_val == 32768, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x8000; immval:0x4; align:0; flagreg:x3; +// valreg: x2; valoffset: 63*FLEN/8 +TEST_STORE_F(x1,x9,29,x2,f31,0x4,63*XLEN/8,c.fswsp,0,x3,x2, 63*FLEN/8) + +inst_64: +// rs2_val == 131072, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x20000; immval:0xbc; align:0; flagreg:x3; +// valreg: x2; valoffset: 64*FLEN/8 +TEST_STORE_F(x1,x9,100,x2,f31,0xbc,64*XLEN/8,c.fswsp,0,x3,x2, 64*FLEN/8) + +inst_65: +// rs2_val == 262144, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x40000; immval:0x30; align:0; flagreg:x3; +// valreg: x2; valoffset: 65*FLEN/8 +TEST_STORE_F(x1,x9,1,x2,f31,0x30,65*XLEN/8,c.fswsp,0,x3,x2, 65*FLEN/8) + +inst_66: +// rs2_val == 524288, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x80000; immval:0x3c; align:0; flagreg:x3; +// valreg: x2; valoffset: 66*FLEN/8 +TEST_STORE_F(x1,x9,3,x2,f31,0x3c,66*XLEN/8,c.fswsp,0,x3,x2, 66*FLEN/8) + +inst_67: +// rs2_val == 1048576, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x100000; immval:0x8; align:0; flagreg:x3; +// valreg: x2; valoffset: 67*FLEN/8 +TEST_STORE_F(x1,x9,14,x2,f31,0x8,67*XLEN/8,c.fswsp,0,x3,x2, 67*FLEN/8) + +inst_68: +// rs2_val == 2097152, +// opcode:c.fswsp; op1:x2; op2:f31; op2val:0x200000; immval:0x10; align:0; flagreg:x3; +// valreg: x2; valoffset: 68*FLEN/8 +TEST_STORE_F(x1,x9,69,x2,f31,0x10,68*XLEN/8,c.fswsp,0,x3,x2, 68*FLEN/8) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +test_dataset_0: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 69*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END