Incorrect misaligned memory operation handling in userspace simulation

[vacantron]

The current exception handling of userspace program simulation simply skip the misaligned memory operation and return from M-mode:

rv32emu/src/emulate.c

Lines 51 to 55 in f7fd15b

	static void rv_trap_default_handler(riscv_t *rv)
	{
	rv->csr_mepc += rv->compressed ? 2 : 4;
	rv->PC = rv->csr_mepc; /* mret */
	}

And the handler is also missing in just-in-time (JIT) mode.

The real behavor of the hardware that allows the misaligned memory operation would be taking that operation to piece of the smaller and aligned memory operation (i.e. lb/lbu/sb and lh/lhu/sh for misaligned lw/sw or lb/lbu/sb for misaligned lh/lhu/sh.