Need help with UEFI Tool #49
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Replies: 10 comments 29 replies
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On the 1st screenshot, Strap driver is not the last one in the volume list, perhaps this causes an error? |
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You may get a smaller .ffs file if you manually compile v0.1 from github. But make sure this is really the issue, because v0.1 uses hard-coded values for the GPU BAR0 address on the PCI bus (plus the PCI bridge memory mapped address), that you need to fill in manually into the source code. Also see the video guide (thanks to @UnidentifiedTag for providing it). Maybe you can try an older UEFI image for your motherboard, with a smaller size, just to confirm that size is the problem. Make sure the older version still supports your CPU ! To further decrease the .ffs size, you could manually remove all the IDs from DeviceRegistry.c source file, except the PCI device ID for your GPU |
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If you can help with that (make .ffs smaller 9 kb) I will be very grateful. I can send hex values of my system. I will try tomorrow, but i dont sure about success |
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@666cloudyy i saw on win-raid forum that some users delete unwanted modules relating to network boot to free up space for nvme dxe on old motherboards. maybe that can work in this case too |
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what steps can we follow to help isolate the problem if our system fails to post with any size ReBAR set? |
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Hi @666cloudyy Your LocalPciGpu.h file should have the values below. I used hexadecimal values, but you can freely use the equivalent decimal values if you want. #define TARGET_GPU_PCI_VENDOR_ID 0x10DEu
#define TARGET_GPU_PCI_DEVICE_ID 0x2188u
#define TARGET_GPU_PCI_BUS 0x02u
#define TARGET_GPU_PCI_DEVICE 0x00u
#define TARGET_GPU_PCI_FUNCTION 0x00u
// PCIe config register offset 0x10
#define TARGET_GPU_BAR0_ADDRESS UINT32_C(0xFA00'0000) // Should fall within memory range mapped by the bridge
#define TARGET_GPU_BAR1_SIZE_SELECTOR _4G // Desired size for GPU BAR1, should cover the VRAM size
// Secondary bus of the bridge must match the GPU bus
// Check the output form CPU-Z .txt report
#define TARGET_BRIDGE_PCI_VENDOR_ID 0x8086u
#define TARGET_BRIDGE_PCI_DEVICE_ID 0x0E08u
#define TARGET_BRIDGE_PCI_BUS 0x00u
#define TARGET_BRIDGE_PCI_DEVICE 0x03u
#define TARGET_BRIDGE_PCI_FUNCTION 0x00u
// Memory range and I/O port range (base + limit) mapped to bridge
// from CPU-Z .txt report of the bridge and GPU
// PCIe config register offset 0x20
#define TARGET_BRIDGE_MEM_BASE_LIMIT UINT32_C(0xFB00'FA00) // Should cover the GPU BAR0
// PCIe config register offset 0x1C
#define TARGET_BRIDGE_IO_BASE_LIMIT 0xE0E0u About your error about the Please manually modify the file DeviceList.cc at the following line: The initial version v0.1 was written for the regular expression to match the English language, but later versions no longer depend on language. |
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Yes, the old v0.1 has an issue like this, and other users reported the same output. But it works. The issue was fixed later, unfortunately I do not remember what the problem was in the first place