From 3304e6f34da73db7bc1daae140b3f97bc24960ca Mon Sep 17 00:00:00 2001 From: Grzegorz Bernat Date: Tue, 10 Sep 2024 10:45:43 +0200 Subject: [PATCH] app: board: Change the soc from ace30_ptl to ace30 Renamed soc from ace30_ptl to ace30. We were previously using the wrong soc name. The correct name is ace30. There is only one ptl platform, but there can be several ace30 platforms. Signed-off-by: Grzegorz Bernat --- app/sample.yaml | 8 ++++---- scripts/xtensa-build-zephyr.py | 4 ++-- src/audio/base_fw_intel.c | 2 +- .../{pantherlake => ace30}/include/platform/lib/clk.h | 0 .../{pantherlake => ace30}/include/platform/lib/cpu.h | 0 .../{pantherlake => ace30}/include/platform/lib/dai.h | 0 .../{pantherlake => ace30}/include/platform/lib/dma.h | 0 .../{pantherlake => ace30}/include/platform/lib/mailbox.h | 0 .../{pantherlake => ace30}/include/platform/lib/memory.h | 0 .../{pantherlake => ace30}/include/platform/platform.h | 0 .../{pantherlake => ace30}/include/platform/trace/trace.h | 0 src/platform/{pantherlake => ace30}/lib/clk.c | 0 west.yml | 2 +- zephyr/CMakeLists.txt | 8 ++++---- zephyr/lib/dma.c | 8 ++++---- 15 files changed, 16 insertions(+), 16 deletions(-) rename src/platform/{pantherlake => ace30}/include/platform/lib/clk.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/lib/cpu.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/lib/dai.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/lib/dma.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/lib/mailbox.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/lib/memory.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/platform.h (100%) rename src/platform/{pantherlake => ace30}/include/platform/trace/trace.h (100%) rename src/platform/{pantherlake => ace30}/lib/clk.c (100%) diff --git a/app/sample.yaml b/app/sample.yaml index 4dfa47824681..edcaf3996476 100644 --- a/app/sample.yaml +++ b/app/sample.yaml @@ -14,8 +14,8 @@ tests: - intel_adsp/cavs25 - intel_adsp/ace15_mtpm - intel_adsp/ace20_lnl - - intel_adsp/ace30_ptl - - intel_adsp/ace30_ptl_sim + - intel_adsp/ace30/ptl + - intel_adsp/ace30/ptl/sim - imx8qm_mek/mimx8qm6/adsp - imx8qxp_mek/mimx8qx6/adsp - imx8mp_evk/mimx8ml8/adsp @@ -25,8 +25,8 @@ tests: - intel_adsp/cavs25 # TGL - intel_adsp/ace15_mtpm # MTL - intel_adsp/ace20_lnl - - intel_adsp/ace30_ptl - - intel_adsp/ace30_ptl_sim + - intel_adsp/ace30/ptl + - intel_adsp/ace30/ptl/sim - imx8qm_mek/mimx8qm6/adsp - imx8qxp_mek/mimx8qx6/adsp - imx8mp_evk/mimx8ml8/adsp diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index d4049df7c2f4..c70fb9c717db 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -92,13 +92,13 @@ class PlatformConfig: # For instance: there's no open-source toolchain available for them yet. extra_platform_configs = { "ptl" : PlatformConfig( - "intel", "intel_adsp/ace30_ptl", + "intel", "intel_adsp/ace30/ptl", f"RI-2022.10{xtensa_tools_version_postfix}", "ace30_LX7HiFi4_PIF", ipc4 = True ), "ptl-sim" : PlatformConfig( - "intel", "intel_adsp/ace30_ptl_sim", + "intel", "intel_adsp/ace30/ptl/sim", f"RI-2022.10{xtensa_tools_version_postfix}", "ace30_LX7HiFi4_PIF", ipc4 = True diff --git a/src/audio/base_fw_intel.c b/src/audio/base_fw_intel.c index 9ebfb9128585..ff22b16ea9d3 100644 --- a/src/audio/base_fw_intel.c +++ b/src/audio/base_fw_intel.c @@ -88,7 +88,7 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data) tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_LP_EBB_COUNT_HW_CFG, PLATFORM_LPSRAM_EBB_COUNT); -#ifdef CONFIG_SOC_INTEL_ACE30_PTL +#ifdef CONFIG_SOC_INTEL_ACE30 tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_I2S_CAPS_HW_CFG, I2S_VER_30_PTL); #endif diff --git a/src/platform/pantherlake/include/platform/lib/clk.h b/src/platform/ace30/include/platform/lib/clk.h similarity index 100% rename from src/platform/pantherlake/include/platform/lib/clk.h rename to src/platform/ace30/include/platform/lib/clk.h diff --git a/src/platform/pantherlake/include/platform/lib/cpu.h b/src/platform/ace30/include/platform/lib/cpu.h similarity index 100% rename from src/platform/pantherlake/include/platform/lib/cpu.h rename to src/platform/ace30/include/platform/lib/cpu.h diff --git a/src/platform/pantherlake/include/platform/lib/dai.h b/src/platform/ace30/include/platform/lib/dai.h similarity index 100% rename from src/platform/pantherlake/include/platform/lib/dai.h rename to src/platform/ace30/include/platform/lib/dai.h diff --git a/src/platform/pantherlake/include/platform/lib/dma.h b/src/platform/ace30/include/platform/lib/dma.h similarity index 100% rename from src/platform/pantherlake/include/platform/lib/dma.h rename to src/platform/ace30/include/platform/lib/dma.h diff --git a/src/platform/pantherlake/include/platform/lib/mailbox.h b/src/platform/ace30/include/platform/lib/mailbox.h similarity index 100% rename from src/platform/pantherlake/include/platform/lib/mailbox.h rename to src/platform/ace30/include/platform/lib/mailbox.h diff --git a/src/platform/pantherlake/include/platform/lib/memory.h b/src/platform/ace30/include/platform/lib/memory.h similarity index 100% rename from src/platform/pantherlake/include/platform/lib/memory.h rename to src/platform/ace30/include/platform/lib/memory.h diff --git a/src/platform/pantherlake/include/platform/platform.h b/src/platform/ace30/include/platform/platform.h similarity index 100% rename from src/platform/pantherlake/include/platform/platform.h rename to src/platform/ace30/include/platform/platform.h diff --git a/src/platform/pantherlake/include/platform/trace/trace.h b/src/platform/ace30/include/platform/trace/trace.h similarity index 100% rename from src/platform/pantherlake/include/platform/trace/trace.h rename to src/platform/ace30/include/platform/trace/trace.h diff --git a/src/platform/pantherlake/lib/clk.c b/src/platform/ace30/lib/clk.c similarity index 100% rename from src/platform/pantherlake/lib/clk.c rename to src/platform/ace30/lib/clk.c diff --git a/west.yml b/west.yml index 7de378764a5f..cfcb5cc277b9 100644 --- a/west.yml +++ b/west.yml @@ -43,7 +43,7 @@ manifest: - name: zephyr repo-path: zephyr - revision: 9d9089edd09919c90c4224222fc2c560410e6c85 + revision: 99e6280d7e22552de9a94992b626acdcbde00fee remote: zephyrproject # Import some projects listed in zephyr/west.yml@revision diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt index eaf185b9c8b8..366aa561059d 100644 --- a/zephyr/CMakeLists.txt +++ b/zephyr/CMakeLists.txt @@ -262,8 +262,8 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE) ${SOF_PLATFORM_PATH}/lunarlake/lib/clk.c ) - zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30_PTL - ${SOF_PLATFORM_PATH}/pantherlake/lib/clk.c + zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30 + ${SOF_PLATFORM_PATH}/ace30/lib/clk.c ) # SOF core infrastructure - runs on top of Zephyr @@ -292,8 +292,8 @@ if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE) set(PLATFORM "meteorlake") elseif(CONFIG_SOC_INTEL_ACE20_LNL) set(PLATFORM "lunarlake") - elseif(CONFIG_SOC_INTEL_ACE30_PTL) - set(PLATFORM "pantherlake") + elseif(CONFIG_SOC_INTEL_ACE30) + set(PLATFORM "ace30") endif() zephyr_include_directories(${SOF_PLATFORM_PATH}/intel/ace/include) diff --git a/zephyr/lib/dma.c b/zephyr/lib/dma.c index 623be80beffd..9a641128da69 100644 --- a/zephyr/lib/dma.c +++ b/zephyr/lib/dma.c @@ -78,12 +78,12 @@ SHARED_DATA struct dma dma[] = { .plat_data = { .dir = DMA_DIR_DEV_TO_MEM, .caps = DMA_CAP_HDA, -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) .devs = DMA_DEV_HDA | DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_ALH, #else .devs = DMA_DEV_HDA, -#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL */ +#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 */ .channels = DT_PROP(DT_NODELABEL(hda_link_in), dma_channels), .period_count = HDA_DMA_BUFFER_PERIOD_COUNT, }, @@ -95,12 +95,12 @@ SHARED_DATA struct dma dma[] = { .plat_data = { .dir = DMA_DIR_MEM_TO_DEV, .caps = DMA_CAP_HDA, -#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL) +#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30) .devs = DMA_DEV_HDA | DMA_DEV_SSP | DMA_DEV_DMIC | DMA_DEV_ALH, #else .devs = DMA_DEV_HDA, -#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL */ +#endif /* CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 */ .channels = DT_PROP(DT_NODELABEL(hda_link_out), dma_channels), .period_count = HDA_DMA_BUFFER_PERIOD_COUNT, },