From e983b510bea53af6c7d1082d015d56de3c97f6d5 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Mon, 9 Sep 2024 19:52:56 +0300 Subject: [PATCH] base_fw: move SRAM bank details to Intel specific code The SRAM definitions like SRAM_BANK_SIZE and EBB_BANKS_IN_SEGMENT are only used in Intel specific code and not really needed in platform layer that needs to implemented by all platforms. Move these definitions to base_fw_intel.c and clean up related definitions from platform layer. Signed-off-by: Kai Vehmanen --- src/audio/base_fw.c | 7 --- src/audio/base_fw_intel.c | 24 ++++++++++ .../intel/ace/include/ace/lib/memory.h | 7 --- .../intel/cavs/include/cavs/lib/memory.h | 46 ------------------- .../posix/include/platform/lib/memory.h | 5 -- .../tigerlake/include/platform/lib/memory.h | 6 --- 6 files changed, 24 insertions(+), 71 deletions(-) diff --git a/src/audio/base_fw.c b/src/audio/base_fw.c index 28e939abef21..04df6fecfe1f 100644 --- a/src/audio/base_fw.c +++ b/src/audio/base_fw.c @@ -132,7 +132,6 @@ static int basefw_hw_config(uint32_t *data_offset, char *data) { struct sof_tlv *tuple = (struct sof_tlv *)data; uint32_t plat_data_offset = 0; - uint32_t value; tlv_value_uint32_set(tuple, IPC4_CAVS_VER_HW_CFG, HW_CFG_VERSION); @@ -142,12 +141,6 @@ static int basefw_hw_config(uint32_t *data_offset, char *data) tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_MEM_PAGE_BYTES_HW_CFG, HOST_PAGE_SIZE); - tuple = tlv_next(tuple); - tlv_value_uint32_set(tuple, IPC4_EBB_SIZE_BYTES_HW_CFG, SRAM_BANK_SIZE); - - tuple = tlv_next(tuple); - value = SOF_DIV_ROUND_UP(EBB_BANKS_IN_SEGMENT * SRAM_BANK_SIZE, HOST_PAGE_SIZE); - tlv_value_uint32_set(tuple, IPC4_TOTAL_PHYS_MEM_PAGES_HW_CFG, value); tuple = tlv_next(tuple); diff --git a/src/audio/base_fw_intel.c b/src/audio/base_fw_intel.c index fed487b7c2f3..9ebfb9128585 100644 --- a/src/audio/base_fw_intel.c +++ b/src/audio/base_fw_intel.c @@ -20,6 +20,8 @@ #endif #include +#include + #include #include @@ -28,6 +30,21 @@ struct ipc4_modules_info { struct sof_man_module modules[0]; } __packed __aligned(4); +/* + * TODO: default to value of ACE1.x platforms. This is defined + * in multiple places in Zephyr, mm_drv_intel_adsp.h and + * cavs25/adsp_memory.h, needs to be unified (and defined + * in Zephyr side) + */ +#ifndef SRAM_BANK_SIZE +#define SRAM_BANK_SIZE (128 * 1024) +#endif + +#define EBB_BANKS_IN_SEGMENT 32 + +#define PLATFORM_LPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram1)) / SRAM_BANK_SIZE) +#define PLATFORM_HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE) + LOG_MODULE_REGISTER(basefw_intel, CONFIG_SOF_LOG_LEVEL); int basefw_vendor_fw_config(uint32_t *data_offset, char *data) @@ -55,6 +72,13 @@ int basefw_vendor_hw_config(uint32_t *data_offset, char *data) tlv_value_uint32_set(tuple, IPC4_HP_EBB_COUNT_HW_CFG, PLATFORM_HPSRAM_EBB_COUNT); + tuple = tlv_next(tuple); + tlv_value_uint32_set(tuple, IPC4_EBB_SIZE_BYTES_HW_CFG, SRAM_BANK_SIZE); + + tuple = tlv_next(tuple); + value = SOF_DIV_ROUND_UP(EBB_BANKS_IN_SEGMENT * SRAM_BANK_SIZE, HOST_PAGE_SIZE); + tlv_value_uint32_set(tuple, IPC4_TOTAL_PHYS_MEM_PAGES_HW_CFG, value); + tuple = tlv_next(tuple); /* 2 DMIC dais */ value = DAI_NUM_SSP_BASE + DAI_NUM_HDA_IN + DAI_NUM_HDA_OUT + diff --git a/src/platform/intel/ace/include/ace/lib/memory.h b/src/platform/intel/ace/include/ace/lib/memory.h index f86b8e6b99d6..f021b18b00c9 100644 --- a/src/platform/intel/ace/include/ace/lib/memory.h +++ b/src/platform/intel/ace/include/ace/lib/memory.h @@ -16,10 +16,6 @@ #include #endif -#define SRAM_BANK_SIZE (128 * 1024) - -#define EBB_BANKS_IN_SEGMENT 32 - /* data cache line alignment */ #define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE @@ -31,9 +27,6 @@ */ #define SHARED_DATA -#define PLATFORM_LPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram1)) / SRAM_BANK_SIZE) -#define PLATFORM_HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE) - #include #define uncache_to_cache(address) sys_cache_cached_ptr_get(address) diff --git a/src/platform/intel/cavs/include/cavs/lib/memory.h b/src/platform/intel/cavs/include/cavs/lib/memory.h index 4d1f36a9b4a4..b53c76d64b6d 100644 --- a/src/platform/intel/cavs/include/cavs/lib/memory.h +++ b/src/platform/intel/cavs/include/cavs/lib/memory.h @@ -19,52 +19,6 @@ /* data cache line alignment */ #define PLATFORM_DCACHE_ALIGN DCACHE_LINE_SIZE -#define SRAM_BANK_SIZE (64 * 1024) - -#define EBB_BANKS_IN_SEGMENT 32 - -#define EBB_SEGMENT_SIZE EBB_BANKS_IN_SEGMENT - -#if CONFIG_LP_MEMORY_BANKS -#define PLATFORM_LPSRAM_EBB_COUNT CONFIG_LP_MEMORY_BANKS -#else -#define PLATFORM_LPSRAM_EBB_COUNT 0 -#endif - -#define PLATFORM_HPSRAM_EBB_COUNT CONFIG_HP_MEMORY_BANKS - -#define MAX_MEMORY_SEGMENTS PLATFORM_HPSRAM_SEGMENTS - -#ifndef __ZEPHYR__ -#if CONFIG_LP_MEMORY_BANKS -#define LP_SRAM_SIZE \ - (CONFIG_LP_MEMORY_BANKS * SRAM_BANK_SIZE) -#else -#define LP_SRAM_SIZE 0 -#endif - -#define HP_SRAM_SIZE \ - (CONFIG_HP_MEMORY_BANKS * SRAM_BANK_SIZE) - -#endif /* __ZEPHYR__ */ - -#define PLATFORM_HPSRAM_SEGMENTS SOF_DIV_ROUND_UP(PLATFORM_HPSRAM_EBB_COUNT, \ - EBB_BANKS_IN_SEGMENT) - -#if defined(__ASSEMBLER__) -#define LPSRAM_MASK(ignored) ((1 << PLATFORM_LPSRAM_EBB_COUNT) - 1) - -#define HPSRAM_MASK(seg_idx) ((1 << (PLATFORM_HPSRAM_EBB_COUNT \ - - EBB_BANKS_IN_SEGMENT * seg_idx)) - 1) -#else -#define LPSRAM_MASK(ignored) ((1ULL << PLATFORM_LPSRAM_EBB_COUNT) - 1) - -#define HPSRAM_MASK(seg_idx) ((1ULL << (PLATFORM_HPSRAM_EBB_COUNT \ - - EBB_BANKS_IN_SEGMENT * seg_idx)) - 1) -#endif - -#define LPSRAM_SIZE (PLATFORM_LPSRAM_EBB_COUNT * SRAM_BANK_SIZE) - #define HEAP_BUF_ALIGNMENT PLATFORM_DCACHE_ALIGN /** \brief EDF task's default stack size in bytes. */ diff --git a/src/platform/posix/include/platform/lib/memory.h b/src/platform/posix/include/platform/lib/memory.h index ba44a5e53285..e15e5f370aec 100644 --- a/src/platform/posix/include/platform/lib/memory.h +++ b/src/platform/posix/include/platform/lib/memory.h @@ -39,11 +39,6 @@ static inline void *platform_shared_get(void *ptr, int bytes) return ptr; } -#define SRAM_BANK_SIZE 0x10000 -#define EBB_BANKS_IN_SEGMENT 32 -#define PLATFORM_HPSRAM_EBB_COUNT 32 -#define PLATFORM_LPSRAM_EBB_COUNT 1 - #define SHARED_DATA /**/ #endif /* PLATFORM_HOST_PLATFORM_MEMORY_H */ diff --git a/src/platform/tigerlake/include/platform/lib/memory.h b/src/platform/tigerlake/include/platform/lib/memory.h index ff33d3b5bd97..63802920ac95 100644 --- a/src/platform/tigerlake/include/platform/lib/memory.h +++ b/src/platform/tigerlake/include/platform/lib/memory.h @@ -333,12 +333,6 @@ #define SOF_STACK_SIZE (CONFIG_SOF_STACK_SIZE) #define SOF_STACK_TOTAL_SIZE (CONFIG_CORE_COUNT * SOF_STACK_SIZE) -/* SOF Core S configuration */ -#define SOF_CORE_S_SIZE \ - ALIGN((HEAP_SYSTEM_S_SIZE + HEAP_SYS_RUNTIME_S_SIZE + SOF_STACK_SIZE),\ - SRAM_BANK_SIZE) -#define SOF_CORE_S_T_SIZE ((CONFIG_CORE_COUNT - 1) * SOF_CORE_S_SIZE) - /* * The LP SRAM Heap and Stack on Tigerlake are organised like this :- *