From 20142d350f4b013cc108ac5de4be183e678a0ba5 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 14:30:43 +0300 Subject: [PATCH 1/7] platform: tigerlake: move remain use of shim.h to cavs code The only remaining user of the SOF shim.h platform interface is Intel Tiger Lake platform. And even for this target, only a very small part of the interface is used. Everything else is either not used, and/or moved to Zephyr. Move the remaining definitions to the Tiger Lake implementation, allowing the interface to be removed from SOF platform layer. Signed-off-by: Kai Vehmanen --- src/platform/intel/cavs/platform.c | 11 + .../tigerlake/include/platform/lib/shim.h | 258 +----------------- src/platform/tigerlake/lib/clk.c | 34 +++ 3 files changed, 46 insertions(+), 257 deletions(-) diff --git a/src/platform/intel/cavs/platform.c b/src/platform/intel/cavs/platform.c index 2f4602b4c222..50b482d1e905 100644 --- a/src/platform/intel/cavs/platform.c +++ b/src/platform/intel/cavs/platform.c @@ -81,6 +81,17 @@ static const struct sof_ipc_fw_ready ready #define CAVS_DEFAULT_RO_FOR_MEM SHIM_CLKCTL_OCS_HP_RING #endif +#include + +/* DSP IPC for Host Registers */ +#define IPC_DIPCIDR 0x10 +#define IPC_DIPCIDD 0x18 + +static inline void ipc_write(uint32_t reg, uint32_t val) +{ + *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val; +} + int platform_boot_complete(uint32_t boot_message) { struct ipc_cmd_hdr header; diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h index 60a512e8d80e..ec68f32070eb 100644 --- a/src/platform/tigerlake/include/platform/lib/shim.h +++ b/src/platform/tigerlake/include/platform/lib/shim.h @@ -12,263 +12,7 @@ #ifndef __PLATFORM_LIB_SHIM_H__ #define __PLATFORM_LIB_SHIM_H__ -#include -#include -#include -#include - -/* DSP IPC for Host Registers */ -#define IPC_DIPCTDR 0x00 -#define IPC_DIPCTDA 0x04 -#define IPC_DIPCTDD 0x08 -#define IPC_DIPCIDR 0x10 -#define IPC_DIPCIDA 0x14 -#define IPC_DIPCIDD 0x18 -#define IPC_DIPCCTL 0x28 - -#define IPC_DSP_OFFSET 0x10 - -/* DSP IPC for intra DSP communication */ -#define IPC_IDCTFC(x) (0x0 + x * IPC_DSP_OFFSET) -#define IPC_IDCTEFC(x) (0x4 + x * IPC_DSP_OFFSET) -#define IPC_IDCITC(x) (0x8 + x * IPC_DSP_OFFSET) -#define IPC_IDCIETC(x) (0xc + x * IPC_DSP_OFFSET) -#define IPC_IDCCTL 0x50 - -/* IDCTFC */ -#define IPC_IDCTFC_BUSY BIT(31) -#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF - -/* IDCTEFC */ -#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF - -/* IDCITC */ -#define IPC_IDCITC_BUSY BIT(31) -#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF - -/* IDCIETC */ -#define IPC_IDCIETC_DONE BIT(30) -#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF - -/* IDCCTL */ -#define IPC_IDCCTL_IDCIDIE(x) (0x100 << (x)) -#define IPC_IDCCTL_IDCTBIE(x) BIT(x) - -#define IRQ_CPU_OFFSET 0x40 - -#define REG_IRQ_IL2MSD(xcpu) (0x0 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MCD(xcpu) (0x4 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2MD(xcpu) (0x8 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL2SD(xcpu) (0xc + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL2MD_ALL 0x03F181F0 - -#define REG_IRQ_IL3MSD(xcpu) (0x10 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MCD(xcpu) (0x14 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3MD(xcpu) (0x18 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL3SD(xcpu) (0x1c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL3MD_ALL 0x807F81FF - -#define REG_IRQ_IL4MSD(xcpu) (0x20 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MCD(xcpu) (0x24 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4MD(xcpu) (0x28 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL4SD(xcpu) (0x2c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL4MD_ALL 0x807F81FF - -#define REG_IRQ_IL5MSD(xcpu) (0x30 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MCD(xcpu) (0x34 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5MD(xcpu) (0x38 + (xcpu * IRQ_CPU_OFFSET)) -#define REG_IRQ_IL5SD(xcpu) (0x3c + (xcpu * IRQ_CPU_OFFSET)) - -/* all mask valid bits */ -#define REG_IRQ_IL5MD_ALL 0xFFFFC0CF - -#define REG_IRQ_IL2RSD 0x100 -#define REG_IRQ_IL3RSD 0x104 -#define REG_IRQ_IL4RSD 0x108 -#define REG_IRQ_IL5RSD 0x10c - -#define REG_IRQ_LVL5_LP_GPDMA0_MASK (0xff << 16) -#define REG_IRQ_LVL5_LP_GPDMA1_MASK (0xff << 24) - -/* DSP Shim Registers */ -#define SHIM_DSPWC 0x20 /* DSP Wall Clock */ -#define SHIM_DSPWCL 0x20 /* DSP Wall Clock Low */ -#define SHIM_DSPWCH 0x24 /* DSP Wall Clock High */ -#define SHIM_DSPWCTCS 0x28 /* DSP Wall Clock Timer Control & Status */ -#define SHIM_DSPWCT0C 0x30 /* DSP Wall Clock Timer 0 Compare */ -#define SHIM_DSPWCT1C 0x38 /* DSP Wall Clock Timer 1 Compare */ - -#define SHIM_DSPWCTCS_T1T BIT(5) /* Timer 1 triggered */ -#define SHIM_DSPWCTCS_T0T BIT(4) /* Timer 0 triggered */ -#define SHIM_DSPWCTCS_T1A BIT(1) /* Timer 1 armed */ -#define SHIM_DSPWCTCS_T0A BIT(0) /* Timer 0 armed */ - -/** \brief Clock control */ -#define SHIM_CLKCTL 0x78 - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request WOVCRO Clock */ -#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) - -/** \brief Request XTAL Oscillator Clock */ -#define SHIM_CLKCTL_RXOSCC BIT(30) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Tensilica Core Prevent Local Clock Gating */ -#define SHIM_CLKCTL_TCPLCG_EN(x) BIT(16 + (x)) -#define SHIM_CLKCTL_TCPLCG_DIS(x) 0 -#define SHIM_CLKCTL_TCPLCG_DIS_ALL (SHIM_CLKCTL_TCPLCG_DIS(0) | \ - SHIM_CLKCTL_TCPLCG_DIS(1) | \ - SHIM_CLKCTL_TCPLCG_DIS(2) | \ - SHIM_CLKCTL_TCPLCG_DIS(3)) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 -#define SHIM_CLKCTL_WOVCROSC BIT(3) - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV2 0 -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 -#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) - -/* Core clock PLL divisor */ -#define SHIM_CLKCTL_DPCS_MASK(x) BIT(2) - -/* Prevent Audio PLL Shutdown */ -#define SHIM_CLKCTL_TCPAPLLS BIT(7) - -/* 0--from PLL, 1--from oscillator */ -#define SHIM_CLKCTL_HDCS BIT(4) - -/* Oscillator select */ -#define SHIM_CLKCTL_HDOCS BIT(2) - -/* HP memory clock PLL divisor */ -#define SHIM_CLKCTL_HPMPCS BIT(0) - -/** \brief Mask for requesting clock - */ -#define SHIM_CLKCTL_OSC_REQUEST_MASK \ - (SHIM_CLKCTL_RHROSCC | SHIM_CLKCTL_RXOSCC | \ - SHIM_CLKCTL_RLROSCC) - -/** \brief Mask for setting previously requested clock - */ -#define SHIM_CLKCTL_OSC_SOURCE_MASK \ - (SHIM_CLKCTL_OCS_HP_RING | SHIM_CLKCTL_LMCS_DIV4 | \ - SHIM_CLKCTL_HMCS_DIV4) - -/** \brief Clock status */ -#define SHIM_CLKSTS 0x7C - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief WOVCRO Clock Status */ -#define SHIM_CLKSTS_WOV_CRO BIT(4) - -/** \brief XTAL Oscillator Clock Status */ -#define SHIM_CLKSTS_XOSCCS BIT(30) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#define SHIM_PWRCTL 0x90 -#define SHIM_PWRCTL_TCPDSPPG(x) BIT(x) -#define SHIM_PWRCTL_TCPCTLPG BIT(4) - -#define SHIM_PWRSTS 0x92 - -#define SHIM_LPSCTL 0x94 -#define SHIM_LPSCTL_BID BIT(7) -#define SHIM_LPSCTL_FDSPRUN BIT(9) -#define SHIM_LPSCTL_BATTR_0 BIT(12) - -/** \brief GPDMA shim registers Control */ -#define SHIM_GPDMA_BASE_OFFSET 0x6500 -#define SHIM_GPDMA_BASE(x) (SHIM_GPDMA_BASE_OFFSET + (x) * 0x100) - -/** \brief GPDMA Clock Control */ -#define SHIM_GPDMA_CLKCTL(x) (SHIM_GPDMA_BASE(x) + 0x4) -/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */ -#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0) - -/** \brief GPDMA Channel Linear Link Position Control */ -#define SHIM_GPDMA_CHLLPC(x, y) (SHIM_GPDMA_BASE(x) + 0x10 + (y) * 0x10) -#define SHIM_GPDMA_CHLLPC_EN BIT(7) -#define SHIM_GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x) - -#define SHIM_GPDMA_CHLLPL(x, y) (SHIM_GPDMA_BASE(x) + 0x18 + (y) * 0x10) -#define SHIM_GPDMA_CHLLPU(x, y) (SHIM_GPDMA_BASE(x) + 0x1c + (y) * 0x10) - -/* I2S SHIM Registers */ -#define I2SLCTL 0x71C04 - -/* SPA register should be set for each I2S port and DSP should - * wait for CPA to be set - */ -#define I2SLCTL_SPA(x) BIT(0 + x) -#define I2SLCTL_CPA(x) BIT(8 + x) - -#define SHIM_L2_MECS (SHIM_BASE + 0xd0) - -/** \brief LDO Control */ -#define SHIM_LDOCTL 0xA4 -#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16) -#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_ON (3 << 0 | 3 << 16) -#define SHIM_LDOCTL_LPSRAM_LDO_ON (3 << 2) -#define SHIM_LDOCTL_HPSRAM_LDO_BYPASS (BIT(0) | BIT(16)) -#define SHIM_LDOCTL_LPSRAM_LDO_BYPASS BIT(2) -#define SHIM_LDOCTL_HPSRAM_LDO_OFF (0 << 0) -#define SHIM_LDOCTL_LPSRAM_LDO_OFF (0 << 2) - -#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x)) -#define LPGPDMA_CTLOSEL_FLAG BIT(15) -#define LPGPDMA_CHOSEL_FLAG 0xFF - -#define DSP_INIT_IOPO 0x71A68 -#define IOPO_DMIC_FLAG BIT(0) -#define IOPO_I2S_FLAG MASK(DAI_NUM_SSP_BASE + DAI_NUM_SSP_EXT + 7, 8) - -#define DSP_INIT_GENO 0x71A6C -#define GENO_MDIVOSEL BIT(1) -#define GENO_DIOPTOSEL BIT(2) - -#define DSP_INIT_ALHO 0x71A70 -#define ALHO_ASO_FLAG BIT(0) -#define ALHO_CSO_FLAG BIT(1) -#define ALHO_CFO_FLAG BIT(2) - -#define SHIM_SVCFG 0xF4 -#define SHIM_SVCFG_FORCE_L1_EXIT BIT(1) - -/* host windows */ -#define DMWBA(x) (HOST_WIN_BASE(x) + 0x0) -#define DMWLO(x) (HOST_WIN_BASE(x) + 0x4) - -#define DMWBA_ENABLE BIT(0) -#define DMWBA_READONLY BIT(1) - -/* DMIC power ON bit */ -#define DMICLCTL_SPA ((uint32_t) BIT(0)) - -/* DMIC disable clock gating */ -#define DMIC_DCGD ((uint32_t) BIT(30)) +/* no-op */ #endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/src/platform/tigerlake/lib/clk.c b/src/platform/tigerlake/lib/clk.c index 46734476efe9..581e9ba3eb40 100644 --- a/src/platform/tigerlake/lib/clk.c +++ b/src/platform/tigerlake/lib/clk.c @@ -9,6 +9,40 @@ #include #include +/** \brief Request HP RING Oscillator Clock */ +#define SHIM_CLKCTL_RHROSCC BIT(31) + +/** \brief Request WOVCRO Clock */ +#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) + +/** \brief Request LP RING Oscillator Clock */ +#define SHIM_CLKCTL_RLROSCC BIT(29) + +/** \brief Oscillator Clock Select*/ +#define SHIM_CLKCTL_OCS_HP_RING BIT(2) +#define SHIM_CLKCTL_OCS_LP_RING 0 +#define SHIM_CLKCTL_WOVCROSC BIT(3) + +/** \brief LP Memory Clock Select */ +#define SHIM_CLKCTL_LMCS_DIV2 0 +#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) + +/** \brief HP Memory Clock Select */ +#define SHIM_CLKCTL_HMCS_DIV2 0 +#define SHIM_CLKCTL_HMCS_DIV4 BIT(0) + +/** \brief HP RING Oscillator Clock Status */ +#define SHIM_CLKSTS_HROSCCS BIT(31) + +/** \brief WOVCRO Clock Status */ +#define SHIM_CLKSTS_WOV_CRO BIT(4) + +/** \brief XTAL Oscillator Clock Status */ +#define SHIM_CLKSTS_XOSCCS BIT(30) + +/** \brief LP RING Oscillator Clock Status */ +#define SHIM_CLKSTS_LROSCCS BIT(29) + static const struct freq_table platform_cpu_freq[] = { { 38400000, 38400 }, { 120000000, 120000 }, From 07a42687a32e81dacd48d90965ccaae418bb4c59 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 14:44:58 +0300 Subject: [PATCH 2/7] platform: intel: cavs: remove unused dw-dma.h Only native Zephyr drivers supported now for Intel cAVS, so dw-dma.h can be removed. Removing this file allow to remove the SOF shim.h layer. Signed-off-by: Kai Vehmanen --- .../intel/cavs/include/cavs/drivers/dw-dma.h | 113 ------------------ 1 file changed, 113 deletions(-) delete mode 100644 src/platform/intel/cavs/include/cavs/drivers/dw-dma.h diff --git a/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h b/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h deleted file mode 100644 index a1b0ee06e5ad..000000000000 --- a/src/platform/intel/cavs/include/cavs/drivers/dw-dma.h +++ /dev/null @@ -1,113 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __PLATFORM_DRIVERS_DW_DMA_H__ - -#ifndef __CAVS_LIB_DW_DMA_H__ -#define __CAVS_LIB_DW_DMA_H__ - -#include -#include -#include - -#include - -/* number of supported DW-DMACs */ -#define PLATFORM_NUM_DW_DMACS 2 - -/* index of the first DW-DMAC in the array */ -#define PLATFORM_DW_DMA_INDEX 0 - -/* DMA treats PHY addresses as host address unless within DSP region */ -#define PLATFORM_DW_DMA_HOST_MASK 0x00000000 - -/* CTL_HI */ -#define DW_CTLH_CLASS(x) SET_BITS(31, 29, x) -#define DW_CTLH_WEIGHT(x) SET_BITS(28, 18, x) -#define DW_CTLH_DONE(x) SET_BIT(17, x) -#define DW_CTLH_BLOCK_TS_MASK MASK(16, 0) - -/* CFG_LO */ -#define DW_CFG_RELOAD_DST BIT(31) -#define DW_CFG_RELOAD_SRC BIT(30) -#define DW_CFG_CTL_HI_UPD_EN BIT(5) - -/* CFG_HI */ -#define DW_CFGH_DST_PER_EXT(x) SET_BITS(31, 30, x) -#define DW_CFGH_SRC_PER_EXT(x) SET_BITS(29, 28, x) -#define DW_CFGH_DST_PER(x) SET_BITS(7, 4, x) -#define DW_CFGH_SRC_PER(x) SET_BITS(3, 0, x) -#define DW_CFGH_DST(x) \ - (DW_CFGH_DST_PER_EXT((x) >> 4) | DW_CFGH_DST_PER(x)) -#define DW_CFGH_SRC(x) \ - (DW_CFGH_SRC_PER_EXT((x) >> 4) | DW_CFGH_SRC_PER(x)) - -/* default initial setup register values */ -#define DW_CFG_LOW_DEF 0x3 -#define DW_CFG_HIGH_DEF 0x0 - -/* LLPC address */ -#define DW_CHLLPC(dma, chan) \ - SHIM_GPDMA_CHLLPC((dma)->plat_data.id, (chan)->index) - -#define DW_CHLLPL(dma, chan) \ - SHIM_GPDMA_CHLLPL((dma)->plat_data.id, (chan)->index) - -#define DW_CHLLPU(dma, chan) \ - SHIM_GPDMA_CHLLPU((dma)->plat_data.id, (chan)->index) - -#define platform_dw_dma_set_class(chan, lli, class) \ - (lli->ctrl_hi |= DW_CTLH_CLASS(class)) - -#define platform_dw_dma_set_transfer_size(chan, lli, size) \ - (lli->ctrl_hi |= (size & DW_CTLH_BLOCK_TS_MASK)) - -static inline void platform_dw_dma_llp_config(struct dma *dma, - struct dma_chan_data *chan, - uint32_t config) -{ - shim_write(DW_CHLLPC(dma, chan), SHIM_GPDMA_CHLLPC_DHRS(config)); -} - -static inline void platform_dw_dma_llp_enable(struct dma *dma, - struct dma_chan_data *chan) -{ - uint32_t val; - - val = shim_read(DW_CHLLPC(dma, chan)); - if (!(val & SHIM_GPDMA_CHLLPC_EN)) - shim_write(DW_CHLLPC(dma, chan), val | SHIM_GPDMA_CHLLPC_EN); -} - -static inline void platform_dw_dma_llp_disable(struct dma *dma, - struct dma_chan_data *chan) -{ - shim_write(DW_CHLLPC(dma, chan), - shim_read(DW_CHLLPC(dma, chan)) & ~SHIM_GPDMA_CHLLPC_EN); -} - -static inline void platform_dw_dma_llp_read(struct dma *dma, - struct dma_chan_data *chan, - uint32_t *llp_l, - uint32_t *llp_u) -{ - *llp_l = shim_read(DW_CHLLPL(dma, chan)); - *llp_u = shim_read(DW_CHLLPU(dma, chan)); -} - -static inline struct dw_lli *platform_dw_dma_lli_get(struct dw_lli *lli) -{ - return cache_to_uncache(lli); -} - -#endif /* __CAVS_LIB_DW_DMA_H__ */ - -#else - -#error "This file shouldn't be included from outside of platform/drivers/dw-dma.h" - -#endif /* __PLATFORM_DRIVERS_DW_DMA_H__ */ From 47296a819297994389b2617d4f6891a3d879520e Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 14:47:37 +0300 Subject: [PATCH 3/7] platform: intel: cavs: remove unused asm_memory_management.h Memory management has been moved to Zephyr for these platforms, so this file can be removed. Removing this file allow to remove the SOF shim.h layer. Signed-off-by: Kai Vehmanen --- .../include/cavs/lib/asm_memory_management.h | 80 ------------------- 1 file changed, 80 deletions(-) delete mode 100644 src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h diff --git a/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h b/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h deleted file mode 100644 index 0fc46a7cb6f1..000000000000 --- a/src/platform/intel/cavs/include/cavs/lib/asm_memory_management.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2018 Intel Corporation. All rights reserved. - * - * Author: Lech Betlej - */ - -/** - * \file - * \brief Macros for power gating memory banks specific for cAVS 2.5 (Tiger Lake) - * \author Lech Betlej - */ - -#ifndef __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ -#define __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ - -#ifndef ASSEMBLY -#warning "ASSEMBLY macro not defined. Header can't be included in C files" -#warning "The file is intended to be included in assembly files only." -#endif - -#include - -#include -#include - -/** - * Macro powers down entire HPSRAM. On entry literals and code for section from - * where this code is executed need to be placed in memory which is not - * HPSRAM (in case when this code is located in HPSRAM, lock memory in L1$ or - * L1 SRAM) - */ -.macro m_cavs_hpsram_power_down_entire ax, ay, az - // SEGMENT #0 - movi \az, SHIM_HSPGCTL(0) - movi \ax, SHIM_HSPGISTS(0) - movi \ay, HPSRAM_MASK(0) - s32i \ay, \ax, 0 - memw -1 : - l32i \ax, \az, 0 - bne \ax, \ay, 1b - - // SEGMENT #1 - movi \az, SHIM_HSPGCTL(1) - movi \ax, SHIM_HSPGISTS(1) - movi \ay, HPSRAM_MASK(1) - s32i \ay, \ax, 0 - memw -1 : - l32i \ax, \az, 0 - bne \ax, \ay, 1b -.endm - -.macro m_cavs_hpsram_power_change segment_index, mask, ax, ay, az - movi \ax, SHIM_HSPGCTL(\segment_index) - movi \ay, SHIM_HSPGISTS(\segment_index) - s32i \mask, \ax, 0 - memw - // assumed that HDA shared dma buffer will be in LPSRAM -1 : - l32i \ax, \ay, 0 - bne \ax, \mask, 1b -.endm - -.macro m_cavs_lpsram_power_down_entire ax, ay, az, loop_cnt_addr - movi \az, LSPGISTS - movi \ax, LSPGCTL - movi \ay, LPSRAM_MASK() - s32i \ay, \ax, 0 - memw - // assumed that HDA shared dma buffer will be in LPSRAM - movi \ax, \loop_cnt_addr - l32i \ax, \ax, 0 -1 : - addi \ax, \ax, -1 - bnez \ax, 1b -.endm - -#endif /* __CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__ */ From f360c7d02e78291195c166cb058eccc31cb6377b Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 14:49:29 +0300 Subject: [PATCH 4/7] platform: intel: cavs: remove unused pm_memory.h Memory power management has been moved to Zephyr for these platforms, so this file can be removed. Removing this file allow to remove the SOF shim.h layer. Signed-off-by: Kai Vehmanen --- .../intel/cavs/include/cavs/lib/pm_memory.h | 198 ------------------ 1 file changed, 198 deletions(-) delete mode 100644 src/platform/intel/cavs/include/cavs/lib/pm_memory.h diff --git a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h b/src/platform/intel/cavs/include/cavs/lib/pm_memory.h deleted file mode 100644 index 93237f79365b..000000000000 --- a/src/platform/intel/cavs/include/cavs/lib/pm_memory.h +++ /dev/null @@ -1,198 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2020 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -/** - * \file cavs/lib/pm_memory.h - * \brief Memory power management header file for cAVS platforms - * \author Tomasz Lauda - */ - -#ifndef __CAVS_LIB_PM_MEMORY_H__ -#define __CAVS_LIB_PM_MEMORY_H__ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define MEMORY_POWER_CHANGE_DELAY 256 -#define MEMORY_POWER_CHANGE_TIMEOUT (256 * MEMORY_POWER_CHANGE_DELAY) - -/** - * \brief Retrieves register mask for given segment. - * \param[in] start_bank Start bank id. - * \param[in] end_bank End bank id. - * \param[in] segment Segment id. - * \return Register mask. - */ -static inline uint32_t cavs_pm_memory_hp_sram_mask_get(uint32_t start_bank, - uint32_t end_bank, - int segment) -{ - uint32_t first_in_segment; - uint32_t last_in_segment; - - first_in_segment = segment * EBB_SEGMENT_SIZE; - last_in_segment = ((segment + 1) * EBB_SEGMENT_SIZE) - 1; - - /* not in this segment */ - if (start_bank > last_in_segment || end_bank < first_in_segment) - return 0; - - if (start_bank < first_in_segment) - start_bank = first_in_segment; - - if (end_bank > last_in_segment) - end_bank = last_in_segment; - - return MASK(end_bank - first_in_segment, start_bank - first_in_segment); -} - -/** - * \brief Sets register mask for given segment. - * \param[in] mask Register mask to be set. - * \param[in] segment Segment id. - * \param[in] enabled True if banks should be enabled, false otherwise. - */ -static inline void cavs_pm_memory_hp_sram_mask_set(uint32_t mask, int segment, - bool enabled) -{ - uint32_t expected = enabled ? 0 : mask; - uint32_t delay = 0; - uint32_t i; - - io_reg_update_bits(&HPSRAM_REGS(segment)->HSxPGCTL, mask, enabled ? 0 : mask); - io_reg_update_bits(&HPSRAM_REGS(segment)->HSxRMCTL, mask, enabled ? 0 : mask); - - /* Double check of PG status needed to confirm EBB readiness */ - for (i = 0; i < 2; i++) { - idelay(MEMORY_POWER_CHANGE_DELAY); - - while ((io_reg_read(&HPSRAM_REGS(segment)->HSxPGISTS) & mask) != expected) { - idelay(MEMORY_POWER_CHANGE_DELAY); - delay += MEMORY_POWER_CHANGE_DELAY; - if (delay >= MEMORY_POWER_CHANGE_TIMEOUT) - platform_panic(SOF_IPC_PANIC_MEM); - } - delay = 0; - } -} - -static inline void cavs_pm_memory_hp_sram_banks_power_gate( - uint32_t start_bank_id, uint32_t ending_bank_id, bool enabled) -{ - uint32_t mask; - int i; - - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_ON); - - idelay(MEMORY_POWER_CHANGE_DELAY); - - for (i = 0; i < PLATFORM_HPSRAM_SEGMENTS; ++i) { - mask = cavs_pm_memory_hp_sram_mask_get(start_bank_id, - ending_bank_id, i); - cavs_pm_memory_hp_sram_mask_set(mask, i, enabled); - } - - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS); -} - -/** - * \brief Sets HP SRAM power gating. - * - * Power gates address range only on full banks. If given address form mid block - * it will try to narrow down power gate to nearest full banks. - * - * \param[in] ptr Ptr to address from which to start gating. - * \param[in] size Size of memory to manage. - * \param[in] enabled Deciding banks desired state (true powered false gated). - */ -void cavs_pm_memory_hp_sram_power_gate(void *ptr, uint32_t size, bool enabled); - -#if CONFIG_LP_SRAM - -/** - * \brief Sets LP SRAM enabled gating hw bit mask for memory banks. - * \param[in] start_bank_id Id of first bank to be managed (inclusive) 0 based. - * \param[in] ending_bank_id Id of last bank to be managed (inclusive) 0 based. - * \param[in] enabled Deciding banks desired state (true powered false gated). - */ -static inline void cavs_pm_memory_lp_sram_banks_power_gate( - uint32_t start_bank_id, uint32_t ending_bank_id, bool enabled) -{ - uint32_t mask = MASK(ending_bank_id, start_bank_id); - uint32_t expected = enabled ? 0 : mask; - uint32_t delay = 0; - - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_LPSRAM_LDO_ON); - - idelay(MEMORY_POWER_CHANGE_DELAY); - - io_reg_update_bits(LSPGCTL, mask, enabled ? 0 : mask); - - idelay(MEMORY_POWER_CHANGE_DELAY); - - while ((io_reg_read(LSPGISTS) & mask) != expected) { - idelay(MEMORY_POWER_CHANGE_DELAY); - delay += MEMORY_POWER_CHANGE_DELAY; - if (delay >= MEMORY_POWER_CHANGE_TIMEOUT) - platform_panic(SOF_IPC_PANIC_MEM); - } - - shim_write(SHIM_LDOCTL, SHIM_LDOCTL_HPSRAM_LDO_BYPASS); -} - -/** - * \brief Sets LP SRAM power gating. - * - * Power gates address range only on full banks. If given address form mid block - * it will try to narrow down power gate to nearest full banks. - * - * \param[in] ptr Ptr to address from which to start gating. - * \param[in] size Size of memory to manage. - * \param[in] enabled Deciding banks desired state (true powered false gated). - */ -void cavs_pm_memory_lp_sram_power_gate(void *ptr, uint32_t size, bool enabled); - -#endif /* CONFIG_LP_SRAM */ - -#if CONFIG_L1_DRAM - -static inline void cavs_pm_memory_l1_dram_banks_power_gate( - uint32_t start_bank_id, uint32_t ending_bank_id, bool enable) -{ - uint32_t mask = MASK(start_bank_id, ending_bank_id); - uint32_t pgctl = io_reg_read(L1_MEM_DRAM_PGCTL); - uint32_t expected = enable ? 0 : mask; - uint32_t delay = 0; - - if (enable) - pgctl &= ~mask; - else - pgctl |= mask; - - io_reg_write(L1_MEM_DRAM_PGCTL, pgctl); - - while ((io_reg_read(L1_MEM_DRAM_PGISTS) & mask) != expected) { - idelay(MEMORY_POWER_CHANGE_DELAY); - delay += MEMORY_POWER_CHANGE_DELAY; - if (delay >= MEMORY_POWER_CHANGE_TIMEOUT) - platform_panic(SOF_IPC_PANIC_MEM); - } -} - -#endif /* CONFIG_L1_DRAM */ - -#endif /* __CAVS_LIB_PM_MEMORY_H__ */ From d680b32f818524c47b3d431d32ad25311e74fd20 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 15:01:24 +0300 Subject: [PATCH 5/7] platform: intel: remove shim.h interface as it's no longer needed All users of shim.h have been either removed and/or moved to Zephyr, so the interface can be removed from codebase. Signed-off-by: Kai Vehmanen --- src/platform/intel/ace/include/ace/lib/clk.h | 1 - .../intel/cavs/include/cavs/lib/clk.h | 1 - .../intel/cavs/include/cavs/lib/shim.h | 108 ------------------ .../library/include/platform/lib/shim.h | 24 ---- .../lunarlake/include/platform/lib/shim.h | 53 --------- .../meteorlake/include/platform/lib/shim.h | 53 --------- .../pantherlake/include/platform/lib/shim.h | 58 ---------- .../tigerlake/include/platform/lib/shim.h | 23 ---- 8 files changed, 321 deletions(-) delete mode 100644 src/platform/intel/cavs/include/cavs/lib/shim.h delete mode 100644 src/platform/library/include/platform/lib/shim.h delete mode 100644 src/platform/lunarlake/include/platform/lib/shim.h delete mode 100644 src/platform/meteorlake/include/platform/lib/shim.h delete mode 100644 src/platform/pantherlake/include/platform/lib/shim.h delete mode 100644 src/platform/tigerlake/include/platform/lib/shim.h diff --git a/src/platform/intel/ace/include/ace/lib/clk.h b/src/platform/intel/ace/include/ace/lib/clk.h index c08fb4b4b5cb..2a4fdfe1495d 100644 --- a/src/platform/intel/ace/include/ace/lib/clk.h +++ b/src/platform/intel/ace/include/ace/lib/clk.h @@ -22,7 +22,6 @@ #include #include #include -#include #include struct sof; diff --git a/src/platform/intel/cavs/include/cavs/lib/clk.h b/src/platform/intel/cavs/include/cavs/lib/clk.h index ab38315d800d..eec51ac3963e 100644 --- a/src/platform/intel/cavs/include/cavs/lib/clk.h +++ b/src/platform/intel/cavs/include/cavs/lib/clk.h @@ -21,7 +21,6 @@ #include #include #include -#include #include struct sof; diff --git a/src/platform/intel/cavs/include/cavs/lib/shim.h b/src/platform/intel/cavs/include/cavs/lib/shim.h deleted file mode 100644 index 77fee415fd5e..000000000000 --- a/src/platform/intel/cavs/include/cavs/lib/shim.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2020 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifdef __PLATFORM_LIB_SHIM_H__ - -#ifndef __CAVS_LIB_SHIM_H__ -#define __CAVS_LIB_SHIM_H__ - -#ifndef ASSEMBLY - -#include -#include - -static inline uint16_t shim_read16(uint32_t reg) -{ - return *((volatile uint16_t*)(SHIM_BASE + reg)); -} - -static inline void shim_write16(uint32_t reg, uint16_t val) -{ - *((volatile uint16_t*)(SHIM_BASE + reg)) = val; -} - -static inline uint32_t shim_read(uint32_t reg) -{ - return *((volatile uint32_t*)(SHIM_BASE + reg)); -} - -static inline void shim_write(uint32_t reg, uint32_t val) -{ - *((volatile uint32_t*)(SHIM_BASE + reg)) = val; -} - -static inline uint64_t shim_read64(uint32_t reg) -{ - return *((volatile uint64_t*)(SHIM_BASE + reg)); -} - -static inline void shim_write64(uint32_t reg, uint64_t val) -{ - *((volatile uint64_t*)(SHIM_BASE + reg)) = val; -} - -static inline uint32_t sw_reg_read(uint32_t reg) -{ - return *((volatile uint32_t*)((SRAM_SW_REG_BASE - - SRAM_ALIAS_OFFSET) + reg)); -} - -static inline void sw_reg_write(uint32_t reg, uint32_t val) -{ - *((volatile uint32_t*)((SRAM_SW_REG_BASE - - SRAM_ALIAS_OFFSET) + reg)) = val; -} - -static inline uint32_t mn_reg_read(uint32_t reg, uint32_t id) -{ - return *((volatile uint32_t*)(MN_BASE + reg)); -} - -static inline void mn_reg_write(uint32_t reg, uint32_t id, uint32_t val) -{ - *((volatile uint32_t*)(MN_BASE + reg)) = val; -} - -static inline uint32_t irq_read(uint32_t reg) -{ - return *((volatile uint32_t*)(IRQ_BASE + reg)); -} - -static inline void irq_write(uint32_t reg, uint32_t val) -{ - *((volatile uint32_t*)(IRQ_BASE + reg)) = val; -} - -static inline uint32_t ipc_read(uint32_t reg) -{ - return *((volatile uint32_t*)(IPC_HOST_BASE + reg)); -} - -static inline void ipc_write(uint32_t reg, uint32_t val) -{ - *((volatile uint32_t*)(IPC_HOST_BASE + reg)) = val; -} - -static inline uint32_t idc_read(uint32_t reg, uint32_t core_id) -{ - return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)); -} - -static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val) -{ - *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val; -} - -#endif /* !ASSEMBLY */ - -#endif /* __CAVS_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of platform/lib/shim.h" - -#endif /* __PLATFORM_LIB_SHIM_H__ */ diff --git a/src/platform/library/include/platform/lib/shim.h b/src/platform/library/include/platform/lib/shim.h deleted file mode 100644 index 10a4f517bf53..000000000000 --- a/src/platform/library/include/platform/lib/shim.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2016 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include - -static inline uint32_t shim_read(uint32_t reg) {return 0; } -static inline void shim_write(uint32_t reg, uint32_t val) {} - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/lunarlake/include/platform/lib/shim.h b/src/platform/lunarlake/include/platform/lib/shim.h deleted file mode 100644 index 777f18fea377..000000000000 --- a/src/platform/lunarlake/include/platform/lib/shim.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2023 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include -#include - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request WOVCRO Clock */ -#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 -#define SHIM_CLKCTL_WOVCROSC BIT(3) - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief WOVCRO Clock Status */ -#define SHIM_CLKSTS_WOV_CRO BIT(4) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/meteorlake/include/platform/lib/shim.h b/src/platform/meteorlake/include/platform/lib/shim.h deleted file mode 100644 index 0bc0c106e77f..000000000000 --- a/src/platform/meteorlake/include/platform/lib/shim.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2022 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include -#include - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request WOVCRO Clock */ -#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 -#define SHIM_CLKCTL_WOVCROSC BIT(3) - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief WOVCRO Clock Status */ -#define SHIM_CLKSTS_WOV_CRO BIT(4) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/pantherlake/include/platform/lib/shim.h b/src/platform/pantherlake/include/platform/lib/shim.h deleted file mode 100644 index 175b8af24980..000000000000 --- a/src/platform/pantherlake/include/platform/lib/shim.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2022-2024 Intel Corporation. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -#include -#include - -/** \brief Request HP RING Oscillator Clock */ -#define SHIM_CLKCTL_RHROSCC BIT(31) - -/** \brief Request WOVCRO Clock */ -#define SHIM_CLKCTL_WOV_CRO_REQUEST BIT(4) - -/** \brief Request LP RING Oscillator Clock */ -#define SHIM_CLKCTL_RLROSCC BIT(29) - -/** \brief Oscillator Clock Select*/ -#define SHIM_CLKCTL_OCS_HP_RING BIT(2) -#define SHIM_CLKCTL_OCS_LP_RING 0 -#define SHIM_CLKCTL_WOVCROSC BIT(3) - -/** \brief LP Memory Clock Select */ -#define SHIM_CLKCTL_LMCS_DIV4 BIT(1) - -/** \brief HP Memory Clock Select */ -#define SHIM_CLKCTL_HMCS_DIV2 0 - -/** \brief HP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_HROSCCS BIT(31) - -/** \brief WOVCRO Clock Status */ -#define SHIM_CLKSTS_WOV_CRO BIT(4) - -/** \brief LP RING Oscillator Clock Status */ -#define SHIM_CLKSTS_LROSCCS BIT(29) - -#define L2HSBPM(x) (0x17A800 + 0x0008 * (x)) -#define SHIM_HSPGCTL(x) (L2HSBPM(x) + 0x0000) - -#define LSPGCTL 0x71D80 - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ diff --git a/src/platform/tigerlake/include/platform/lib/shim.h b/src/platform/tigerlake/include/platform/lib/shim.h deleted file mode 100644 index ec68f32070eb..000000000000 --- a/src/platform/tigerlake/include/platform/lib/shim.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2017 Intel Corporation. All rights reserved. - * - * Author: Liam Girdwood - * Keyon Jie - * Rander Wang - */ - -#ifdef __SOF_LIB_SHIM_H__ - -#ifndef __PLATFORM_LIB_SHIM_H__ -#define __PLATFORM_LIB_SHIM_H__ - -/* no-op */ - -#endif /* __PLATFORM_LIB_SHIM_H__ */ - -#else - -#error "This file shouldn't be included from outside of sof/lib/shim.h" - -#endif /* __SOF_LIB_SHIM_H__ */ From 2b7d0b06b527f082514315ef40d50e17a5b13695 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 15:06:35 +0300 Subject: [PATCH 6/7] xtos: sof/lib/shim.h: remove header Remove the shim.h interface from RTOS layer as there is no use of this interface anymore in SOF codebase. Link: https://github.com/thesofproject/sof/issues/9015 Signed-off-by: Kai Vehmanen --- xtos/include/sof/lib/shim.h | 13 ------------- 1 file changed, 13 deletions(-) delete mode 100644 xtos/include/sof/lib/shim.h diff --git a/xtos/include/sof/lib/shim.h b/xtos/include/sof/lib/shim.h deleted file mode 100644 index 518880f1f953..000000000000 --- a/xtos/include/sof/lib/shim.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright(c) 2019 Intel Corporation. All rights reserved. - * - * Author: Tomasz Lauda - */ - -#ifndef __SOF_LIB_SHIM_H__ -#define __SOF_LIB_SHIM_H__ - -#include - -#endif /* __SOF_LIB_SHIM_H__ */ From 198916cdb860164791279cef785bea2e095a13d9 Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 11 Sep 2024 14:19:02 +0300 Subject: [PATCH 7/7] zephyr: dai.h: fix typos in code comments Fix errors in code documentation to match the implementation. Signed-off-by: Kai Vehmanen --- zephyr/include/sof/lib/dai.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/zephyr/include/sof/lib/dai.h b/zephyr/include/sof/lib/dai.h index a0531e47ff95..cc6914370b58 100644 --- a/zephyr/include/sof/lib/dai.h +++ b/zephyr/include/sof/lib/dai.h @@ -6,12 +6,10 @@ #ifndef __SOF_LIB_DAI_H__ #define __SOF_LIB_DAI_H__ -/* no-op on Zephyr */ - #ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS #include #else #include #endif -#endif /* __SOF_LIB_MEMORY_H__ */ +#endif /* __SOF_LIB_DAI_H__ */