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XADC.xpr
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XADC.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2014.4 -->
<!-- -->
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="2" Path="/home/rd/vivado-outputs/XADC_3_DEM/XADC.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="1651ddd201bd42c7a8d7bcfae4936d28"/>
<Option Name="Part" Val="xc7z010clg400-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="SimulatorLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../zybo-audio/ac_interface"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../ShiftSlice"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../lcd16x2"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../delayz1z2"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../switch_out2n"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../IP"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../IP_VGA_VL"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/bd/System/System.bd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/imports/hdl/System_wrapper.vhd">
<FileInfo>
<Attr Name="ImportPath" Val="$PSRCDIR/sources_1/bd/System/hdl/System_wrapper.vhd"/>
<Attr Name="ImportTime" Val="1492936289"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_axi_fifo_mm_s_0_0/System_axi_fifo_mm_s_0_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_axi_gpio_0_0/System_axi_gpio_0_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_processing_system7_0_0/System_processing_system7_0_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_processing_system7_0_axi_periph_0/System_processing_system7_0_axi_periph_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_rst_processing_system7_0_100M_0/System_rst_processing_system7_0_100M_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_xadc_channel_14_0_0/System_xadc_channel_14_0_0.upgrade_log"/>
<File Path="$PSRCDIR/sources_1/bd/System/ip/System_lcd16x2_ctrl_demo_0_0/System_lcd16x2_ctrl_demo_0_0.upgrade_log"/>
<File Path="$PPRDIR/../../bp_1M_40k_c10k.coe">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System_wrapper"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/System.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PSRCDIR/constrs_1/new/System.xdc"/>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="System_wrapper"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="9">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z010clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
</Run>
</Runs>
<HWSession Dir="hw_1" File="hw.xml"/>
</Project>