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ar.cpp
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ar.cpp
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/*
* UAE Action Replay 1/2/3/1200 and HRTMon support
*
* (c) 2000-2015 Toni Wilen <twilen@arabuusimiehet.com>
* (c) 2003 Mark Cox <markcox@email.com>
*
* Action Replay 1200 (basically old version of HRTMon):
*
* 256k ROM at 0x800000
* 64k RAM at 0x880000
* status register at 0x8c0000 (bit 3 = freeze button, bit 4 = hide)
* custom register writes stored at 0x88f000
* CIA-A at 0x88e000
* CIA-B at 0x88d000
* freeze button = bus error + rom mapped at 0x0
*
* 14.06.2006 first implementation
*
* Action Replay 2/3:
*
* Tested with AR3 ROM version 3.09 (10/13/91) and AR2 2.12 (12/24/90)
*
* Found to work for the following roms by Mark Cox:
* (Yes the date format is inconsistent, i just copied it straight from the rom)
* 1.15
* 2.14 22/02/91 dd/mm/yy
* 3.09 10/13/91 mm/dd/yy
* 3.17 12/17/91 mm/dd/yy
*
* This patch also makes AR3 compatible with KickStart's other than 1.3
* (ROM checksum error is normal with KS != 1.3)
* NOTE: AR has problems with 68020+ processors.
* For maximum compatibility select 68000/68010 and A500 speed from UAE
* options.
*
* How to rip Action Replay 1/2/3 ROM:
*
* Find A500 with AR1/2/3, press 'freeze'-button
*
* type following:
*
* AR1:
* lord olaf<RETURN>
*
* AR2 or AR3:
* may<RETURN>
* the<RETURN>
* force<RETURN>
* be<RETURN>
* with<RETURN>
* you<RETURN>
* new<RETURN> (AR3 only)
*
* AR1: 64K ROM is visible at 0xf00000-0xf0ffff
* and 16K RAM at 0x9fc000-0x9fffff
* AR2: 128K ROM is visible at 0x400000-0x41ffff
* AR3: 256K ROM is visible at 0x400000-0x43ffff
* and 64K RAM at 0x440000-0x44ffff
*
* following command writes ROM to disk:
*
* AR1: sm ar1.rom,f00000 f10000
* AR2: sm ar2.rom,400000 420000
* AR3: sm ar3.rom,400000 440000
*
* NOTE: I (mark) could not get the action replay 1 dump to work as above.
* (also, it will only dump to the action replay special disk format)
* To dump the rom i had to :
* 1. Boot the a500 and start a monitor (e.g. cmon).
* 2. Use the monitor to allocate 64k memory.
* 3. Enter the action replay.
* 4. Enter sysop mode.
* 5. Copy the rom into the address the monitor allocated.
* 6. Exit the action replay.
* 7. Save the ram from the monitor to disk.
*
* I DO NOT REPLY MAILS ASKING FOR ACTION REPLAY ROMS!
*
* AR2/3 hardware notes (not 100% correct..)
*
* first 8 bytes of ROM are not really ROM, they are
* used to read/write cartridge's hardware state
*
* Read/write HW state
*
* 0x400001.B READ:
*
* 11 (3) = freeze was caused by reset condition
* 10 (2) = freeze was caused by 0xBFD100.B WRITE
* 01 (1) = freeze was caused by 0xBFE001.B READ
* 00 (0) = freeze was caused by button press
*
* 0x400001.B WRITE
*
* bit 1 set: enable freeze caused by BFE001.B READ
* bit 0 set: enable freeze caused by BFD100.B WRITE
*
* 0x400002/0x400003: mirrors 0x400000/0x400001
* 0x400006/0x400007: when written to, turns chip-ram overlay off
*
* Reset condition: first chip ram (or non-custom register) write after hardware reset.
*
* cartridge hardware also snoops CPU write accesses to custom chip
* registers (DFF000-DFF1FE). All CPU custom chip write accesses are
* saved to RAM at 0x44f000-0x44f1ff. Note that emulated AR3 also
* saves copper's custom chip accesses. This fix stops programs
* that try to trick AR by using copper to update write-only
* custom registers.
*
* 30.04.2001 - added AR2 support
* 21.07.2001 - patch updated
* 29.07.2002 - added AR1 support
* 11.03.2003 - added AR1 breakpoint support, checksum support and fixes. (Mark Cox)
*
*/
/* AR2/3 'NORES' info.
* On ar2 there is a 'nores' command,
* on ar3, it is accessible using the mouse.
* This command will not work using the current infrastructure,
* so don't use it 8).
*/
/* AR1 Breakpoint info.
* 1.15 If a breakpoint occurred. Its address is stored at 9fe048.
* The 5 breakpoint entries each consisting of 6 bytes are stored at 9fe23e.
* Each entry contains the breakpoint long word followed by 2 bytes of the original contents of memory
* that is replaced by a trap instruction in mem.
* So the table finishes at 9fe25c.
*/
/* How AR1 is entered on reset:
* In the kickstart (1.3) there is the following code:
* I have marked the important lines:
*
* fc00e6 lea f00000,a1 ; address where AR1 rom is located.
* fc00ec cmpa.l a1,a0
* fc00ee beq fc00fe.s
* fc00f0 lea C(pc), a5
* fc00f4 cmpi.w #1111,(a1) ; The first word of the AR1 rom is set to 1111.
* fc00f8 bne fc00fe.s
* fc00fa jmp 2(a1) ; This is the entry point of the rom.
*/
/* Flag info:
* AR3:'ARON'. This is unset initially. It is set the first time you enter the AR via a freeze.
* It enables you to keep the keyboard buffer and such.
* If this flag is unset, the keyboard buffer is cleared, the breakpoints are deleted and ... */
/* AR3:'PRIN'. This flag is unset initially. It is set at some point and when you switch to the 2nd screen
* for the first time it displays all the familiar text. Then unsets 'PRIN'.
*/
/* Super IV:
*
* Possible "ROM" addresses ("ROM" is loaded from disk to Amiga memory)
* - 0xd00000
* - 0xc00000
* - 0x080000
*
* CIA-A: 0xb40000 (0x000, 0x100,...)
* CIA-B: 0xb40001 (0x001, 0x101,...)
* Custom: 0xe40000
*
* NOTE: emulation also supports 0xd00000 relocated "rom"-images
*/
/* X-Power 500:
*
* ROM: 0xe20000 (128k)
* RAM: 0xf20000 (64k)
* CIA-A: 0xf2fc00 (00,02,04,...)
* CIA-B: 0xf2fc01 (01,03,05,...)
* Custom: 0xf2fc00 (from 0x20->)
*/
/* Nordic Power:
*
* ROM: 0xf00000 (64k, mirrored at 0xf10000)
* RAM: 0xf40000 (32k, mirrored at 0xf48000 - 0xf5ffff)
* CIA-A: 0xf43c00 (00,02,04,...)
* CIA-B: 0xf43c01 (01,03,05,...)
* Custom: 0xf43c00 (from 0x20->)
* addresses 0 to 1023: 0xf40000 (weird feature..)
*/
/* X-Power and Nordic Power ROM scrambling
*
* Data lines are swapped.
* Address lines are XOR'd (0x817F) and swapped.
*
* Even (middle) ROM
*
* Data: 0-3,1-6,2-0,3-4,4-7,5-5,6-1,7-2
* Addr: 0-7,1-1,2-2,3-11,4-12,5-0,6-13,7-14,8-8,9-3,10-5,11-6,12-4,13-10,14-9,15-15
*
* Odd (corner) ROM
*
* Data: 0-2,1-3,2-4,3-5,4-6,5-7,6-0,7-1
* Addr: 0-3,1-6,2-5,3-7,4-9,5-12,6-14,7-13,8-8,9-11,10-10,11-1,12-0,13-4,14-2,15-15
*
*/
#include "sysconfig.h"
#include "sysdeps.h"
#include "options.h"
#include "uae.h"
#include "memory.h"
#include "rommgr.h"
#include "custom.h"
#include "newcpu.h"
#include "zfile.h"
#include "ar.h"
#include "savestate.h"
#include "crc32.h"
#include "akiko.h"
#include "xwin.h"
#include "gfxboard.h"
#define DEBUG
#ifdef DEBUG
#define write_log_debug write_log
#else
#define write_log_debug
#endif
static const TCHAR *cart_memnames[] = { NULL, _T("hrtmon"), _T("arhrtmon"), _T("superiv") };
// Action Replay 2/3
// $400001.B read values
#define ARMODE_FREEZE 0 /* 'freeze' button has been pressed. */
#define ARMODE_READ_BFE001 1 /* BFE001 read = freeze */
#define ARMODE_WRITE_BFD100 2 /* BFD100 write = freeze */
#define ARMODE_SOFTRESET 2
#define ARMODE_RESET 3 /* reset state */
// $400001.B written values
#define ARMODE_ACTIVATE_BFE001 2
#define ARMODE_ACTIVATE_BFD100 1
#define ARMODE_ACTIVE_NONE 0
#define CART_AR 0
#define CART_HRTMON 1
#define CART_AR1200 2
#define CART_SUPER4 3
uae_u8 ar_custom[2*256];
uae_u8 ar_ciaa[16], ar_ciab[16];
static int hrtmon_ciadiv = 256;
int hrtmon_flag = ACTION_REPLAY_INACTIVE;
static int cart_type;
static int ar_mapped, ar_hidden;
static uae_u8 *hrtmemory = 0, *hrtmemory2 = 0, *hrtmemory3 = 0;
static uae_u8 *armemory_rom = 0, *armemory_ram = 0;
static uae_u32 hrtmem_mask, hrtmem2_mask, hrtmem3_mask;
static uae_u8 *hrtmon_custom, *hrtmon_ciaa, *hrtmon_ciab, *hrtmon_zeropage;
uae_u32 hrtmem_start, hrtmem2_start, hrtmem3_start, hrtmem_size, hrtmem2_size, hrtmem2_size2, hrtmem3_size;
uae_u32 hrtmem_end, hrtmem2_end;
static int hrtmem_rom;
static int triggered_once;
static bool action_replay_hardreset;
static void hrtmon_unmap_banks (void);
void check_prefs_changed_carts (int in_memory_reset);
static int stored_picasso_on = -1;
static void cartridge_enter(void)
{
stored_picasso_on = gfxboard_set(0, false) ? 1 : 0;
}
static void cartridge_exit (void)
{
if (stored_picasso_on > 0)
gfxboard_set(0, true);
stored_picasso_on = -1;
}
static uae_u32 REGPARAM2 hrtmem3_bget (uaecptr addr)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
return hrtmemory3[addr];
}
static uae_u32 REGPARAM2 hrtmem3_wget (uaecptr addr)
{
return (hrtmem3_bget (addr) << 8) | hrtmem3_bget (addr + 1);
}
static uae_u32 REGPARAM2 hrtmem3_lget (uaecptr addr)
{
return (hrtmem3_wget (addr) << 16) | hrtmem3_wget (addr + 2);
}
static void REGPARAM2 hrtmem3_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
m = (uae_u32 *)(hrtmemory3 + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 hrtmem3_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
m = (uae_u16 *)(hrtmemory3 + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 hrtmem3_bput (uaecptr addr, uae_u32 b)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
hrtmemory3[addr] = b;
}
static int REGPARAM2 hrtmem3_check (uaecptr addr, uae_u32 size)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
return (addr + size) <= hrtmem3_size;
}
static uae_u8 *REGPARAM2 hrtmem3_xlate (uaecptr addr)
{
addr -= hrtmem3_start & hrtmem3_mask;
addr &= hrtmem3_mask;
return hrtmemory3 + addr;
}
static uae_u32 REGPARAM2 hrtmem2_bget (uaecptr addr)
{
if (addr == 0xb8007c && cart_type == CART_SUPER4) {
static int cnt = 60;
cnt--;
if (cnt == 0)
uae_reset(0, 0);
}
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
return hrtmemory2[addr];
}
static uae_u32 REGPARAM2 hrtmem2_wget (uaecptr addr)
{
return (hrtmem2_bget (addr) << 8) | hrtmem2_bget (addr + 1);
}
static uae_u32 REGPARAM2 hrtmem2_lget (uaecptr addr)
{
return (hrtmem2_wget (addr) << 16) | hrtmem2_wget (addr + 2);
}
static void REGPARAM2 hrtmem2_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
m = (uae_u32 *)(hrtmemory2 + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 hrtmem2_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
m = (uae_u16 *)(hrtmemory2 + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 hrtmem2_bput (uaecptr addr, uae_u32 b)
{
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
hrtmemory2[addr] = b;
}
static int REGPARAM2 hrtmem2_check (uaecptr addr, uae_u32 size)
{
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
return (addr + size) <= hrtmem2_size;
}
static uae_u8 *REGPARAM2 hrtmem2_xlate (uaecptr addr)
{
addr -= hrtmem2_start & hrtmem2_mask;
addr &= hrtmem2_mask;
return hrtmemory2 + addr;
}
static uae_u32 REGPARAM2 hrtmem_lget (uaecptr addr)
{
uae_u32 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
m = (uae_u32 *)(hrtmemory + addr);
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 hrtmem_wget (uaecptr addr)
{
uae_u16 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
m = (uae_u16 *)(hrtmemory + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 hrtmem_bget (uaecptr addr)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
return hrtmemory[addr];
}
static void REGPARAM2 hrtmem_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
if (cart_type == CART_AR1200 && addr < 0x80000)
return;
if (hrtmem_rom)
return;
m = (uae_u32 *)(hrtmemory + addr);
do_put_mem_long (m, l);
}
static void REGPARAM2 hrtmem_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
if (cart_type == CART_AR1200 && addr < 0x80000)
return;
if (hrtmem_rom)
return;
m = (uae_u16 *)(hrtmemory + addr);
do_put_mem_word (m, (uae_u16)w);
}
static void REGPARAM2 hrtmem_bput (uaecptr addr, uae_u32 b)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
if (cart_type == CART_AR1200 && addr < 0x80000)
return;
if (hrtmem_rom)
return;
hrtmemory[addr] = b;
}
static int REGPARAM2 hrtmem_check (uaecptr addr, uae_u32 size)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
return (addr + size) <= hrtmem_size;
}
static uae_u8 *REGPARAM2 hrtmem_xlate (uaecptr addr)
{
addr -= hrtmem_start & hrtmem_mask;
addr &= hrtmem_mask;
return hrtmemory + addr;
}
static addrbank hrtmem_bank = {
hrtmem_lget, hrtmem_wget, hrtmem_bget,
hrtmem_lput, hrtmem_wput, hrtmem_bput,
hrtmem_xlate, hrtmem_check, NULL, NULL, _T("Cartridge Bank"),
hrtmem_lget, hrtmem_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
static addrbank hrtmem2_bank = {
hrtmem2_lget, hrtmem2_wget, hrtmem2_bget,
hrtmem2_lput, hrtmem2_wput, hrtmem2_bput,
hrtmem2_xlate, hrtmem2_check, NULL, NULL, _T("Cartridge Bank 2"),
hrtmem2_lget, hrtmem2_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
static addrbank hrtmem3_bank = {
hrtmem3_lget, hrtmem3_wget, hrtmem3_bget,
hrtmem3_lput, hrtmem3_wput, hrtmem3_bput,
hrtmem3_xlate, hrtmem3_check, NULL, NULL, _T("Cartridge Bank 3"),
hrtmem3_lget, hrtmem3_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
static void copyfromamiga (uae_u8 *dst, uaecptr src, int len)
{
while (len--) {
*dst++ = get_byte (src);
src++;
}
}
static void copytoamiga (uaecptr dst, uae_u8 *src, int len)
{
while (len--) {
put_byte (dst, *src++);
dst++;
}
}
int action_replay_flag = ACTION_REPLAY_INACTIVE;
static int ar_state1 = -1, ar_state2 = -1, ar_hide;
static int ar_rom_file_size;
/* Use this for relocating AR? */
static int ar_rom_location;
/*static*/ int armodel;
static uae_u8 artemp[4]; /* Space to store the 'real' level 7 interrupt */
static uae_u8 armode_read, armode_write;
static uae_u32 arrom_start, arrom_size, arrom_mask;
static uae_u32 arram_start, arram_size, arram_mask;
static int ar_wait_pop = 0; /* bool used by AR1 when waiting for the program counter to exit it's ram. */
uaecptr wait_for_pc = 0; /* The program counter that we wait for. */
/* returns true if the Program counter is currently in the AR rom. */
int is_ar_pc_in_rom (void)
{
uaecptr pc = m68k_getpc () & 0xFFFFFF;
return pc >= arrom_start && pc < arrom_start+arrom_size;
}
/* returns true if the Program counter is currently in the AR RAM. */
int is_ar_pc_in_ram (void)
{
uaecptr pc = m68k_getpc () & 0xFFFFFF;
return pc >= arram_start && pc < arram_start+arram_size;
}
/* flag writing == 1 for writing memory, 0 for reading from memory. */
STATIC_INLINE int ar3a (uaecptr addr, uae_u8 b, int writing)
{
/* if (addr < 8) //|| writing ) */
/* { */
/* if (writing) */
/* write_log_debug("ARSTATUS armode:%d, Writing %d to address %p, PC=%p\n", armode, b, addr, m68k_getpc ()); */
/* else */
/* write_log_debug("ARSTATUS armode:%d, Reading %d from address %p, PC=%p\n", armode, armemory_rom[addr], addr, m68k_getpc ()); */
/* } */
if (armodel == 1) /* With AR1. It is always a read. Actually, it is a strobe on exit of the AR.
* but, it is also read during the checksum routine. */
{
if (addr < 2) {
if (is_ar_pc_in_rom()) {
if (ar_wait_pop) {
action_replay_flag = ACTION_REPLAY_WAIT_PC;
/* write_log_debug ("SP %p\n", m68k_areg (regs, 7)); */
/* write_log_debug ("SP+2 %p\n", m68k_areg (regs, 7) + 2); */
/* write_log_debug ("(SP+2) %p\n", longget (m68k_areg (regs, 7) + 2)); */
ar_wait_pop = 0;
/* We get (SP+2) here, as the first word on the stack is the status register. */
/* We want the following long, which is the return program counter. */
wait_for_pc = get_long(m68k_areg (regs, 7) + 2); /* Get (SP+2) */
set_special (SPCFLAG_ACTION_REPLAY);
uaecptr pc = m68k_getpc ();
/* write_log_debug ("Action Replay marked as ACTION_REPLAY_WAIT_PC, PC=%p\n",pc);*/
}
else
{
uaecptr pc = m68k_getpc ();
/* write_log_debug ("Action Replay marked as IDLE, PC=%p\n",pc);*/
action_replay_flag = ACTION_REPLAY_IDLE;
}
}
}
/* This probably violates the hide_banks thing except ar1 doesn't use that yet .*/
return armemory_rom[addr];
}
#ifdef ACTION_REPLAY_HIDE_CARTRIDGE
if (addr >= 8)
return armemory_rom[addr];
if (action_replay_flag == 0)
return 0;
#endif
if (!writing) {
//write_log(_T("READ %x\n"), addr);
if (addr == 1 || addr == 3) { /* This is necessary because we don't update rom location 0 every time we change armode */
//write_log(_T("ARMODE READ %02x %08X\n"), armode_read, M68K_GETPC);
return armode_read | (regs.irc & ~3);
} else if (addr < 4) {
return (addr & 1) ? regs.irc : regs.irc >> 8;
}
return armemory_rom[addr];
} else {
//write_log(_T("WRITE %x\n"), addr);
if (addr == 1) {
armode_write = b;
armode_read = 0;
//write_log(_T("ARMODE WRITE %02x %08X\n"), b, M68K_GETPC);
set_special (SPCFLAG_ACTION_REPLAY);
action_replay_flag = ACTION_REPLAY_HIDE;
} else if (addr == 6) {
copytoamiga (regs.vbr + 0x7c, artemp, 4);
}
}
return 0;
}
static void action_replay_chipwrite (void);
void REGPARAM2 chipmem_lput_actionreplay1 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
}
void REGPARAM2 chipmem_wput_actionreplay1 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (addr == 0x60 && !is_ar_pc_in_rom())
action_replay_chipwrite ();
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 chipmem_bput_actionreplay1 (uaecptr addr, uae_u32 b)
{
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
if (addr >= 0x60 && addr <= 0x63 && !is_ar_pc_in_rom())
action_replay_chipwrite();
chipmem_bank.baseaddr[addr] = b;
}
void REGPARAM2 chipmem_lput_actionreplay23 (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u32 *)(chipmem_bank.baseaddr + addr);
do_put_mem_long (m, l);
if (action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
}
void REGPARAM2 chipmem_wput_actionreplay23 (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
addr -= chipmem_start_addr & chipmem_bank.mask;
addr &= chipmem_bank.mask;
m = (uae_u16 *)(chipmem_bank.baseaddr + addr);
do_put_mem_word (m, w);
if (action_replay_flag == ACTION_REPLAY_WAITRESET)
action_replay_chipwrite();
}
static uae_u32 REGPARAM3 arram_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arram_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arram_bget (uaecptr) REGPARAM;
static void REGPARAM3 arram_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arram_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arram_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 arram_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 arram_xlate (uaecptr addr) REGPARAM;
static uae_u32 REGPARAM3 arrom_lget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arrom_wget (uaecptr) REGPARAM;
static uae_u32 REGPARAM3 arrom_bget (uaecptr) REGPARAM;
static void REGPARAM3 arrom_lput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arrom_wput (uaecptr, uae_u32) REGPARAM;
static void REGPARAM3 arrom_bput (uaecptr, uae_u32) REGPARAM;
static int REGPARAM3 arrom_check (uaecptr addr, uae_u32 size) REGPARAM;
static uae_u8 *REGPARAM3 arrom_xlate (uaecptr addr) REGPARAM;
static void action_replay_unmap_banks (void);
static uae_u32 action_replay_calculate_checksum(void);
static uae_u8* get_checksum_location(void);
static void disable_rom_test(void);
static uae_u32 ar_null(int size)
{
if (size == 4)
return dummy_bank.lget(0);
if (size == 2)
return dummy_bank.wget(0);
return dummy_bank.bget(0);
}
static uae_u32 REGPARAM2 arram_lget (uaecptr addr)
{
uae_u32 *m;
if (ar_hidden)
return ar_null(4);
addr -= arram_start;
addr &= arram_mask;
m = (uae_u32 *)(armemory_ram + addr);
if (strncmp ("T8", (char*)m, 2) == 0)
write_log_debug (_T("Reading T8 from addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("LAME", (char*)m, 4) == 0)
write_log_debug (_T("Reading LAME from addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("RES1", (char*)m, 4) == 0)
write_log_debug (_T("Reading RES1 from addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("ARON", (char*)m, 4) == 0)
write_log_debug (_T("Reading ARON from addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("KILL", (char*)m, 4) == 0)
write_log_debug (_T("Reading KILL from addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("BRON", (char*)m, 4) == 0)
write_log_debug (_T("Reading BRON from addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("PRIN", (char*)m, 4) == 0)
write_log_debug (_T("Reading PRIN from addr %08x PC=%08x\n"), addr, m68k_getpc ());
return do_get_mem_long (m);
}
static uae_u32 REGPARAM2 arram_wget (uaecptr addr)
{
uae_u16 *m;
if (ar_hidden)
return ar_null(4);
addr -= arram_start;
addr &= arram_mask;
m = (uae_u16 *)(armemory_ram + addr);
return do_get_mem_word (m);
}
static uae_u32 REGPARAM2 arram_bget (uaecptr addr)
{
if (ar_hidden)
return ar_null(4);
addr -= arram_start;
addr &= arram_mask;
return armemory_ram[addr];
}
void REGPARAM2 arram_lput (uaecptr addr, uae_u32 l)
{
uae_u32 *m;
if (ar_hidden)
return;
addr -= arram_start;
addr &= arram_mask;
m = (uae_u32 *)(armemory_ram + addr);
if (strncmp ("T8", (char*)m, 2) == 0)
write_log_debug (_T("Writing T8 to addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("LAME", (char*)m, 4) == 0)
write_log_debug (_T("Writing LAME to addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("RES1", (char*)m, 4) == 0)
write_log_debug (_T("Writing RES1 to addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("ARON", (char*)m, 4) == 0)
write_log_debug (_T("Writing ARON to addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("KILL", (char*)m, 4) == 0)
write_log_debug (_T("Writing KILL to addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("BRON", (char*)m, 4) == 0)
write_log_debug (_T("Writing BRON to addr %08x PC=%08x\n"), addr, m68k_getpc ());
if (strncmp ("PRIN", (char*)m, 4) == 0)
write_log_debug (_T("Writing PRIN to addr %08x PC=%08x\n"), addr, m68k_getpc ());
do_put_mem_long (m, l);
}
void REGPARAM2 arram_wput (uaecptr addr, uae_u32 w)
{
uae_u16 *m;
if (ar_hidden)
return;
addr -= arram_start;
addr &= arram_mask;
m = (uae_u16 *)(armemory_ram + addr);
do_put_mem_word (m, w);
}
void REGPARAM2 arram_bput (uaecptr addr, uae_u32 b)
{
if (ar_hidden)
return;
addr -= arram_start;
addr &= arram_mask;
armemory_ram[addr] = b;
}
static int REGPARAM2 arram_check (uaecptr addr, uae_u32 size)
{
addr -= arram_start;
addr &= arram_mask;
return (addr + size) <= arram_size;
}
static uae_u8 *REGPARAM2 arram_xlate (uaecptr addr)
{
addr -= arram_start;
addr &= arram_mask;
return armemory_ram + addr;
}
static uae_u32 REGPARAM2 arrom_lget (uaecptr addr)
{
if (ar_hidden)
return ar_null(4);
addr -= arrom_start;
addr &= arrom_mask;
return (ar3a (addr, 0, 0) << 24) | (ar3a (addr + 1, 0, 0) << 16) | (ar3a (addr + 2, 0, 0) << 8) | ar3a (addr + 3, 0, 0);
}
static uae_u32 REGPARAM2 arrom_wget (uaecptr addr)
{
if (ar_hidden)
return ar_null(2);
addr -= arrom_start;
addr &= arrom_mask;
return (ar3a (addr, 0, 0) << 8) | ar3a (addr + 1, 0, 0);
}
static uae_u32 REGPARAM2 arrom_bget (uaecptr addr)
{
if (ar_hidden)
return ar_null(1);
addr -= arrom_start;
addr &= arrom_mask;
return ar3a (addr, 0, 0);
}
static void REGPARAM2 arrom_lput (uaecptr addr, uae_u32 l)
{
if (ar_hidden)
return;
addr -= arrom_start;
addr &= arrom_mask;
ar3a (addr + 0,(uae_u8)(l >> 24), 1);
ar3a (addr + 1,(uae_u8)(l >> 16), 1);
ar3a (addr + 2,(uae_u8)(l >> 8), 1);
ar3a (addr + 3,(uae_u8)(l >> 0), 1);
}
static void REGPARAM2 arrom_wput (uaecptr addr, uae_u32 w)
{
if (ar_hidden)
return;
addr -= arrom_start;
addr &= arrom_mask;
ar3a (addr + 0,(uae_u8)(w >> 8), 1);
ar3a (addr + 1,(uae_u8)(w >> 0), 1);
}
static void REGPARAM2 arrom_bput (uaecptr addr, uae_u32 b)
{
if (ar_hidden)
return;
addr -= arrom_start;
addr &= arrom_mask;
ar3a (addr, b, 1);
}
static int REGPARAM2 arrom_check (uaecptr addr, uae_u32 size)
{
addr -= arrom_start;
addr &= arrom_mask;
return (addr + size) <= arrom_size;
}
static uae_u8 *REGPARAM2 arrom_xlate (uaecptr addr)
{
addr -= arrom_start;
addr &= arrom_mask;
return armemory_rom + addr;
}
static addrbank arrom_bank = {
arrom_lget, arrom_wget, arrom_bget,
arrom_lput, arrom_wput, arrom_bput,
arrom_xlate, arrom_check, NULL, NULL, _T("Action Replay ROM"),
arrom_lget, arrom_wget,
ABFLAG_ROM, S_READ, S_WRITE
};
static addrbank arram_bank = {
arram_lget, arram_wget, arram_bget,
arram_lput, arram_wput, arram_bput,
arram_xlate, arram_check, NULL, NULL, _T("Action Replay RAM"),
arram_lget, arram_wget,
ABFLAG_RAM, S_READ, S_WRITE
};
static void action_replay_map_banks (void)
{
if(!armemory_rom)
return;
ar_hidden = false;
if (ar_mapped > 0)
return;
ar_mapped = 1;
map_banks (&arrom_bank, arrom_start >> 16, arrom_size >> 16, 0);
map_banks (&arram_bank, arram_start >> 16, arram_size >> 16, 0);
}
static void action_replay_unmap_banks (void)
{
if(!armemory_rom)
return;
if (armodel == 1) {
action_replay_map_banks ();
return;
}
ar_hidden = true;
if (ar_mapped == 0)
return;
ar_mapped = 0;
map_banks (&dummy_bank, arrom_start >> 16 , arrom_size >> 16, 0);
map_banks (&dummy_bank, arram_start >> 16 , arram_size >> 16, 0);
}
static void hide_cart (int hide)
{
ar_hide = hide;
#ifdef ACTION_REPLAY_HIDE_CARTRIDGE
if(hide) {
action_replay_unmap_banks ();
} else {
action_replay_map_banks ();
}
#endif
}
/* Cartridge activates itself by overlaying its rom
* over chip-ram and then issuing IRQ 7
*
* I just copy IRQ vector 7 from ROM to chip RAM
* instead of fully emulating cartridge's behaviour.
*/
static void action_replay_go (void)
{
cartridge_enter();
hide_cart (0);
memcpy (armemory_ram + 0xf000, ar_custom, 2 * 256);
action_replay_flag = ACTION_REPLAY_ACTIVE;
set_special (SPCFLAG_ACTION_REPLAY);
copyfromamiga (artemp, regs.vbr + 0x7c, 4);
copytoamiga (regs.vbr + 0x7c, armemory_rom + 0x7c, 4);
NMI ();
}
static void action_replay_go1 (int irq)
{
cartridge_enter();
hide_cart (0);
action_replay_flag = ACTION_REPLAY_ACTIVE;
memcpy (armemory_ram + 0xf000, ar_custom, 2 * 256);
NMI ();
}
typedef struct {
uae_u8 dummy[4+4];
uae_u8 jmps[3*4];
uae_u32 mon_size;
uae_u8 col0h, col0l, col1h, col1l;
uae_u8 right;
uae_u8 keyboard;
uae_u8 key;
uae_u8 ide;
uae_u8 a1200;
uae_u8 aga;
uae_u8 insert;
uae_u8 delay;
uae_u8 lview;
uae_u8 cd32;
uae_u8 screenmode;
uae_u8 novbr;
uae_u8 entered;
uae_u8 hexmode;
uae_u16 error_sr;
uae_u32 error_pc;
uae_u16 error_status;
uae_u8 newid[6];
uae_u16 mon_version;
uae_u16 mon_revision;
uae_u32 whd_base;
uae_u16 whd_version;
uae_u16 whd_revision;
uae_u32 max_chip;
uae_u32 whd_expstrt;
uae_u32 whd_expstop;
} HRTCFG;
static void hrtmon_go (void)
{
uaecptr old;
int i;
triggered_once = 1;
cartridge_enter();
hrtmon_flag = ACTION_REPLAY_ACTIVE;
set_special (SPCFLAG_ACTION_REPLAY);