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Jul 29, 2024 - Verilog
cocotb
Here are 49 public repositories matching this topic...
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Jul 29, 2024 - Verilog
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
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Jul 25, 2024 - SystemVerilog
Python packages providing a library for Verification Stimulus and Coverage
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Jul 25, 2024 - Python
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
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Jul 17, 2024 - SystemVerilog
Design & Verification of IP Cores and ICs, Artificial Intelligence
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Jul 9, 2024 - VHDL
Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board
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May 6, 2024 - Verilog
Branch Predictor Optimization for BlackParrot
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Mar 24, 2024 - HTML
Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
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Mar 15, 2024 - Python
Cosimulation for the Rapid Open Hardware Development (ROHD) framework with other simulators
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Feb 26, 2024 - Dart
Library of hardware accelerators for popular cryptographic hash functions in SystemVerilog
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Feb 9, 2024 - Python
Functional Coverage and Constrained Randomization Extensions for Cocotb
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Nov 15, 2023 - Python
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