Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
-
Updated
Sep 20, 2024 - Python
Cross-platform CLI and Python drivers for AIO liquid coolers and other devices
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototypes are available on different FPGA boards. Described in our preprint: https://arxiv.org/pdf/2211.05838.pdf
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
Behavioral architecture of a read/write cycle controller for a DRAM chip.
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
Improving DRAM Reliability and Performance On-Demand via Coherent Replication [ISCA 2021]
A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.
A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. This data and its analysis are described in the 2022 paper by Patel et al.: https://arxiv.org/abs/2204.10378
This is a repository for the ParaMonte library examples. For more information, visit:
Design of a simulator of a multi-core processor and DRAM for a subset of MIPS instruction set architecture in C++. Course Project of COL216: Computer Architecture taught in Second Sem, 2020-21 at IIT Delhi
HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/210…
MCMC toolbox for Matlab
Add a description, image, and links to the dram topic page so that developers can more easily learn about it.
To associate your repository with the dram topic, visit your repo's landing page and select "manage topics."