VeeR EL2 Core
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Updated
Oct 17, 2024 - SystemVerilog
VeeR EL2 Core
Yet another attempt at bazel rules for fusesoc. This one relies on a hermetic installation of fusesoc and edalize, and not a containerized build. See https://github.com/filmil/bazel_rules_fusesoc for that other bit.
NES Controller Interface written in Verilog-2005
A quick SPI BFM to assist in SPI device testing and development
A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.
VeeR EH1 core
A simple SHA-256 implementation in VHDL and Verilog, simulated using a basic UVM testbench.
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