ip-core
Here are 23 public repositories matching this topic...
Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher
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Feb 27, 2024 - Verilog
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
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Jan 26, 2024 - Python
FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器,可实现视频压缩。
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Jan 26, 2024 - Verilog
Microarquitecturas y Softcores - CESE - FIUBA
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Dec 13, 2023 - Verilog
Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
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Mar 6, 2023 - C
Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
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Mar 6, 2023 - TeX
Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC
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Mar 6, 2023 - TeX
A Python-based IP Core Management Infrastructure.
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Apr 29, 2021 - Python
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
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Jul 29, 2020 - C++
Synthesizable SystemVerilog IP-Core of the I2S Receiver
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Jun 7, 2020 - SystemVerilog
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
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Jun 7, 2020 - SystemVerilog
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
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Jun 6, 2020 - SystemVerilog
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
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Jan 5, 2019 - VHDL
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
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Oct 24, 2017 - Verilog
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
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Jul 12, 2017 - VHDL
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