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bob.txt
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------- FILE std_kernel.asm LEVEL 1 PASS 2
1 10000 processor 6502
------- FILE vcs.h LEVEL 2 PASS 2
0 10000 ???? include "vcs.h"
1 10000 ???? ; VCS.H
2 10000 ???? ; Version 1.06, 06/SEP/2020
3 10000 ????
4 10000 ???? 00 6a VERSION_VCS = 106
5 10000 ????
6 10000 ???? ; THIS IS *THE* "STANDARD" VCS.H
7 10000 ???? ; THIS FILE IS EXPLICITLY SUPPORTED AS A DASM-PREFERRED COMPANION FILE
8 10000 ???? ; The latest version can be found at https://dasm-assembler.github.io/
9 10000 ???? ;
10 10000 ???? ; This file defines hardware registers and memory mapping for the
11 10000 ???? ; Atari 2600. It is distributed as a companion machine-specific support package
12 10000 ???? ; for the DASM compiler. Updates to this file, DASM, and associated tools are
13 10000 ???? ; available at at https://dasm-assembler.github.io/
14 10000 ???? ;
15 10000 ???? ; Many thanks to the people who have contributed. If you find an issue with the
16 10000 ???? ; contents, or would like ot add something, please report as an issue at...
17 10000 ???? ; https://github.com/dasm-assembler/dasm/issues
18 10000 ????
19 10000 ???? ;
20 10000 ???? ; Latest Revisions...
21 10000 ???? ; 1.06 05/SEP/2020 Modified header/license and links to new versions
22 10000 ???? ; 1.05 13/NOV/2003 - Correction to 1.04 - now functions as requested by MR.
23 10000 ???? ; - Added VERSION_VCS equate (which will reflect 100x version #)
24 10000 ???? ; This will allow conditional code to verify VCS.H being
25 10000 ???? ; used for code assembly.
26 10000 ???? ; 1.04 12/NOV/2003 Added TIA_BASE_WRITE_ADDRESS and TIA_BASE_READ_ADDRESS for
27 10000 ???? ; convenient disassembly/reassembly compatibility for hardware
28 10000 ???? ; mirrored reading/writing differences. This is more a
29 10000 ???? ; readability issue, and binary compatibility with disassembled
30 10000 ???? ; and reassembled sources. Per Manuel Rotschkar's suggestion.
31 10000 ???? ; 1.03 12/MAY/2003 Added SEG segment at end of file to fix old-code compatibility
32 10000 ???? ; which was broken by the use of segments in this file, as
33 10000 ???? ; reported by Manuel Polik on [stella] 11/MAY/2003
34 10000 ???? ; 1.02 22/MAR/2003 Added TIMINT($285)
35 10000 ???? ; 1.01 Constant offset added to allow use for 3F-style bankswitching
36 10000 ???? ; - define TIA_BASE_ADDRESS as $40 for Tigervision carts, otherwise
37 10000 ???? ; it is safe to leave it undefined, and the base address will
38 10000 ???? ; be set to 0. Thanks to Eckhard Stolberg for the suggestion.
39 10000 ???? ; Note, may use -DLABEL=EXPRESSION to define TIA_BASE_ADDRESS
40 10000 ???? ; - register definitions are now generated through assignment
41 10000 ???? ; in uninitialised segments. This allows a changeable base
42 10000 ???? ; address architecture.
43 10000 ???? ; 1.0 22/MAR/2003 Initial release
44 10000 ????
45 10000 ????
46 10000 ???? ;-------------------------------------------------------------------------------
47 10000 ????
48 10000 ???? ; TIA_BASE_ADDRESS
49 10000 ???? ; The TIA_BASE_ADDRESS defines the base address of access to TIA registers.
50 10000 ???? ; Normally 0, the base address should (externally, before including this file)
51 10000 ???? ; be set to $40 when creating 3F-bankswitched (and other?) cartridges.
52 10000 ???? ; The reason is that this bankswitching scheme treats any access to locations
53 10000 ???? ; < $40 as a bankswitch.
54 10000 ????
55 10000 ???? - IFNCONST TIA_BASE_ADDRESS
56 10000 ???? -TIA_BASE_ADDRESS = 0
57 10000 ???? ENDIF
58 10000 ????
59 10000 ???? ; Note: The address may be defined on the command-line using the -D switch, eg:
60 10000 ???? ; dasm.exe code.asm -DTIA_BASE_ADDRESS=$40 -f3 -v5 -ocode.bin
61 10000 ???? ; *OR* by declaring the label before including this file, eg:
62 10000 ???? ; TIA_BASE_ADDRESS = $40
63 10000 ???? ; include "vcs.h"
64 10000 ????
65 10000 ???? ; Alternate read/write address capability - allows for some disassembly compatibility
66 10000 ???? ; usage ; to allow reassembly to binary perfect copies). This is essentially catering
67 10000 ???? ; for the mirrored ROM hardware registers.
68 10000 ????
69 10000 ???? ; Usage: As per above, define the TIA_BASE_READ_ADDRESS and/or TIA_BASE_WRITE_ADDRESS
70 10000 ???? ; using the -D command-line switch, as required. If the addresses are not defined,
71 10000 ???? ; they defaut to the TIA_BASE_ADDRESS.
72 10000 ????
73 10000 ???? - IFNCONST TIA_BASE_READ_ADDRESS
74 10000 ???? -TIA_BASE_READ_ADDRESS = TIA_BASE_ADDRESS
75 10000 ???? ENDIF
76 10000 ????
77 10000 ???? - IFNCONST TIA_BASE_WRITE_ADDRESS
78 10000 ???? -TIA_BASE_WRITE_ADDRESS = TIA_BASE_ADDRESS
79 10000 ???? ENDIF
80 10000 ????
81 10000 ???? ;-------------------------------------------------------------------------------
82 10000 ????
83 U002d ???? SEG.U TIA_REGISTERS_WRITE
84 U0000 ORG TIA_BASE_WRITE_ADDRESS
85 U0000
86 U0000 ; DO NOT CHANGE THE RELATIVE ORDERING OF REGISTERS!
87 U0000
88 U0000 00 VSYNC ds 1 ; $00 0000 00x0 Vertical Sync Set-Clear
89 U0001 00 VBLANK ds 1 ; $01 xx00 00x0 Vertical Blank Set-Clear
90 U0002 00 WSYNC ds 1 ; $02 ---- ---- Wait for Horizontal Blank
91 U0003 00 RSYNC ds 1 ; $03 ---- ---- Reset Horizontal Sync Counter
92 U0004 00 NUSIZ0 ds 1 ; $04 00xx 0xxx Number-Size player/missle 0
93 U0005 00 NUSIZ1 ds 1 ; $05 00xx 0xxx Number-Size player/missle 1
94 U0006 00 COLUP0 ds 1 ; $06 xxxx xxx0 Color-Luminance Player 0
95 U0007 00 COLUP1 ds 1 ; $07 xxxx xxx0 Color-Luminance Player 1
96 U0008 00 COLUPF ds 1 ; $08 xxxx xxx0 Color-Luminance Playfield
97 U0009 00 COLUBK ds 1 ; $09 xxxx xxx0 Color-Luminance Background
98 U000a 00 CTRLPF ds 1 ; $0A 00xx 0xxx Control Playfield, Ball, Collisions
99 U000b 00 REFP0 ds 1 ; $0B 0000 x000 Reflection Player 0
100 U000c 00 REFP1 ds 1 ; $0C 0000 x000 Reflection Player 1
101 U000d 00 PF0 ds 1 ; $0D xxxx 0000 Playfield Register Byte 0
102 U000e 00 PF1 ds 1 ; $0E xxxx xxxx Playfield Register Byte 1
103 U000f 00 PF2 ds 1 ; $0F xxxx xxxx Playfield Register Byte 2
104 U0010 00 RESP0 ds 1 ; $10 ---- ---- Reset Player 0
105 U0011 00 RESP1 ds 1 ; $11 ---- ---- Reset Player 1
106 U0012 00 RESM0 ds 1 ; $12 ---- ---- Reset Missle 0
107 U0013 00 RESM1 ds 1 ; $13 ---- ---- Reset Missle 1
108 U0014 00 RESBL ds 1 ; $14 ---- ---- Reset Ball
109 U0015 00 AUDC0 ds 1 ; $15 0000 xxxx Audio Control 0
110 U0016 00 AUDC1 ds 1 ; $16 0000 xxxx Audio Control 1
111 U0017 00 AUDF0 ds 1 ; $17 000x xxxx Audio Frequency 0
112 U0018 00 AUDF1 ds 1 ; $18 000x xxxx Audio Frequency 1
113 U0019 00 AUDV0 ds 1 ; $19 0000 xxxx Audio Volume 0
114 U001a 00 AUDV1 ds 1 ; $1A 0000 xxxx Audio Volume 1
115 U001b 00 GRP0 ds 1 ; $1B xxxx xxxx Graphics Register Player 0
116 U001c 00 GRP1 ds 1 ; $1C xxxx xxxx Graphics Register Player 1
117 U001d 00 ENAM0 ds 1 ; $1D 0000 00x0 Graphics Enable Missle 0
118 U001e 00 ENAM1 ds 1 ; $1E 0000 00x0 Graphics Enable Missle 1
119 U001f 00 ENABL ds 1 ; $1F 0000 00x0 Graphics Enable Ball
120 U0020 00 HMP0 ds 1 ; $20 xxxx 0000 Horizontal Motion Player 0
121 U0021 00 HMP1 ds 1 ; $21 xxxx 0000 Horizontal Motion Player 1
122 U0022 00 HMM0 ds 1 ; $22 xxxx 0000 Horizontal Motion Missle 0
123 U0023 00 HMM1 ds 1 ; $23 xxxx 0000 Horizontal Motion Missle 1
124 U0024 00 HMBL ds 1 ; $24 xxxx 0000 Horizontal Motion Ball
125 U0025 00 VDELP0 ds 1 ; $25 0000 000x Vertical Delay Player 0
126 U0026 00 VDELP1 ds 1 ; $26 0000 000x Vertical Delay Player 1
127 U0027 00 VDELBL ds 1 ; $27 0000 000x Vertical Delay Ball
128 U0028 00 RESMP0 ds 1 ; $28 0000 00x0 Reset Missle 0 to Player 0
129 U0029 00 RESMP1 ds 1 ; $29 0000 00x0 Reset Missle 1 to Player 1
130 U002a 00 HMOVE ds 1 ; $2A ---- ---- Apply Horizontal Motion
131 U002b 00 HMCLR ds 1 ; $2B ---- ---- Clear Horizontal Move Registers
132 U002c 00 CXCLR ds 1 ; $2C ---- ---- Clear Collision Latches
133 U002d
134 U002d ;-------------------------------------------------------------------------------
135 U002d
136 U000e ???? SEG.U TIA_REGISTERS_READ
137 U0000 ORG TIA_BASE_READ_ADDRESS
138 U0000
139 U0000 ; bit 7 bit 6
140 U0000 00 CXM0P ds 1 ; $00 xx00 0000 Read Collision M0-P1 M0-P0
141 U0001 00 CXM1P ds 1 ; $01 xx00 0000 M1-P0 M1-P1
142 U0002 00 CXP0FB ds 1 ; $02 xx00 0000 P0-PF P0-BL
143 U0003 00 CXP1FB ds 1 ; $03 xx00 0000 P1-PF P1-BL
144 U0004 00 CXM0FB ds 1 ; $04 xx00 0000 M0-PF M0-BL
145 U0005 00 CXM1FB ds 1 ; $05 xx00 0000 M1-PF M1-BL
146 U0006 00 CXBLPF ds 1 ; $06 x000 0000 BL-PF -----
147 U0007 00 CXPPMM ds 1 ; $07 xx00 0000 P0-P1 M0-M1
148 U0008 00 INPT0 ds 1 ; $08 x000 0000 Read Pot Port 0
149 U0009 00 INPT1 ds 1 ; $09 x000 0000 Read Pot Port 1
150 U000a 00 INPT2 ds 1 ; $0A x000 0000 Read Pot Port 2
151 U000b 00 INPT3 ds 1 ; $0B x000 0000 Read Pot Port 3
152 U000c 00 INPT4 ds 1 ; $0C x000 0000 Read Input (Trigger) 0
153 U000d 00 INPT5 ds 1 ; $0D x000 0000 Read Input (Trigger) 1
154 U000e
155 U000e ;-------------------------------------------------------------------------------
156 U000e
157 U0298 ???? SEG.U RIOT
158 U0280 ORG $280
159 U0280
160 U0280 ; RIOT MEMORY MAP
161 U0280
162 U0280 00 SWCHA ds 1 ; $280 Port A data register for joysticks:
163 U0281 ; Bits 4-7 for player 1. Bits 0-3 for player 2.
164 U0281
165 U0281 00 SWACNT ds 1 ; $281 Port A data direction register (DDR)
166 U0282 00 SWCHB ds 1 ; $282 Port B data (console switches)
167 U0283 00 SWBCNT ds 1 ; $283 Port B DDR
168 U0284 00 INTIM ds 1 ; $284 Timer output
169 U0285
170 U0285 00 TIMINT ds 1 ; $285
171 U0286
172 U0286 ; Unused/undefined registers ($285-$294)
173 U0286
174 U0286 00 ds 1 ; $286
175 U0287 00 ds 1 ; $287
176 U0288 00 ds 1 ; $288
177 U0289 00 ds 1 ; $289
178 U028a 00 ds 1 ; $28A
179 U028b 00 ds 1 ; $28B
180 U028c 00 ds 1 ; $28C
181 U028d 00 ds 1 ; $28D
182 U028e 00 ds 1 ; $28E
183 U028f 00 ds 1 ; $28F
184 U0290 00 ds 1 ; $290
185 U0291 00 ds 1 ; $291
186 U0292 00 ds 1 ; $292
187 U0293 00 ds 1 ; $293
188 U0294
189 U0294 00 TIM1T ds 1 ; $294 set 1 clock interval
190 U0295 00 TIM8T ds 1 ; $295 set 8 clock interval
191 U0296 00 TIM64T ds 1 ; $296 set 64 clock interval
192 U0297 00 T1024T ds 1 ; $297 set 1024 clock interval
193 U0298
194 U0298 ;-------------------------------------------------------------------------------
195 U0298 ; The following required for back-compatibility with code which does not use
196 U0298 ; segments.
197 U0298
198 10000 ???? SEG
199 10000 ????
200 10000 ???? ; EOF
------- FILE std_kernel.asm
------- FILE macro.h LEVEL 2 PASS 2
0 10000 ???? include "macro.h"
1 10000 ???? ; MACRO.H
2 10000 ???? ; Version 1.09, 05/SEP/2020
3 10000 ????
4 10000 ???? 00 6d VERSION_MACRO = 109
5 10000 ????
6 10000 ???? ;
7 10000 ???? ; THIS FILE IS EXPLICITLY SUPPORTED AS A DASM-PREFERRED COMPANION FILE
8 10000 ???? ; The latest version can be found at https://dasm-assembler.github.io/
9 10000 ???? ;
10 10000 ???? ; This file defines DASM macros useful for development for the Atari 2600.
11 10000 ???? ; It is distributed as a companion machine-specific support package
12 10000 ???? ; for the DASM compiler.
13 10000 ???? ;
14 10000 ???? ; Many thanks to the people who have contributed. If you find an issue with the
15 10000 ???? ; contents, or would like ot add something, please report as an issue at...
16 10000 ???? ; https://github.com/dasm-assembler/dasm/issues
17 10000 ????
18 10000 ????
19 10000 ???? ; Latest Revisions...
20 10000 ???? ; 1.09 05/SEP/2020 - updated license/links
21 10000 ????
22 10000 ???? ; 1.08 13/JUL/2020 - added use of LXA to CLEAN_START
23 10000 ???? ; 1.07 19/JAN/2020 - correction to comment VERTICAL_SYNC
24 10000 ???? ; 1.06 03/SEP/2004 - nice revision of VERTICAL_SYNC (Edwin Blink)
25 10000 ???? ; 1.05 14/NOV/2003 - Added VERSION_MACRO equate (which will reflect 100x version #)
26 10000 ???? ; This will allow conditional code to verify MACRO.H being
27 10000 ???? ; used for code assembly.
28 10000 ???? ; 1.04 13/NOV/2003 - SET_POINTER macro added (16-bit address load)
29 10000 ???? ;
30 10000 ???? ; 1.03 23/JUN/2003 - CLEAN_START macro added - clears TIA, RAM, registers
31 10000 ???? ;
32 10000 ???? ; 1.02 14/JUN/2003 - VERTICAL_SYNC macro added
33 10000 ???? ; (standardised macro for vertical synch code)
34 10000 ???? ; 1.01 22/MAR/2003 - SLEEP macro added.
35 10000 ???? ; - NO_ILLEGAL_OPCODES switch implemented
36 10000 ???? ; 1.0 22/MAR/2003 Initial release
37 10000 ????
38 10000 ???? ; Note: These macros use illegal opcodes. To disable illegal opcode usage,
39 10000 ???? ; define the symbol NO_ILLEGAL_OPCODES (-DNO_ILLEGAL_OPCODES=1 on command-line).
40 10000 ???? ; If you do not allow illegal opcode usage, you must include this file
41 10000 ???? ; *after* including VCS.H (as the non-illegal opcodes access hardware
42 10000 ???? ; registers and require them to be defined first).
43 10000 ????
44 10000 ???? ; Available macros...
45 10000 ???? ; SLEEP n - sleep for n cycles
46 10000 ???? ; VERTICAL_SYNC - correct 3 scanline vertical synch code
47 10000 ???? ; CLEAN_START - set machine to known state on startup
48 10000 ???? ; SET_POINTER - load a 16-bit absolute to a 16-bit variable
49 10000 ????
50 10000 ???? ;-------------------------------------------------------------------------------
51 10000 ???? ; SLEEP duration
52 10000 ???? ; Original author: Thomas Jentzsch
53 10000 ???? ; Inserts code which takes the specified number of cycles to execute. This is
54 10000 ???? ; useful for code where precise timing is required.
55 10000 ???? ; ILLEGAL-OPCODE VERSION DOES NOT AFFECT FLAGS OR REGISTERS.
56 10000 ???? ; LEGAL OPCODE VERSION MAY AFFECT FLAGS
57 10000 ???? ; Uses illegal opcode (DASM 2.20.01 onwards).
58 10000 ????
59 10000 ???? MAC sleep
60 10000 ???? .CYCLES SET {1}
61 10000 ????
62 10000 ???? IF .CYCLES < 2
63 10000 ???? ECHO "MACRO ERROR: 'SLEEP': Duration must be > 1"
64 10000 ???? ERR
65 10000 ???? ENDIF
66 10000 ????
67 10000 ???? IF .CYCLES & 1
68 10000 ???? IFNCONST NO_ILLEGAL_OPCODES
69 10000 ???? nop 0
70 10000 ???? ELSE
71 10000 ???? bit VSYNC
72 10000 ???? ENDIF
73 10000 ???? .CYCLES SET .CYCLES - 3
74 10000 ???? ENDIF
75 10000 ????
76 10000 ???? REPEAT .CYCLES / 2
77 10000 ???? nop
78 10000 ???? REPEND
79 10000 ???? ENDM ;usage: SLEEP n (n>1)
80 10000 ????
81 10000 ???? ;-------------------------------------------------------------------------------
82 10000 ???? ; VERTICAL_SYNC
83 10000 ???? ; revised version by Edwin Blink -- saves bytes!
84 10000 ???? ; Inserts the code required for a proper 3 scanline vertical sync sequence
85 10000 ???? ; Note: Alters the accumulator
86 10000 ????
87 10000 ???? ; OUT: A = 0
88 10000 ????
89 10000 ???? MAC vertical_sync
90 10000 ???? lda #%1110 ; each '1' bits generate a VSYNC ON line (bits 1..3)
91 10000 ???? .VSLP1 sta WSYNC ; 1st '0' bit resets Vsync, 2nd '0' bit exit loop
92 10000 ???? sta VSYNC
93 10000 ???? lsr
94 10000 ???? bne .VSLP1 ; branch until VYSNC has been reset
95 10000 ???? ENDM
96 10000 ????
97 10000 ???? ;-------------------------------------------------------------------------------
98 10000 ???? ; CLEAN_START
99 10000 ???? ; Original author: Andrew Davie
100 10000 ???? ; Standardised start-up code, clears stack, all TIA registers and RAM to 0
101 10000 ???? ; Sets stack pointer to $FF, and all registers to 0
102 10000 ???? ; Sets decimal mode off, sets interrupt flag (kind of un-necessary)
103 10000 ???? ; Use as very first section of code on boot (ie: at reset)
104 10000 ???? ; Code written to minimise total ROM usage - uses weird 6502 knowledge :)
105 10000 ????
106 10000 ???? MAC clean_start
107 10000 ???? sei
108 10000 ???? cld
109 10000 ????
110 10000 ???? IFNCONST NO_ILLEGAL_OPCODES
111 10000 ???? lxa #0
112 10000 ???? ELSE
113 10000 ???? ldx #0
114 10000 ???? txa
115 10000 ???? ENDIF
116 10000 ???? tay
117 10000 ???? .CLEAR_STACK dex
118 10000 ???? txs
119 10000 ???? pha
120 10000 ???? bne .CLEAR_STACK ; SP=$FF, X = A = Y = 0
121 10000 ????
122 10000 ???? ENDM
123 10000 ????
124 10000 ???? ;-------------------------------------------------------
125 10000 ???? ; SET_POINTER
126 10000 ???? ; Original author: Manuel Rotschkar
127 10000 ???? ;
128 10000 ???? ; Sets a 2 byte RAM pointer to an absolute address.
129 10000 ???? ;
130 10000 ???? ; Usage: SET_POINTER pointer, address
131 10000 ???? ; Example: SET_POINTER SpritePTR, SpriteData
132 10000 ???? ;
133 10000 ???? ; Note: Alters the accumulator, NZ flags
134 10000 ???? ; IN 1: 2 byte RAM location reserved for pointer
135 10000 ???? ; IN 2: absolute address
136 10000 ????
137 10000 ???? MAC set_pointer
138 10000 ???? .POINTER SET {1}
139 10000 ???? .ADDRESS SET {2}
140 10000 ????
141 10000 ???? LDA #<.ADDRESS ; Get Lowbyte of Address
142 10000 ???? STA .POINTER ; Store in pointer
143 10000 ???? LDA #>.ADDRESS ; Get Hibyte of Address
144 10000 ???? STA .POINTER+1 ; Store in pointer+1
145 10000 ????
146 10000 ???? ENDM
147 10000 ????
148 10000 ???? ;-------------------------------------------------------
149 10000 ???? ; BOUNDARY byte#
150 10000 ???? ; Original author: Denis Debro (borrowed from Bob Smith / Thomas)
151 10000 ???? ;
152 10000 ???? ; Push data to a certain position inside a page and keep count of how
153 10000 ???? ; many free bytes the programmer will have.
154 10000 ???? ;
155 10000 ???? ; eg: BOUNDARY 5 ; position at byte #5 in page
156 10000 ????
157 10000 ???? .FREE_BYTES SET 0
158 10000 ???? MAC boundary
159 10000 ???? REPEAT 256
160 10000 ???? IF <. % {1} = 0
161 10000 ???? MEXIT
162 10000 ???? ELSE
163 10000 ???? .FREE_BYTES SET .FREE_BYTES + 1
164 10000 ???? .byte $00
165 10000 ???? ENDIF
166 10000 ???? REPEND
167 10000 ???? ENDM
168 10000 ????
169 10000 ????
170 10000 ???? ; EOF
------- FILE std_kernel.asm
------- FILE timers.h LEVEL 2 PASS 2
0 10000 ???? include "timers.h"
1 10000 ????
2 10000 ???? processor 6502
------- FILE vcs.h LEVEL 3 PASS 2
0 10000 ???? include "vcs.h"
1 10000 ???? ; VCS.H
2 10000 ???? ; Version 1.06, 06/SEP/2020
3 10000 ????
4 10000 ???? 00 6a VERSION_VCS = 106
5 10000 ????
6 10000 ???? ; THIS IS *THE* "STANDARD" VCS.H
7 10000 ???? ; THIS FILE IS EXPLICITLY SUPPORTED AS A DASM-PREFERRED COMPANION FILE
8 10000 ???? ; The latest version can be found at https://dasm-assembler.github.io/
9 10000 ???? ;
10 10000 ???? ; This file defines hardware registers and memory mapping for the
11 10000 ???? ; Atari 2600. It is distributed as a companion machine-specific support package
12 10000 ???? ; for the DASM compiler. Updates to this file, DASM, and associated tools are
13 10000 ???? ; available at at https://dasm-assembler.github.io/
14 10000 ???? ;
15 10000 ???? ; Many thanks to the people who have contributed. If you find an issue with the
16 10000 ???? ; contents, or would like ot add something, please report as an issue at...
17 10000 ???? ; https://github.com/dasm-assembler/dasm/issues
18 10000 ????
19 10000 ???? ;
20 10000 ???? ; Latest Revisions...
21 10000 ???? ; 1.06 05/SEP/2020 Modified header/license and links to new versions
22 10000 ???? ; 1.05 13/NOV/2003 - Correction to 1.04 - now functions as requested by MR.
23 10000 ???? ; - Added VERSION_VCS equate (which will reflect 100x version #)
24 10000 ???? ; This will allow conditional code to verify VCS.H being
25 10000 ???? ; used for code assembly.
26 10000 ???? ; 1.04 12/NOV/2003 Added TIA_BASE_WRITE_ADDRESS and TIA_BASE_READ_ADDRESS for
27 10000 ???? ; convenient disassembly/reassembly compatibility for hardware
28 10000 ???? ; mirrored reading/writing differences. This is more a
29 10000 ???? ; readability issue, and binary compatibility with disassembled
30 10000 ???? ; and reassembled sources. Per Manuel Rotschkar's suggestion.
31 10000 ???? ; 1.03 12/MAY/2003 Added SEG segment at end of file to fix old-code compatibility
32 10000 ???? ; which was broken by the use of segments in this file, as
33 10000 ???? ; reported by Manuel Polik on [stella] 11/MAY/2003
34 10000 ???? ; 1.02 22/MAR/2003 Added TIMINT($285)
35 10000 ???? ; 1.01 Constant offset added to allow use for 3F-style bankswitching
36 10000 ???? ; - define TIA_BASE_ADDRESS as $40 for Tigervision carts, otherwise
37 10000 ???? ; it is safe to leave it undefined, and the base address will
38 10000 ???? ; be set to 0. Thanks to Eckhard Stolberg for the suggestion.
39 10000 ???? ; Note, may use -DLABEL=EXPRESSION to define TIA_BASE_ADDRESS
40 10000 ???? ; - register definitions are now generated through assignment
41 10000 ???? ; in uninitialised segments. This allows a changeable base
42 10000 ???? ; address architecture.
43 10000 ???? ; 1.0 22/MAR/2003 Initial release
44 10000 ????
45 10000 ????
46 10000 ???? ;-------------------------------------------------------------------------------
47 10000 ????
48 10000 ???? ; TIA_BASE_ADDRESS
49 10000 ???? ; The TIA_BASE_ADDRESS defines the base address of access to TIA registers.
50 10000 ???? ; Normally 0, the base address should (externally, before including this file)
51 10000 ???? ; be set to $40 when creating 3F-bankswitched (and other?) cartridges.
52 10000 ???? ; The reason is that this bankswitching scheme treats any access to locations
53 10000 ???? ; < $40 as a bankswitch.
54 10000 ????
55 10000 ???? - IFNCONST TIA_BASE_ADDRESS
56 10000 ???? -TIA_BASE_ADDRESS = 0
57 10000 ???? ENDIF
58 10000 ????
59 10000 ???? ; Note: The address may be defined on the command-line using the -D switch, eg:
60 10000 ???? ; dasm.exe code.asm -DTIA_BASE_ADDRESS=$40 -f3 -v5 -ocode.bin
61 10000 ???? ; *OR* by declaring the label before including this file, eg:
62 10000 ???? ; TIA_BASE_ADDRESS = $40
63 10000 ???? ; include "vcs.h"
64 10000 ????
65 10000 ???? ; Alternate read/write address capability - allows for some disassembly compatibility
66 10000 ???? ; usage ; to allow reassembly to binary perfect copies). This is essentially catering
67 10000 ???? ; for the mirrored ROM hardware registers.
68 10000 ????
69 10000 ???? ; Usage: As per above, define the TIA_BASE_READ_ADDRESS and/or TIA_BASE_WRITE_ADDRESS
70 10000 ???? ; using the -D command-line switch, as required. If the addresses are not defined,
71 10000 ???? ; they defaut to the TIA_BASE_ADDRESS.
72 10000 ????
73 10000 ???? - IFNCONST TIA_BASE_READ_ADDRESS
74 10000 ???? -TIA_BASE_READ_ADDRESS = TIA_BASE_ADDRESS
75 10000 ???? ENDIF
76 10000 ????
77 10000 ???? - IFNCONST TIA_BASE_WRITE_ADDRESS
78 10000 ???? -TIA_BASE_WRITE_ADDRESS = TIA_BASE_ADDRESS
79 10000 ???? ENDIF
80 10000 ????
81 10000 ???? ;-------------------------------------------------------------------------------
82 10000 ????
83 U002d SEG.U TIA_REGISTERS_WRITE
84 U0000 ORG TIA_BASE_WRITE_ADDRESS
85 U0000
86 U0000 ; DO NOT CHANGE THE RELATIVE ORDERING OF REGISTERS!
87 U0000
88 U0000 00 VSYNC ds 1 ; $00 0000 00x0 Vertical Sync Set-Clear
89 U0001 00 VBLANK ds 1 ; $01 xx00 00x0 Vertical Blank Set-Clear
90 U0002 00 WSYNC ds 1 ; $02 ---- ---- Wait for Horizontal Blank
91 U0003 00 RSYNC ds 1 ; $03 ---- ---- Reset Horizontal Sync Counter
92 U0004 00 NUSIZ0 ds 1 ; $04 00xx 0xxx Number-Size player/missle 0
93 U0005 00 NUSIZ1 ds 1 ; $05 00xx 0xxx Number-Size player/missle 1
94 U0006 00 COLUP0 ds 1 ; $06 xxxx xxx0 Color-Luminance Player 0
95 U0007 00 COLUP1 ds 1 ; $07 xxxx xxx0 Color-Luminance Player 1
96 U0008 00 COLUPF ds 1 ; $08 xxxx xxx0 Color-Luminance Playfield
97 U0009 00 COLUBK ds 1 ; $09 xxxx xxx0 Color-Luminance Background
98 U000a 00 CTRLPF ds 1 ; $0A 00xx 0xxx Control Playfield, Ball, Collisions
99 U000b 00 REFP0 ds 1 ; $0B 0000 x000 Reflection Player 0
100 U000c 00 REFP1 ds 1 ; $0C 0000 x000 Reflection Player 1
101 U000d 00 PF0 ds 1 ; $0D xxxx 0000 Playfield Register Byte 0
102 U000e 00 PF1 ds 1 ; $0E xxxx xxxx Playfield Register Byte 1
103 U000f 00 PF2 ds 1 ; $0F xxxx xxxx Playfield Register Byte 2
104 U0010 00 RESP0 ds 1 ; $10 ---- ---- Reset Player 0
105 U0011 00 RESP1 ds 1 ; $11 ---- ---- Reset Player 1
106 U0012 00 RESM0 ds 1 ; $12 ---- ---- Reset Missle 0
107 U0013 00 RESM1 ds 1 ; $13 ---- ---- Reset Missle 1
108 U0014 00 RESBL ds 1 ; $14 ---- ---- Reset Ball
109 U0015 00 AUDC0 ds 1 ; $15 0000 xxxx Audio Control 0
110 U0016 00 AUDC1 ds 1 ; $16 0000 xxxx Audio Control 1
111 U0017 00 AUDF0 ds 1 ; $17 000x xxxx Audio Frequency 0
112 U0018 00 AUDF1 ds 1 ; $18 000x xxxx Audio Frequency 1
113 U0019 00 AUDV0 ds 1 ; $19 0000 xxxx Audio Volume 0
114 U001a 00 AUDV1 ds 1 ; $1A 0000 xxxx Audio Volume 1
115 U001b 00 GRP0 ds 1 ; $1B xxxx xxxx Graphics Register Player 0
116 U001c 00 GRP1 ds 1 ; $1C xxxx xxxx Graphics Register Player 1
117 U001d 00 ENAM0 ds 1 ; $1D 0000 00x0 Graphics Enable Missle 0
118 U001e 00 ENAM1 ds 1 ; $1E 0000 00x0 Graphics Enable Missle 1
119 U001f 00 ENABL ds 1 ; $1F 0000 00x0 Graphics Enable Ball
120 U0020 00 HMP0 ds 1 ; $20 xxxx 0000 Horizontal Motion Player 0
121 U0021 00 HMP1 ds 1 ; $21 xxxx 0000 Horizontal Motion Player 1
122 U0022 00 HMM0 ds 1 ; $22 xxxx 0000 Horizontal Motion Missle 0
123 U0023 00 HMM1 ds 1 ; $23 xxxx 0000 Horizontal Motion Missle 1
124 U0024 00 HMBL ds 1 ; $24 xxxx 0000 Horizontal Motion Ball
125 U0025 00 VDELP0 ds 1 ; $25 0000 000x Vertical Delay Player 0
126 U0026 00 VDELP1 ds 1 ; $26 0000 000x Vertical Delay Player 1
127 U0027 00 VDELBL ds 1 ; $27 0000 000x Vertical Delay Ball
128 U0028 00 RESMP0 ds 1 ; $28 0000 00x0 Reset Missle 0 to Player 0
129 U0029 00 RESMP1 ds 1 ; $29 0000 00x0 Reset Missle 1 to Player 1
130 U002a 00 HMOVE ds 1 ; $2A ---- ---- Apply Horizontal Motion
131 U002b 00 HMCLR ds 1 ; $2B ---- ---- Clear Horizontal Move Registers
132 U002c 00 CXCLR ds 1 ; $2C ---- ---- Clear Collision Latches
133 U002d
134 U002d ;-------------------------------------------------------------------------------
135 U002d
136 U000e SEG.U TIA_REGISTERS_READ
137 U0000 ORG TIA_BASE_READ_ADDRESS
138 U0000
139 U0000 ; bit 7 bit 6
140 U0000 00 CXM0P ds 1 ; $00 xx00 0000 Read Collision M0-P1 M0-P0
141 U0001 00 CXM1P ds 1 ; $01 xx00 0000 M1-P0 M1-P1
142 U0002 00 CXP0FB ds 1 ; $02 xx00 0000 P0-PF P0-BL
143 U0003 00 CXP1FB ds 1 ; $03 xx00 0000 P1-PF P1-BL
144 U0004 00 CXM0FB ds 1 ; $04 xx00 0000 M0-PF M0-BL
145 U0005 00 CXM1FB ds 1 ; $05 xx00 0000 M1-PF M1-BL
146 U0006 00 CXBLPF ds 1 ; $06 x000 0000 BL-PF -----
147 U0007 00 CXPPMM ds 1 ; $07 xx00 0000 P0-P1 M0-M1
148 U0008 00 INPT0 ds 1 ; $08 x000 0000 Read Pot Port 0
149 U0009 00 INPT1 ds 1 ; $09 x000 0000 Read Pot Port 1
150 U000a 00 INPT2 ds 1 ; $0A x000 0000 Read Pot Port 2
151 U000b 00 INPT3 ds 1 ; $0B x000 0000 Read Pot Port 3
152 U000c 00 INPT4 ds 1 ; $0C x000 0000 Read Input (Trigger) 0
153 U000d 00 INPT5 ds 1 ; $0D x000 0000 Read Input (Trigger) 1
154 U000e
155 U000e ;-------------------------------------------------------------------------------
156 U000e
157 U0298 SEG.U RIOT
158 U0280 ORG $280
159 U0280
160 U0280 ; RIOT MEMORY MAP
161 U0280
162 U0280 00 SWCHA ds 1 ; $280 Port A data register for joysticks:
163 U0281 ; Bits 4-7 for player 1. Bits 0-3 for player 2.
164 U0281
165 U0281 00 SWACNT ds 1 ; $281 Port A data direction register (DDR)
166 U0282 00 SWCHB ds 1 ; $282 Port B data (console switches)
167 U0283 00 SWBCNT ds 1 ; $283 Port B DDR
168 U0284 00 INTIM ds 1 ; $284 Timer output
169 U0285
170 U0285 00 TIMINT ds 1 ; $285
171 U0286
172 U0286 ; Unused/undefined registers ($285-$294)
173 U0286
174 U0286 00 ds 1 ; $286
175 U0287 00 ds 1 ; $287
176 U0288 00 ds 1 ; $288
177 U0289 00 ds 1 ; $289
178 U028a 00 ds 1 ; $28A
179 U028b 00 ds 1 ; $28B
180 U028c 00 ds 1 ; $28C
181 U028d 00 ds 1 ; $28D
182 U028e 00 ds 1 ; $28E
183 U028f 00 ds 1 ; $28F
184 U0290 00 ds 1 ; $290
185 U0291 00 ds 1 ; $291
186 U0292 00 ds 1 ; $292
187 U0293 00 ds 1 ; $293
188 U0294
189 U0294 00 TIM1T ds 1 ; $294 set 1 clock interval
190 U0295 00 TIM8T ds 1 ; $295 set 8 clock interval
191 U0296 00 TIM64T ds 1 ; $296 set 64 clock interval
192 U0297 00 T1024T ds 1 ; $297 set 1024 clock interval
193 U0298
194 U0298 ;-------------------------------------------------------------------------------
195 U0298 ; The following required for back-compatibility with code which does not use
196 U0298 ; segments.
197 U0298
198 10000 ???? SEG
199 10000 ????
200 10000 ???? ; EOF
------- FILE timers.h
4 10000 ????
5 10000 ???? MAC timer_wait
6 10000 ???? .waitTimer
7 10000 ???? LDA INTIM
8 10000 ???? BNE .waitTimer
9 10000 ???? STA WSYNC
10 10000 ???? ENDM
11 10000 ????
12 10000 ???? MAC timer_vblank
13 10000 ???? lda #45
14 10000 ???? STA TIM64T
15 10000 ???? ENDM
16 10000 ????
17 10000 ???? MAC timer_frame
18 10000 ???? lda #231
19 10000 ???? STA TIM64T
20 10000 ???? ENDM
21 10000 ????
22 10000 ???? MAC timer_overscan
23 10000 ???? lda #40
24 10000 ???? STA TIM64T
25 10000 ???? ENDM
------- FILE std_kernel.asm
5 10000 ????
6 10000 ???? 00 0e WHITE = $0E
7 10000 ???? 00 c2 GREEN = $C2
8 10000 ???? 00 76 BLUE = $76
9 10000 ???? 00 1e YELLOW = $1E
10 10000 ????
11 U0089 ???? SEG.U vars
12 U0080 ORG $80 ; start of RAM
13 U0080
14 U0080 00 SCANLINE_N ds 1
15 U0081 00 PLAYER0_X ds 1
16 U0082 00 PLAYER0_Y ds 1
17 U0083
18 U0083 00 PLAYER0_X_PREV ds 1
19 U0084 00 PLAYER0_Y_PREV ds 1
20 U0085
21 U0085 00 PLAYER0_SLICE_EVEN ds 1 ; player slice even lines
22 U0086 00 PLAYER0_SLICE_ODD ds 1 ; player slice odd lines
23 U0087
24 U0087 00 BK_COLOR ds 1
25 U0088
26 U0088 00 TEMP ds 1
27 U0089
28 10000 ???? SEG
29 f000 ORG $F000
30 f000
31 f000 Reset
0 f000 CLEAN_START
1 f000 78 sei
2 f001 d8 cld
3 f002
4 f002 IFNCONST NO_ILLEGAL_OPCODES
5 f002 ab 00 lxa #0
6 f004 - ELSE
7 f004 - ldx #0
8 f004 - txa
9 f004 ENDIF
10 f004 a8 tay
11 f005 ca .CLEAR_STACK dex
12 f006 9a txs
13 f007 48 pha
14 f008 d0 fb bne .CLEAR_STACK
15 f00a
33 f00a
34 f00a a9 00 lda #0
35 f00c 85 81 sta PLAYER0_X
36 f00e a9 54 lda #84
37 f010 85 82 sta PLAYER0_Y
38 f012
39 f012 a9 c2 lda #GREEN
40 f014 85 87 sta BK_COLOR
41 f016 a9 fa lda #$FA
42 f018 85 06 sta COLUP0 ; color player 0
43 f01a a9 64 lda #100
44 f01c 85 85 sta PLAYER0_SLICE_EVEN ; next player 0 bitslice to draw
45 f01e a9 44 lda #$44
46 f020 85 86 sta PLAYER0_SLICE_ODD
47 f022
48 f022 a9 01 lda #1 ; set D0 CTRLPF for reflection
49 f024 85 0a sta CTRLPF
50 f026 StartOfFrame
51 f026 a9 02 lda #2
52 f028 85 01 sta VBLANK ; blank video signal
0 f02a VERTICAL_SYNC
1 f02a a9 0e lda #%1110
2 f02c 85 02 .VSLP1 sta WSYNC
3 f02e 85 00 sta VSYNC
4 f030 4a lsr
5 f031 d0 f9 bne .VSLP1
0 f033 TIMER_VBLANK ; init timer for VBLANK period
1 f033 a9 2d lda #45
2 f035 8d 96 02 STA TIM64T
55 f038 20 73 f0 JSR FramePre ; do any setup before the frame
0 f03b TIMER_WAIT
1 f03b .waitTimer
2 f03b ad 84 02 LDA INTIM
3 f03e d0 fb BNE .waitTimer
4 f040 85 02 STA WSYNC
57 f042
58 f042 a9 00 lda #0
59 f044 85 01 sta VBLANK ; unblank video signal
60 f046
61 f046
62 f046
0 f046 TIMER_FRAME ; init timer for the visible frame
1 f046 a9 e7 lda #231
2 f048 8d 96 02 STA TIM64T
64 f04b a9 00 lda #0
65 f04d 85 02 STA WSYNC
66 f04f ScanLine
67 f04f 20 b3 f0 JSR DoScanLineLoop
68 f052
69 f052 a2 1e ldx #YELLOW ; yellow for the block of lines not rendered. If visible FRAME_TIMER is too long
70 f054 86 09 stx COLUBK
71 f056
0 f056 TIMER_WAIT
1 f056 .waitTimer
2 f056 ad 84 02 LDA INTIM
3 f059 d0 fb BNE .waitTimer
4 f05b 85 02 STA WSYNC
73 f05d
74 f05d a9 02 lda #2
75 f05f 85 01 sta VBLANK ; blank video signal
76 f061
0 f061 TIMER_OVERSCAN ; init timer for overscan
1 f061 a9 28 lda #40
2 f063 8d 96 02 STA TIM64T
78 f066 20 0e f1 JSR FramePost
0 f069 TIMER_WAIT
1 f069 .waitTimer
2 f069 ad 84 02 LDA INTIM
3 f06c d0 fb BNE .waitTimer
4 f06e 85 02 STA WSYNC
80 f070
81 f070 4c 26 f0 JMP StartOfFrame
82 f073
83 f073
84 f073 FramePre
85 f073
86 f073 a9 0e lda #WHITE
87 f075 85 08 sta COLUPF ; set the playfield color
88 f077
89 f077 a6 82 ldx PLAYER0_Y
90 f079 86 84 stx PLAYER0_Y_PREV
91 f07b a9 20 lda #$20
92 f07d 2c 80 02 bit SWCHA
93 f080 d0 04 bne .testUp
94 f082 e8 inx
95 f083 4c 8e f0 jmp .storeY
96 f086 .testUp
97 f086 a9 10 lda #$10
98 f088 2c 80 02 bit SWCHA
99 f08b d0 01 bne .storeY
100 f08d ca dex
101 f08e .storeY
102 f08e 86 82 stx PLAYER0_Y
103 f090
104 f090 a6 81 ldx PLAYER0_X
105 f092 86 83 stx PLAYER0_X_PREV
106 f094 a9 80 lda #$80
107 f096 2c 80 02 bit SWCHA
108 f099 d0 04 bne .testLeft
109 f09b e8 inx
110 f09c 4c a7 f0 jmp .storeX
111 f09f .testLeft
112 f09f a9 40 lda #$40
113 f0a1 2c 80 02 bit SWCHA
114 f0a4 d0 01 bne .storeX
115 f0a6 ca dex
116 f0a7 .storeX
117 f0a7 86 81 stx PLAYER0_X
118 f0a9
119 f0a9 a5 81 lda PLAYER0_X
120 f0ab 20 00 ff jsr setHorizontalPos
121 f0ae 85 02 sta WSYNC ; wait for new scanline to fine tune position player 1
122 f0b0 85 2a sta HMOVE
123 f0b2 60 rts
124 f0b3
125 f0b3 ; scan line is in acc and y
126 f0b3 ; set playfield and sprites based on scanline
127 f0b3 ;
128 f0b3 DoScanLineLoop
129 f0b3 a9 00 lda #0
130 f0b5 85 80 sta SCANLINE_N
131 f0b7 a8 tay
132 f0b8 .continue
133 f0b8 85 02 STA WSYNC
134 f0ba a6 85 ldx PLAYER0_SLICE_EVEN
135 f0bc 86 1b stx GRP0
136 f0be a8 tay
137 f0bf 29 fc and #%11111100 ; divide by 4 (to repeat 4 lines) and mult by 4 (to index into bitmap)
138 f0c1 aa tax
139 f0c2 bd 12 ff lda Field0,x
140 f0c5 85 0d sta PF0
141 f0c7 bd 13 ff lda Field1,x
142 f0ca 85 0e sta PF1
143 f0cc bd 14 ff lda Field2,x
144 f0cf 85 0f sta PF2
145 f0d1
146 f0d1 ; must be done after the odd scanline
147 f0d1 85 02 sta WSYNC
148 f0d3 a6 86 ldx PLAYER0_SLICE_ODD
149 f0d5 86 1b stx GRP0
150 f0d7
151 f0d7 ; compute next player slice
152 f0d7 98 tya
153 f0d8 38 sec ; 2s complement so set carry
154 f0d9 e5 82 sbc PLAYER0_Y
155 f0db 30 12 bmi .clearPlayer
156 f0dd c9 08 cmp #8
157 f0df 10 0e bpl .clearPlayer
158 f0e1 aa tax
159 f0e2 bd d2 ff lda PlayerBitmap,x
160 f0e5 85 85 sta PLAYER0_SLICE_EVEN
161 f0e7 bd d3 ff lda PlayerBitmap+1,x
162 f0ea
163 f0ea 85 86 sta PLAYER0_SLICE_ODD
164 f0ec 4c f9 f0 jmp .increment
165 f0ef .clearPlayer
166 f0ef ea nop
167 f0f0 ea nop
168 f0f1 ea nop
169 f0f2 ea nop
170 f0f3 a9 00 lda #0
171 f0f5 85 85 sta PLAYER0_SLICE_EVEN
172 f0f7 85 86 sta PLAYER0_SLICE_ODD
173 f0f9 .increment
174 f0f9 e6 80 inc SCANLINE_N
175 f0fb e6 80 inc SCANLINE_N
176 f0fd a5 80 lda SCANLINE_N
177 f0ff c9 c0 cmp #192
178 f101 d0 b5 bne .continue
179 f103 ; clear playfield at end of line
180 f103 85 02 STA WSYNC
181 f105 a9 00 lda #0
182 f107 85 0d sta PF0
183 f109 85 0e sta PF1
184 f10b 85 0f sta PF2
185 f10d 60 rts
186 f10e
187 f10e
188 f10e ; if timing is correct this color is not seen because it should be called in non-visible overscan area
189 f10e
190 f10e FramePost
191 f10e 24 02 bit CXP0FB
192 f110 10 0f bpl .noCollision
193 f112 a9 76 lda #BLUE
194 f114 85 09 sta COLUBK
195 f116 a6 83 ldx PLAYER0_X_PREV
196 f118 86 81 stx PLAYER0_X
197 f11a a6 84 ldx PLAYER0_Y_PREV
198 f11c 86 82 stx PLAYER0_Y
199 f11e 4c 25 f1 jmp .clearCollision
200 f121 .noCollision
201 f121 a9 c2 lda #GREEN
202 f123 85 09 sta COLUBK
203 f125 .clearCollision
204 f125 a9 00 lda #0
205 f127 85 2c sta CXCLR
206 f129 85 0d sta PF0 ; clear
207 f12b 85 0e sta PF1 ; clear
208 f12d 85 0f sta PF2 ; clear
209 f12f
210 f12f 60 RTS
211 f130
212 ff00 org $FF00 ; *********************** GRAPHICS DATA
213 ff00 setHorizontalPos
214 ff00 85 02 sta WSYNC
215 ff02 38 sec
216 ff03 .DivideLoop
217 ff03 e9 0f sbc #15
218 ff05 b0 fc bcs .DivideLoop
219 ff07 49 07 eor #7
220 ff09 0a asl
221 ff0a 0a asl
222 ff0b 0a asl
223 ff0c 0a asl
224 ff0d 85 20 sta HMP0
225 ff0f 85 10 sta RESP0
226 ff11 60 rts
227 ff12
228 ff12 Playfield
229 ff12 f0 ff ff 00 .byte.b %11110000,%11111111,%11111111,$00 ; lower nibble ignored and upper reversed for 1st. 3rd reversed, 4th ignored
230 ff16 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
231 ff1a 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
232 ff1e 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
233 ff22 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
234 ff26 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
235 ff2a 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
236 ff2e 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
237 ff32 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
238 ff36 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
239 ff3a 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
240 ff3e 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
241 ff42 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
242 ff46 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
243 ff4a 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
244 ff4e 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
245 ff52 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
246 ff56 10 3c 00 00 .byte.b %00010000,%00111100,%00000000,$00
247 ff5a 10 24 00 00 .byte.b %00010000,%00100100,%00000000,$00
248 ff5e 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00 ; start gap
249 ff62 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00
250 ff66 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00
251 ff6a 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00
252 ff6e 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00
253 ff72 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00
254 ff76 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00
255 ff7a 00 24 00 00 .byte.b %00000000,%00100100,%00000000,$00 ; end gap
256 ff7e 10 24 00 00 .byte.b %00010000,%00100100,%00000000,$00
257 ff82 10 3c 00 00 .byte.b %00010000,%00111100,%00000000,$00
258 ff86 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
259 ff8a 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
260 ff8e 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
261 ff92 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
262 ff96 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
263 ff9a 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
264 ff9e 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
265 ffa2 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
266 ffa6 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
267 ffaa 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
268 ffae 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
269 ffb2 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
270 ffb6 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
271 ffba 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
272 ffbe 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
273 ffc2 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
274 ffc6 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
275 ffca 10 00 00 00 .byte.b %00010000,%00000000,%00000000,$00
276 ffce f0 ff ff 00 .byte.b %11110000,%11111111,%11111111,$00
277 ffd2
278 ffd2 ff 12 Field0 = Playfield
279 ffd2 ff 13 Field1 = Playfield+1
280 ffd2 ff 14 Field2 = Playfield+2
281 ffd2
282 ffd2 PlayerBitmap
283 ffd2 81 .byte.b %10000001
284 ffd3 42 .byte.b %01000010
285 ffd4 24 .byte.b %00100100
286 ffd5 98 .byte.b %10011000
287 ffd6 e4 .byte.b %11100100
288 ffd7 24 .byte.b %00100100
289 ffd8 18 .byte.b %00011000
290 ffd9 3c .byte.b %00111100
291 ffda
292 fffa ORG $FFFA
293 fffa 00 f0 .word.w Reset ; NMI
294 fffc 00 f0 .word.w Reset ; RESET
295 fffe 00 f0 .word.w Reset ; IRQ
296 10000 END