BUILD.md

Thu Apr 7 15:12:58 CEST 2022, 75e206e

Build instructions

From brand new Ubuntu machine to autogenerated ppu_top.v verilog ppu core.

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1. Install Python

   1.0. update apt registry

    sudo apt update
   

   1.1. install prerequisites of Python and pyenv

    sudo apt-get install -y build-essential libssl-dev zlib1g-dev libbz2-dev libreadline-dev libsqlite3-dev wget curl llvm libncurses5-dev libncursesw5-dev xz-utils tk-dev libffi-dev liblzma-dev python-openssl git unzip
   

   either use pyenv (recommended) or apt

   • pyenv way

     1.1.1 clone and install pyenv

       git clone https://github.com/pyenv/pyenv.git ~/.pyenv
     
       echo 'export PYENV_ROOT="$HOME/.pyenv"' >> ~/.bashrc
       echo 'export PATH="$PYENV_ROOT/bin:$PATH"' >> ~/.bashrc
       echo -e 'if command -v pyenv 1>/dev/null 2>&1; then\n eval "$(pyenv init --path)"\nfi' >> ~/.bashrc
     
       exec $SHELL
       source .bashrc
     

     1.1.2. install Python3.10.0 via pyenv

       pyenv install 3.10.0
       pyenv global 3.10.0
     

   • apt way

     1.2.1. install Python via the apt package manager

       sudo apt install -y python3.10
     

     1.2.2. symlink that version of Python into the user-installed binaries folder

       sudo ln -sf /usr/bin/python3.10 /usr/local/bin/python
     

     1.2.3. create alias for the pip Python package manager

       echo "alias pip='python -m pip'" >> ~/.bashrc
     

     1.2.4. refresh .bashrc so that pip becomes known to the shell session.

       source ~/.bashrc
     

2. install maturin via the Python package manager pip

    pip install maturin
   

3. install the Rust toolchain

    curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh
    source $HOME/.cargo/env
   

4. generate ssh keys to access for github?

    ssh-keygen
    cat ~/.ssh/id_rsa.pub
    # and copy it into your github's settings
   

5. download and install the hardposit library

    git clone git@github.com:urbanij/hardposit.git
    cd hardposit/bindings/py-hardposit
    make
   

6. install the SystemVerilog tools:

   7.1. compiler/simulator icarus verilog

   • either via the apt package manager (linux):

       sudo apt install -y iverilog
     

   • or via the brew package manager (linux/macOS):

       # install brew upfront if not installed
       /bin/bash -c "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/HEAD/install.sh)"
     
       brew install icarus-verilog
     

   • or from source for the most up to date version:

       git clone git@github.com:steveicarus/iverilog.git
       cd iverilog
       sudo apt-get install -y gperf autoconf flex bison
       sh autoconf.sh
       ./configure
       make
       make check # optional
       sudo make install
     

   7.2. gtkwave waveform viewer

    sudo apt install -y gtkwave
   

   7.3. yosys synthesis tool (optional)

    sudo apt install -y yosys
   

7. optionally, download and install the [system]verilog slang code linter

    wget https://github.com/MikePopoloski/slang/releases/download/v0.9/slang-linux.tar.gz
    tar -xf slang-linux.tar.gz
    sudo cp slang/bin/slang /usr/local/bin/
   

8. download and install the systemverilog to verilog sv2v transpiler

    wget https://github.com/zachjs/sv2v/releases/download/v0.0.9/sv2v-Linux.zip
    unzip sv2v-Linux.zip
    sudo cp sv2v-Linux/sv2v /usr/local/bin/
   

9. setup the working directories

   mkdir RISCV-PPU
   cd RISCV-PPU
   

   10.1. clone the repos locally. Note: the ppu folder and the PACoGen folder must be in this relative position to each other in order for the comparison step¹ to work

   git clone git@bitbucket.org:riscv-ppu/ppu.git
   git clone git@bitbucket.org:riscv-ppu/pacogen.git PACoGen
   

   10.2. cd into ppu and export the required env variables

   cd ppu
   source .env
   

   10.3. checkout the pipeline branch, or checkout the exact commit I'm writing this file at:

   git checkout pipeline 
   # git checkout 75e206e
   

   10.4. run the script that generates the test vectors

   make gen-test-vectors
   

   10.5. generate ppu_top.v inside ./fpga/quartus/ppu_top.v and ./fpga/vivado/ppu_top.v and run the outdated simulations:

   make ppu WORD=64 F=32 N=8 ES=0
   

   10.6. run the up to date simulation where WORD ∈ {32, 64}, F ∈ {16, 32, 64}, N ∈ (3, 32], ES ∈ [0, N)

   make tb_pipelined WORD=64 F=32 N=16 ES=1
   

   10.7. open the waveforms

   gtkwave sim/waveforms/tb_ppu_pipelined_P16E1.vcd
   # gtkwave sim/waveforms/tb_ppu_pipelined_P16E1.gtkw # i.e. the pre-saved version of the corresponding vcd file w/ waves already in place
   

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¹ make div-against-pacogen_P16E1