From 066b42589d64c3f06867b450c3224c0a22480280 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 14 Jun 2024 07:51:47 -0400 Subject: [PATCH] Fix AUTOWIRE etc. range simplification with subtraction of negative number (#1879). * verilog-mode.el (verilog-simplify-range-expression): Fix AUTOWIRE etc. range simplification with subtraction of negative number (#1879). [HeChao] --- tests/autowire_merge_pm.v | 23 +++++++++++++++++++ tests_ok/autowire_merge_pm.v | 23 +++++++++++++++++++ verilog-mode.el | 44 ++++++++++++++++++++---------------- 3 files changed, 71 insertions(+), 19 deletions(-) create mode 100644 tests/autowire_merge_pm.v create mode 100644 tests_ok/autowire_merge_pm.v diff --git a/tests/autowire_merge_pm.v b/tests/autowire_merge_pm.v new file mode 100644 index 0000000..4abd238 --- /dev/null +++ b/tests/autowire_merge_pm.v @@ -0,0 +1,23 @@ +// issue #1879 + +module TOP + ( + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DW-1:0] SIG_NAMEA // From A of A.v + // End of automatics + /*AUTOINPUT*/ + ); + /*AUTOWIRE*/ + + A A(/*AUTOINST*/ + // Outputs + .SIG_NAMEA (SIG_NAMEA[DW-1+2:0])); + +endmodule + +module A + ( + output [DW-1+2:0] SIG_NAMEA + ); +endmodule diff --git a/tests_ok/autowire_merge_pm.v b/tests_ok/autowire_merge_pm.v new file mode 100644 index 0000000..03facac --- /dev/null +++ b/tests_ok/autowire_merge_pm.v @@ -0,0 +1,23 @@ +// issue #1879 + +module TOP + ( + /*AUTOOUTPUT*/ + // Beginning of automatic outputs (from unused autoinst outputs) + output [DW+1:0] SIG_NAMEA // From A of A.v + // End of automatics + /*AUTOINPUT*/ + ); + /*AUTOWIRE*/ + + A A(/*AUTOINST*/ + // Outputs + .SIG_NAMEA (SIG_NAMEA[DW-1+2:0])); + +endmodule + +module A + ( + output [DW-1+2:0] SIG_NAMEA + ); +endmodule diff --git a/verilog-mode.el b/verilog-mode.el index a7a028b..f4640d9 100644 --- a/verilog-mode.el +++ b/verilog-mode.el @@ -11441,6 +11441,7 @@ This repairs those mis-inserted by an AUTOARG." ;; Prefix regexp needs beginning of match, or some symbol of ;; lesser or equal precedence. We assume the [:]'s exist in expr. ;; Ditto the end. + ;;(message "sre: out=%s" out) (while (string-match (concat "\\([[({:*/<>+-]\\)" ; - must be last "(\\<\\([0-9A-Za-z_]+\\))" @@ -11486,19 +11487,23 @@ This repairs those mis-inserted by an AUTOARG." out) (let ((pre (match-string 1 out)) (lhs (string-to-number (match-string 2 out))) + (op (match-string 3 out)) (rhs (string-to-number (match-string 4 out))) (post (match-string 5 out)) val) (when (equal pre "-") (setq lhs (- lhs))) - (setq val (if (equal (match-string 3 out) "-") + (setq val (if (equal op "-") (- lhs rhs) (+ lhs rhs)) out (replace-match - (concat (if (and (equal pre "-") - (< val 0)) - "" ; Not "--20" but just "-20" - pre) + (concat (cond ((and (equal pre "-") + (< val 0)) + "") ; Not "--20" but just "-20" + ((and (equal pre "-") + (> val 0)) + "+") ; Not "-+20" but just "+20" + (t pre)) (int-to-string val) post) nil nil out)) )) @@ -11526,22 +11531,23 @@ This repairs those mis-inserted by an AUTOARG." nil nil out))))) out))) -;;(verilog-simplify-range-expression "[1:3]") ; 1 -;;(verilog-simplify-range-expression "[(1):3]") ; 1 -;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; 20 -;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; 48 -;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; FOO*4-2 -;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; FOO*4+0 -;;(verilog-simplify-range-expression "[(func(BAR))]") ; func(BAR) -;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; FOO-0 -;;(verilog-simplify-range-expression "[$clog2(2)]") ; 1 -;;(verilog-simplify-range-expression "[$clog2(7)]") ; 3 -;;(verilog-simplify-range-expression "[(TEST[1])-1:0]") -;;(verilog-simplify-range-expression "[1<<2:8>>2]") ; [4:2] -;;(verilog-simplify-range-expression "[2*4/(4-2) +2+4 <<4 >>2]") +;;(verilog-simplify-range-expression "[1:3]") ; "[1:3]" +;;(verilog-simplify-range-expression "[(1):3]") ; "[1:3]" +;;(verilog-simplify-range-expression "[(((16)+1)+1+(1+1))]") ; "[20]" +;;(verilog-simplify-range-expression "[(2*3+6*7)]") ; "[48]" +;;(verilog-simplify-range-expression "[(FOO*4-1*2)]") ; "[FOO*4-2]" +;;(verilog-simplify-range-expression "[(FOO*4+1-1)]") ; "[FOO*4+0]" +;;(verilog-simplify-range-expression "[(func(BAR))]") ; "[func(BAR)]" +;;(verilog-simplify-range-expression "[FOO-1+1-1+1]") ; "[FOO-0]" +;;(verilog-simplify-range-expression "[FOO-1+2:LSB-3+1]") ; "[FOO+1:LSB-1]" +;;(verilog-simplify-range-expression "[$clog2(2)]") ; "[1]" +;;(verilog-simplify-range-expression "[$clog2(7)]") ; "[3]" +;;(verilog-simplify-range-expression "[(TEST[1])-1:0]") ; "[(TEST[1])-1:0]" +;;(verilog-simplify-range-expression "[1<<2:8>>2]") ; "[4:2]" +;;(verilog-simplify-range-expression "[2*4/(4-2) +2+4 <<4 >>2]") ; "[8/(2) +2+4 <<4 >>2]" ;;(verilog-simplify-range-expression "[WIDTH*2/8-1:0]") ; "[WIDTH*2/8-1:0]" ;;(verilog-simplify-range-expression "[(FOO).size:0]") ; "[FOO.size:0]" - +; (defun verilog-clog2 (value) "Compute $clog2 - ceiling log2 of VALUE." (if (< value 1)