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My design uses interfaces for transmitting different complex types of signals. When using AUTOINST to instantiate a module into another one, the interfaces show up correctly at the instantiation code. However, these signals are not propagated as ports to the module that owns the instance, even though the non-interface-type signals coming from the same instance are properly created.
Is there any variable that has to be set in order to enable interfaces to be brought up the hierarchy?
I created a simple test code to show the issue. It is composed of 3 files: int_i.sv (interface declaration), lower.sv (module that will be instantiated at a higher level), and top.sv (the top level that instantiates the "lower" module).
Hello,
My design uses interfaces for transmitting different complex types of signals. When using AUTOINST to instantiate a module into another one, the interfaces show up correctly at the instantiation code. However, these signals are not propagated as ports to the module that owns the instance, even though the non-interface-type signals coming from the same instance are properly created.
Is there any variable that has to be set in order to enable interfaces to be brought up the hierarchy?
I created a simple test code to show the issue. It is composed of 3 files: int_i.sv (interface declaration), lower.sv (module that will be instantiated at a higher level), and top.sv (the top level that instantiates the "lower" module).
int_i.sv
lower.sv
top.sv, BEFORE running verilog-mode
top.sv, AFTER running verilog-mode
In this example, "my_int.master" was not brought up as ports to the "top" module.
Thank you for any tips,
Marcelo.
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