verilog-pretty-expr doesn't work in latest version

[veripoolbot]

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Author Name: Michael Rytting
Original Redmine Issue: 447 from https://www.veripool.org
Original Date: 2012-03-05

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I have verilog-auto-lineup set to 'all, but the function doesn't line anything up. It no longer prompts for my own regexp (thy myre input to the function is never used). The file I have attached doesn't lineup the assign or the localparam statements like it used to.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-06T02:22:27Z

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The regexp was removed about a year ago. I believe it was rev679. Please confirm if you were using a version before then. Also what regexp do you want to use? I presuming you're looking to have the assignment align but even in rev678 they didn't.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-07T00:22:52Z

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Mac, any thoughts on this?

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-07T00:23:39Z

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Email update:

"It had been a while since I've updated Verilog-mode. I had been using Rev 638 previously. So the verilog-pretty-expr function no longer lines up assign or param assigns? That's unfortunate that the feature went away. I often used the ability to use my own regexp to do alignment in my code."