forked from rajeshfarswan/BOOST-MPPT-CONTROL
-
Notifications
You must be signed in to change notification settings - Fork 0
/
p30f6010A.h
4234 lines (3734 loc) · 149 KB
/
p30f6010A.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*-------------------------------------------------------------------------
*
* MPLAB-C30 dsPIC30F6010A processor header
*
* (c) Copyright 2005-2006 Microchip Technology, All rights reserved
*
* File Description / Notes:
* =========================
* 1] This header file defines special function registers (SFR), and useful
* macros for the dsPIC30Fxxxx Family of Digital Signal
* Controllers (also referred to as the dsPIC).
* 2] The register and bit names used in this file match the
* dsPIC30Fxxxx data sheets as closely as possible.
* 3] The memory locations of the registers defined in this header file are
* specified in the respective linker scripts.
* 4] SFR definitions are listed in the ascending order of memory addresses
* and are grouped based on the module they belong to. For e.g., WREG10
* is listed before ACCAL, and the Core SFRs are grouped separately
* from the Interrupt Controller SFRs or the General Purpose Timer SFRs.
*
* Revision History:
* =================
* --------------------------------------------------------------------------
* Rev: Date: Details: Who:
* --------------------------------------------------------------------------
* 4.1 31 Jan 2005 New file P Sinha
* 4.1a 14 Mar 2005 Removed LVD definitions P Sinha
* 4.2 4 Apr 2005 Renamed EC_IO to ECIO and ERC_IO to ERCIO P Sinha
* 4.2a 11 Apr 2005 Corrected QEI register structures P Sinha
* 4.2b 27 Jun 2005 Fixed typos in comments regarding macros G McCar
* 4.3 1 Jul 2005 Updated section syntax in config macros P Sinha
* v3.00 02 Feb 2007 Added processor check S Curtis
* (Rev reflects compiler version)
* --------------------------------------------------------------------------
*
* ------------------------------------------------------------------------*/
#ifndef __dsPIC30F6010A__
#error "Include file does not match processor setting"
#endif
#ifndef __30F6010A_H
#define __30F6010A_H
/* ------------------------- */
/* Core Register Definitions */
/* ------------------------- */
/* W registers W0-W15 */
extern volatile unsigned int WREG0 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG1 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG2 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG3 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG4 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG5 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG6 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG7 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG8 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG9 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG10 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG11 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG12 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG13 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG14 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG15 __attribute__((__sfr__,__deprecated__,__unsafe__));
/* SPLIM: Stack Pointer Limit */
extern volatile unsigned int SPLIM __attribute__((__sfr__));
/* Alternative access structure for the 40-bit accumulators */
typedef struct tagACC {
unsigned int L;
unsigned int H;
unsigned char U;
} ACC;
/* Acc A<15:0> */
extern volatile unsigned int ACCAL __attribute__((__sfr__));
/* Acc A<31:16> */
extern volatile unsigned int ACCAH __attribute__((__sfr__));
/* Acc A<39:32> */
extern volatile unsigned char ACCAU __attribute__((__sfr__));
/* Acc A defined as a structure consisting of the 3 parts */
extern volatile ACC ACCA __attribute__((__sfr__));
/* Acc B<15:0> */
extern volatile unsigned int ACCBL __attribute__((__sfr__));
/* Acc B<31:16> */
extern volatile unsigned int ACCBH __attribute__((__sfr__));
/* Acc B<39:32> */
extern volatile unsigned char ACCBU __attribute__((__sfr__));
/* Acc B defined as a structure consisting of the 3 parts */
extern volatile ACC ACCB __attribute__((__sfr__));
/* PCL: Program Counter low word */
extern volatile unsigned int PCL __attribute__((__sfr__));
/* PCH: Program Counter high byte */
extern volatile unsigned char PCH __attribute__((__sfr__));
/* TBLPAG: Table Page Register */
extern volatile unsigned char TBLPAG __attribute__((__sfr__));
/* PSVPAG: Program Space Visibility Page Register */
extern volatile unsigned char PSVPAG __attribute__((__sfr__));
/* RCOUNT: REPEAT loop count */
extern volatile unsigned int RCOUNT __attribute__((__sfr__));
/* DCOUNT: DO loop count */
extern volatile unsigned int DCOUNT __attribute__((__sfr__));
/* DOSTARTL: DO loop start address bits <15:0> */
extern volatile unsigned int DOSTARTL __attribute__((__sfr__));
/* DOSTARTH: DO loop start address bits <23:16> */
extern volatile unsigned int DOSTARTH __attribute__((__sfr__));
/* DOENDL: DO loop end address bits <15:0> */
extern volatile unsigned int DOENDL __attribute__((__sfr__));
/* DOENDH: DO loop end address bits <23:16> */
extern volatile unsigned int DOENDH __attribute__((__sfr__));
/* SR: Status Register */
extern volatile unsigned int SR __attribute__((__sfr__));
typedef struct tagSRBITS {
unsigned C :1; /* Carry flag */
unsigned Z :1; /* Sticky Zero flag */
unsigned OV :1; /* Overflow flag */
unsigned N :1; /* Negative flag */
unsigned RA :1; /* REPEAT loop active flag */
unsigned IPL :3; /* CPU Interrupt Priority Level */
unsigned DC :1; /* Digit Carry flag */
unsigned DA :1; /* DO loop active flag */
unsigned SAB :1; /* Combined A/B saturation flag */
unsigned OAB :1; /* Combined A/B overflow flag */
unsigned SB :1; /* Acc B saturation flag */
unsigned SA :1; /* Acc A saturation flag */
unsigned OB :1; /* Acc B overflow flag */
unsigned OA :1; /* Acc A overflow flag */
} SRBITS;
extern volatile SRBITS SRbits __attribute__((__sfr__));
/* CORCON: CPU Mode control Register */
extern volatile unsigned int CORCON __attribute__((__sfr__));
typedef struct tagCORCONBITS {
unsigned IF :1; /* Integer/Fractional mode */
unsigned RND :1; /* Rounding mode */
unsigned PSV :1; /* Program Space Visibility enable */
unsigned IPL3 :1; /* CPU Interrupt Priority Level bit 3 */
unsigned ACCSAT :1; /* Acc saturation mode */
unsigned SATDW :1; /* Data space write saturation enable */
unsigned SATB :1; /* Acc B saturation enable */
unsigned SATA :1; /* Acc A saturation enable */
unsigned DL :3; /* DO loop nesting level status */
unsigned EDT :1; /* Early DO loop termination control */
unsigned US :1; /* Signed/Unsigned mode */
unsigned :3;
} CORCONBITS;
extern volatile CORCONBITS CORCONbits __attribute__((__sfr__));
/* MODCON: Modulo Addressing Control Register */
extern volatile unsigned int MODCON __attribute__((__sfr__));
typedef struct tagMODCONBITS {
unsigned XWM :4; /* X-RAGU/X-WAGU modulo addressing register select */
unsigned YWM :4; /* Y-RAGU modulo addressing register select */
unsigned BWM :4; /* Bit-reversed addressing register select */
unsigned :2;
unsigned YMODEN :1; /* Y-RAGU modulo addressing enable */
unsigned XMODEN :1; /* X-RAGU/X-WAGU modulo addressing enable */
} MODCONBITS;
extern volatile MODCONBITS MODCONbits __attribute__((__sfr__));
/* XMODSRT: X-RAGU/X-WAGU modulo buffer start address */
extern volatile unsigned int XMODSRT __attribute__((__sfr__));
/* XMODEND: X-RAGU/X-WAGU modulo buffer end address */
extern volatile unsigned int XMODEND __attribute__((__sfr__));
/* YMODSRT: Y-RAGU modulo buffer start address */
extern volatile unsigned int YMODSRT __attribute__((__sfr__));
/* YMODEND: Y-RAGU modulo buffer end address */
extern volatile unsigned int YMODEND __attribute__((__sfr__));
/* XBREV: X-WAGU Bit-reversed Addressing Control Register */
extern volatile unsigned int XBREV __attribute__((__sfr__));
typedef struct tagXBREVBITS {
unsigned XB :15; /* Bit-reversed addressing register select */
unsigned BREN :1; /* Bit-reversed addressing enable */
} XBREVBITS;
extern volatile XBREVBITS XBREVbits __attribute__((__sfr__));
/* DISICNT: Disable Interrupt Cycle Count */
extern volatile unsigned int DISICNT __attribute__((__sfr__));
typedef struct tagDISICNTBITS {
unsigned DISICNT:14;
unsigned :2;
} DISICNTBITS;
extern volatile DISICNTBITS DISICNTbits __attribute__((__sfr__));
/* ----------------------------------------- */
/* Interrupt Controller register definitions */
/* ----------------------------------------- */
/* INTCON1: Interrupt Control Register 1 */
extern volatile unsigned int INTCON1 __attribute__((__sfr__));
typedef struct tagINTCON1BITS {
unsigned :1;
unsigned OSCFAIL:1;
unsigned STKERR :1;
unsigned ADDRERR:1;
unsigned MATHERR:1;
unsigned :3;
unsigned COVTE :1;
unsigned OVBTE :1;
unsigned OVATE :1;
unsigned :4;
unsigned NSTDIS :1;
} INTCON1BITS;
extern volatile INTCON1BITS INTCON1bits __attribute__((__sfr__));
/* INTCON2: Interrupt Control Register 2 */
extern volatile unsigned int INTCON2 __attribute__((__sfr__));
typedef struct tagINTCON2BITS {
unsigned INT0EP :1;
unsigned INT1EP :1;
unsigned INT2EP :1;
unsigned INT3EP :1;
unsigned INT4EP :1;
unsigned :9;
unsigned DISI :1;
unsigned ALTIVT :1;
} INTCON2BITS;
extern volatile INTCON2BITS INTCON2bits __attribute__((__sfr__));
/* IFS0: Interrupt Flag Status Register 0 */
extern volatile unsigned int IFS0 __attribute__((__sfr__));
typedef struct tagIFS0BITS {
unsigned INT0IF :1;
unsigned IC1IF :1;
unsigned OC1IF :1;
unsigned T1IF :1;
unsigned IC2IF :1;
unsigned OC2IF :1;
unsigned T2IF :1;
unsigned T3IF :1;
unsigned SPI1IF :1;
unsigned U1RXIF :1;
unsigned U1TXIF :1;
unsigned ADIF :1;
unsigned NVMIF :1;
unsigned SI2CIF :1;
unsigned MI2CIF :1;
unsigned CNIF :1;
} IFS0BITS;
extern volatile IFS0BITS IFS0bits __attribute__((__sfr__));
/* IFS1: Interrupt Flag Status Register 1 */
extern volatile unsigned int IFS1 __attribute__((__sfr__));
typedef struct tagIFS1BITS {
unsigned INT1IF :1;
unsigned IC7IF :1;
unsigned IC8IF :1;
unsigned OC3IF :1;
unsigned OC4IF :1;
unsigned T4IF :1;
unsigned T5IF :1;
unsigned INT2IF :1;
unsigned U2RXIF :1;
unsigned U2TXIF :1;
unsigned SPI2IF :1;
unsigned C1IF :1;
unsigned IC3IF :1;
unsigned IC4IF :1;
unsigned IC5IF :1;
unsigned IC6IF :1;
} IFS1BITS;
extern volatile IFS1BITS IFS1bits __attribute__((__sfr__));
/* IFS2: Interrupt Flag Status Register 2 */
extern volatile unsigned int IFS2 __attribute__((__sfr__));
typedef struct tagIFS2BITS {
unsigned OC5IF :1;
unsigned OC6IF :1;
unsigned OC7IF :1;
unsigned OC8IF :1;
unsigned INT3IF :1;
unsigned INT4IF :1;
unsigned C2IF :1;
unsigned PWMIF :1;
unsigned QEIIF :1;
unsigned :2;
unsigned FLTAIF :1;
unsigned FLTBIF :1;
unsigned :3;
} IFS2BITS;
extern volatile IFS2BITS IFS2bits __attribute__((__sfr__));
/* IEC0: Interrupt Enable Control Register 0 */
extern volatile unsigned int IEC0 __attribute__((__sfr__));
typedef struct tagIEC0BITS {
unsigned INT0IE :1;
unsigned IC1IE :1;
unsigned OC1IE :1;
unsigned T1IE :1;
unsigned IC2IE :1;
unsigned OC2IE :1;
unsigned T2IE :1;
unsigned T3IE :1;
unsigned SPI1IE :1;
unsigned U1RXIE :1;
unsigned U1TXIE :1;
unsigned ADIE :1;
unsigned NVMIE :1;
unsigned SI2CIE :1;
unsigned MI2CIE :1;
unsigned CNIE :1;
} IEC0BITS;
extern volatile IEC0BITS IEC0bits __attribute__((__sfr__));
/* IEC1: Interrupt Enable Control Register 1 */
extern volatile unsigned int IEC1 __attribute__((__sfr__));
typedef struct tagIEC1BITS {
unsigned INT1IE :1;
unsigned IC7IE :1;
unsigned IC8IE :1;
unsigned OC3IE :1;
unsigned OC4IE :1;
unsigned T4IE :1;
unsigned T5IE :1;
unsigned INT2IE :1;
unsigned U2RXIE :1;
unsigned U2TXIE :1;
unsigned SPI2IE :1;
unsigned C1IE :1;
unsigned IC3IE :1;
unsigned IC4IE :1;
unsigned IC5IE :1;
unsigned IC6IE :1;
} IEC1BITS;
extern volatile IEC1BITS IEC1bits __attribute__((__sfr__));
/* IEC2: Interrupt Enable Control Register 2 */
extern volatile unsigned int IEC2 __attribute__((__sfr__));
typedef struct tagIEC2BITS {
unsigned OC5IE :1;
unsigned OC6IE :1;
unsigned OC7IE :1;
unsigned OC8IE :1;
unsigned INT3IE :1;
unsigned INT4IE :1;
unsigned C2IE :1;
unsigned PWMIE :1;
unsigned QEIIE :1;
unsigned :2;
unsigned FLTAIE :1;
unsigned FLTBIE :1;
unsigned :3;
} IEC2BITS;
extern volatile IEC2BITS IEC2bits __attribute__((__sfr__));
/* IPC0: Interrupt Priority Control Register 0 */
extern volatile unsigned int IPC0 __attribute__((__sfr__));
typedef struct tagIPC0BITS {
unsigned INT0IP :3;
unsigned :1;
unsigned IC1IP :3;
unsigned :1;
unsigned OC1IP :3;
unsigned :1;
unsigned T1IP :3;
unsigned :1;
} IPC0BITS;
extern volatile IPC0BITS IPC0bits __attribute__((__sfr__));
/* IPC1: Interrupt Priority Control Register 1 */
extern volatile unsigned int IPC1 __attribute__((__sfr__));
typedef struct tagIPC1BITS {
unsigned IC2IP :3;
unsigned :1;
unsigned OC2IP :3;
unsigned :1;
unsigned T2IP :3;
unsigned :1;
unsigned T3IP :3;
unsigned :1;
} IPC1BITS;
extern volatile IPC1BITS IPC1bits __attribute__((__sfr__));
/* IPC2: Interrupt Priority Control Register 2 */
extern volatile unsigned int IPC2 __attribute__((__sfr__));
typedef struct tagIPC2BITS {
unsigned SPI1IP :3;
unsigned :1;
unsigned U1RXIP :3;
unsigned :1;
unsigned U1TXIP :3;
unsigned :1;
unsigned ADIP :3;
unsigned :1;
} IPC2BITS;
extern volatile IPC2BITS IPC2bits __attribute__((__sfr__));
/* IPC3: Interrupt Priority Control Register 3 */
extern volatile unsigned int IPC3 __attribute__((__sfr__));
typedef struct tagIPC3BITS {
unsigned NVMIP :3;
unsigned :1;
unsigned SI2CIP :3;
unsigned :1;
unsigned MI2CIP :3;
unsigned :1;
unsigned CNIP :3;
unsigned :1;
} IPC3BITS;
extern volatile IPC3BITS IPC3bits __attribute__((__sfr__));
/* IPC4: Interrupt Priority Control Register 4 */
extern volatile unsigned int IPC4 __attribute__((__sfr__));
typedef struct tagIPC4BITS {
unsigned INT1IP :3;
unsigned :1;
unsigned IC7IP :3;
unsigned :1;
unsigned IC8IP :3;
unsigned :1;
unsigned OC3IP :3;
unsigned :1;
} IPC4BITS;
extern volatile IPC4BITS IPC4bits __attribute__((__sfr__));
/* IPC5: Interrupt Priority Control Register 5 */
extern volatile unsigned int IPC5 __attribute__((__sfr__));
typedef struct tagIPC5BITS {
unsigned OC4IP :3;
unsigned :1;
unsigned T4IP :3;
unsigned :1;
unsigned T5IP :3;
unsigned :1;
unsigned INT2IP :3;
unsigned :1;
} IPC5BITS;
extern volatile IPC5BITS IPC5bits __attribute__((__sfr__));
/* IPC6: Interrupt Priority Control Register 6 */
extern volatile unsigned int IPC6 __attribute__((__sfr__));
typedef struct tagIPC6BITS {
unsigned U2RXIP :3;
unsigned :1;
unsigned U2TXIP :3;
unsigned :1;
unsigned SPI2IP :3;
unsigned :1;
unsigned C1IP :3;
unsigned :1;
} IPC6BITS;
extern volatile IPC6BITS IPC6bits __attribute__((__sfr__));
/* IPC7: Interrupt Priority Control Register 7 */
extern volatile unsigned int IPC7 __attribute__((__sfr__));
typedef struct tagIPC7BITS {
unsigned IC3IP :3;
unsigned :1;
unsigned IC4IP :3;
unsigned :1;
unsigned IC5IP :3;
unsigned :1;
unsigned IC6IP :3;
unsigned :1;
} IPC7BITS;
extern volatile IPC7BITS IPC7bits __attribute__((__sfr__));
/* IPC8: Interrupt Priority Control Register 8 */
extern volatile unsigned int IPC8 __attribute__((__sfr__));
typedef struct tagIPC8BITS {
unsigned OC5IP :3;
unsigned :1;
unsigned OC6IP :3;
unsigned :1;
unsigned OC7IP :3;
unsigned :1;
unsigned OC8IP :3;
unsigned :1;
} IPC8BITS;
extern volatile IPC8BITS IPC8bits __attribute__((__sfr__));
/* IPC9: Interrupt Priority Control Register 9 */
extern volatile unsigned int IPC9 __attribute__((__sfr__));
typedef struct tagIPC9BITS {
unsigned INT3IP :3;
unsigned :1;
unsigned INT4IP :3;
unsigned :1;
unsigned C2IP :3;
unsigned :1;
unsigned PWMIP :3;
unsigned :1;
} IPC9BITS;
extern volatile IPC9BITS IPC9bits __attribute__((__sfr__));
/* IPC10: Interrupt Priority Control Register 10 */
extern volatile unsigned int IPC10 __attribute__((__sfr__));
typedef struct tagIPC10BITS {
unsigned QEIIP :3;
unsigned :9;
unsigned FLTAIP :3;
unsigned :1;
} IPC10BITS;
extern volatile IPC10BITS IPC10bits __attribute__((__sfr__));
/* IPC11: Interrupt Priority Control Register 11 */
extern volatile unsigned int IPC11 __attribute__((__sfr__));
typedef struct tagIPC11BITS {
unsigned FLTBIP :3;
unsigned :13;
} IPC11BITS;
extern volatile IPC11BITS IPC11bits __attribute__((__sfr__));
/* INTTREG: Interrupt Controller Test Register */
extern volatile unsigned int INTTREG __attribute__((__sfr__));
typedef struct tagINTTREGBITS {
unsigned VECNUM :6;
unsigned :2;
unsigned ILR :4;
unsigned :1;
unsigned VHOLD :1;
unsigned TMODE :1;
unsigned IRQTOCPU:1;
} INTTREGBITS;
extern volatile INTTREGBITS INTTREGbits __attribute__((__sfr__));
/* ---------------------------------------------- */
/* Input Change Notification register definitions */
/* ---------------------------------------------- */
/* CNEN1: Input Change Notification Interrupt Enable Register 1 */
extern volatile unsigned int CNEN1 __attribute__((__sfr__));
typedef struct tagCNEN1BITS {
unsigned CN0IE :1;
unsigned CN1IE :1;
unsigned CN2IE :1;
unsigned CN3IE :1;
unsigned CN4IE :1;
unsigned CN5IE :1;
unsigned CN6IE :1;
unsigned CN7IE :1;
unsigned CN8IE :1;
unsigned CN9IE :1;
unsigned CN10IE :1;
unsigned CN11IE :1;
unsigned CN12IE :1;
unsigned CN13IE :1;
unsigned CN14IE :1;
unsigned CN15IE :1;
} CNEN1BITS;
extern volatile CNEN1BITS CNEN1bits __attribute__((__sfr__));
/* CNEN2: Input Change Notification Interrupt Enable Register 2 */
extern volatile unsigned int CNEN2 __attribute__((__sfr__));
typedef struct tagCNEN2BITS {
unsigned CN16IE :1;
unsigned CN17IE :1;
unsigned CN18IE :1;
unsigned CN19IE :1;
unsigned CN20IE :1;
unsigned CN21IE :1;
unsigned :10;
} CNEN2BITS;
extern volatile CNEN2BITS CNEN2bits __attribute__((__sfr__));
/* CNPU1: Input Change Notification Pullup Enable Register 1 */
extern volatile unsigned int CNPU1 __attribute__((__sfr__));
typedef struct tagCNPU1BITS {
unsigned CN0PUE :1;
unsigned CN1PUE :1;
unsigned CN2PUE :1;
unsigned CN3PUE :1;
unsigned CN4PUE :1;
unsigned CN5PUE :1;
unsigned CN6PUE :1;
unsigned CN7PUE :1;
unsigned CN8PUE :1;
unsigned CN9PUE :1;
unsigned CN10PUE:1;
unsigned CN11PUE:1;
unsigned CN12PUE:1;
unsigned CN13PUE:1;
unsigned CN14PUE:1;
unsigned CN15PUE:1;
} CNPU1BITS;
extern volatile CNPU1BITS CNPU1bits __attribute__((__sfr__));
/* CNPU2: Input Change Notification Pullup Enable Register 2 */
extern volatile unsigned int CNPU2 __attribute__((__sfr__));
typedef struct tagCNPU2BITS {
unsigned CN16PUE:1;
unsigned CN17PUE:1;
unsigned CN18PUE:1;
unsigned CN19PUE:1;
unsigned CN20PUE:1;
unsigned CN21PUE:1;
unsigned :10;
} CNPU2BITS;
extern volatile CNPU2BITS CNPU2bits __attribute__((__sfr__));
/* --------------------------- */
/* Timer1 register definitions */
/* --------------------------- */
/* Generic structure for Timer 1 Control Register */
typedef struct tagTCON_16BIT {
unsigned :1;
unsigned TCS :1;
unsigned TSYNC :1;
unsigned :1;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_16BIT;
/* TMR1: Timer 1 Count Register */
extern volatile unsigned int TMR1 __attribute__((__sfr__));
/* PR1: Timer 1 Period Register */
extern volatile unsigned int PR1 __attribute__((__sfr__));
/* T1CON: Timer 1 Control Register */
extern volatile unsigned int T1CON __attribute__((__sfr__));
extern volatile TCON_16BIT T1CONbits __attribute__((__sfr__));
/* ----------------------------- */
/* Timer2/3 register definitions */
/* ----------------------------- */
/* Generic structure for Timer 2 and Timer 4 Control Registers */
typedef struct tagTCON_EVEN {
unsigned :1;
unsigned TCS :1;
unsigned :1;
unsigned T32 :1;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_EVEN;
/* Generic structure for Timer 3 and Timer 5 Control Registers */
typedef struct tagTCON_ODD {
unsigned :1;
unsigned TCS :1;
unsigned :2;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_ODD;
/* TMR2: Timer 2 Count Register */
extern volatile unsigned int TMR2 __attribute__((__sfr__));
/* TMR3HLD: Timer 3 Holding Register */
extern volatile unsigned int TMR3HLD __attribute__((__sfr__));
/* TMR3: Timer 3 Count Register */
extern volatile unsigned int TMR3 __attribute__((__sfr__));
/* PR2: Timer 2 Period Register */
extern volatile unsigned int PR2 __attribute__((__sfr__));
/* PR3: Timer 3 Period Register */
extern volatile unsigned int PR3 __attribute__((__sfr__));
/* T2CON: Timer 2 Control Register */
extern volatile unsigned int T2CON __attribute__((__sfr__));
extern volatile TCON_EVEN T2CONbits __attribute__((__sfr__));
/* T3CON: Timer 3 Control Register */
extern volatile unsigned int T3CON __attribute__((__sfr__));
extern volatile TCON_ODD T3CONbits __attribute__((__sfr__));
/* ----------------------------- */
/* Timer4/5 register definitions */
/* ----------------------------- */
/* TMR4: Timer 4 Count Register */
extern volatile unsigned int TMR4 __attribute__((__sfr__));
/* TMR5HLD: Timer 5 Holding Register */
extern volatile unsigned int TMR5HLD __attribute__((__sfr__));
/* TMR5: Timer 5 Count Register */
extern volatile unsigned int TMR5 __attribute__((__sfr__));
/* PR4: Timer 4 Period Register */
extern volatile unsigned int PR4 __attribute__((__sfr__));
/* PR5: Timer 5 Period Register */
extern volatile unsigned int PR5 __attribute__((__sfr__));
/* T4CON: Timer 4 Control Register */
extern volatile unsigned int T4CON __attribute__((__sfr__));
extern volatile TCON_EVEN T4CONbits __attribute__((__sfr__));
/* T5CON: Timer 5 Control Register */
extern volatile unsigned int T5CON __attribute__((__sfr__));
extern volatile TCON_ODD T5CONbits __attribute__((__sfr__));
/* ------------------------------------------------- */
/* Quadrature Encoder Interface register definitions */
/* ------------------------------------------------- */
/* QEICON: QEI Control Register */
extern volatile unsigned int QEICON __attribute__((__sfr__));
typedef struct tagQEICONBITS {
unsigned UPDN_SRC:1;
unsigned TQCS :1;
unsigned POSRES :1;
unsigned TQCKPS :2;
unsigned TQGATE :1;
unsigned PCDOUT :1;
unsigned SWPAB :1;
unsigned QEIM :3;
unsigned UPDN :1;
unsigned INDX :1;
unsigned QEISIDL:1;
unsigned :1;
unsigned CNTERR :1;
} QEICONBITS;
extern volatile QEICONBITS QEICONbits __attribute__((__sfr__));
/* DFLTCON: Digital Filter Control Register */
extern volatile unsigned int DFLTCON __attribute__((__sfr__));
typedef struct tagDFLTCONBITS {
unsigned :4;
unsigned QECK :3;
unsigned QEOUT :1;
unsigned CEID :1;
unsigned IMV :2;
unsigned :5;
} DFLTCONBITS;
extern volatile DFLTCONBITS DFLTCONbits __attribute__((__sfr__));
/* POSCNT: Position Counter Register */
extern volatile unsigned int POSCNT __attribute__((__sfr__));
/* MAXCNT: Maximum Count Register */
extern volatile unsigned int MAXCNT __attribute__((__sfr__));
/* ---------------------------------- */
/* Input Capture register definitions */
/* ---------------------------------- */
/* Generic structure of entire SFR area for each Input Capture module */
typedef struct tagIC {
unsigned int icxbuf;
unsigned int icxcon;
} IC, *PIC;
/* SFR blocks for each Input Capture module */
extern volatile IC IC1 __attribute__((__sfr__));
extern volatile IC IC2 __attribute__((__sfr__));
extern volatile IC IC3 __attribute__((__sfr__));
extern volatile IC IC4 __attribute__((__sfr__));
extern volatile IC IC5 __attribute__((__sfr__));
extern volatile IC IC6 __attribute__((__sfr__));
extern volatile IC IC7 __attribute__((__sfr__));
extern volatile IC IC8 __attribute__((__sfr__));
/* Generic structure for Input Capture Control Registers */
typedef struct tagICxCONBITS {
unsigned ICM :3;
unsigned ICBNE :1;
unsigned ICOV :1;
unsigned ICI :2;
unsigned ICTMR :1;
unsigned :5;
unsigned ICSIDL :1;
unsigned :2;
} ICxCONBITS;
/* IC1BUF: Input Capture 1 Buffer */
extern volatile unsigned int IC1BUF __attribute__((__sfr__));
/* IC1CON: Input Capture 1 Control Register */
extern volatile unsigned int IC1CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC1CONbits __attribute__((__sfr__));
/* IC2BUF: Input Capture 2 Buffer */
extern volatile unsigned int IC2BUF __attribute__((__sfr__));
/* IC2CON: Input Capture 2 Control Register */
extern volatile unsigned int IC2CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC2CONbits __attribute__((__sfr__));
/* IC3BUF: Input Capture 3 Buffer */
extern volatile unsigned int IC3BUF __attribute__((__sfr__));
/* IC3CON: Input Capture 3 Control Register */
extern volatile unsigned int IC3CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC3CONbits __attribute__((__sfr__));
/* IC4BUF: Input Capture 4 Buffer */
extern volatile unsigned int IC4BUF __attribute__((__sfr__));
/* IC4CON: Input Capture 4 Control Register */
extern volatile unsigned int IC4CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC4CONbits __attribute__((__sfr__));
/* IC5BUF: Input Capture 5 Buffer */
extern volatile unsigned int IC5BUF __attribute__((__sfr__));
/* IC5CON: Input Capture 5 Control Register */
extern volatile unsigned int IC5CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC5CONbits __attribute__((__sfr__));
/* IC6BUF: Input Capture 6 Buffer */
extern volatile unsigned int IC6BUF __attribute__((__sfr__));
/* IC6CON: Input Capture 6 Control Register */
extern volatile unsigned int IC6CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC6CONbits __attribute__((__sfr__));
/* IC7BUF: Input Capture 7 Buffer */
extern volatile unsigned int IC7BUF __attribute__((__sfr__));
/* IC7CON: Input Capture 7 Control Register */
extern volatile unsigned int IC7CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC7CONbits __attribute__((__sfr__));
/* IC8BUF: Input Capture 8 Buffer */
extern volatile unsigned int IC8BUF __attribute__((__sfr__));
/* IC8CON: Input Capture 8 Control Register */
extern volatile unsigned int IC8CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC8CONbits __attribute__((__sfr__));
/* --------------------------------------- */
/* Output Compare/PWM register definitions */
/* --------------------------------------- */
/* Generic structure of entire SFR area for each Output Compare module */
typedef struct tagOC {
unsigned int ocxrs;
unsigned int ocxr;
unsigned int ocxcon;
} OC, *POC;
/* SFR blocks for each Output Compare module */
extern volatile OC OC1 __attribute__((__sfr__));
extern volatile OC OC2 __attribute__((__sfr__));
extern volatile OC OC3 __attribute__((__sfr__));
extern volatile OC OC4 __attribute__((__sfr__));
extern volatile OC OC5 __attribute__((__sfr__));
extern volatile OC OC6 __attribute__((__sfr__));
extern volatile OC OC7 __attribute__((__sfr__));
extern volatile OC OC8 __attribute__((__sfr__));
/* Generic structure for Output Compare Control Registers */
typedef struct tagOCxCONBITS {
unsigned OCM :3;
unsigned OCTSEL :1;
unsigned OCFLT :1;
unsigned :8;
unsigned OCSIDL :1;
unsigned :2;
} OCxCONBITS;
/* OC1RS: Output Compare 1 Secondary Register */
extern volatile unsigned int OC1RS __attribute__((__sfr__));
/* OC1R: Output Compare 1 Main Register */
extern volatile unsigned int OC1R __attribute__((__sfr__));
/* OC1CON: Output Compare 1 Control Register */
extern volatile unsigned int OC1CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC1CONbits __attribute__((__sfr__));
/* OC2RS: Output Compare 2 Secondary Register */
extern volatile unsigned int OC2RS __attribute__((__sfr__));
/* OC2R: Output Compare 2 Main Register */
extern volatile unsigned int OC2R __attribute__((__sfr__));
/* OC2CON: Output Compare 2 Control Register */
extern volatile unsigned int OC2CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC2CONbits __attribute__((__sfr__));
/* OC3RS: Output Compare 3 Secondary Register */
extern volatile unsigned int OC3RS __attribute__((__sfr__));
/* OC3R: Output Compare 3 Main Register */
extern volatile unsigned int OC3R __attribute__((__sfr__));
/* OC3CON: Output Compare 3 Control Register */
extern volatile unsigned int OC3CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC3CONbits __attribute__((__sfr__));
/* OC4RS: Output Compare 4 Secondary Register */
extern volatile unsigned int OC4RS __attribute__((__sfr__));
/* OC4R: Output Compare 4 Main Register */
extern volatile unsigned int OC4R __attribute__((__sfr__));
/* OC4CON: Output Compare 4 Control Register */
extern volatile unsigned int OC4CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC4CONbits __attribute__((__sfr__));
/* OC5RS: Output Compare 5 Secondary Register */
extern volatile unsigned int OC5RS __attribute__((__sfr__));
/* OC5R: Output Compare 5 Main Register */
extern volatile unsigned int OC5R __attribute__((__sfr__));
/* OC5CON: Output Compare 5 Control Register */
extern volatile unsigned int OC5CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC5CONbits __attribute__((__sfr__));
/* OC6RS: Output Compare 6 Secondary Register */
extern volatile unsigned int OC6RS __attribute__((__sfr__));
/* OC6R: Output Compare 6 Main Register */
extern volatile unsigned int OC6R __attribute__((__sfr__));
/* OC6CON: Output Compare 6 Control Register */
extern volatile unsigned int OC6CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC6CONbits __attribute__((__sfr__));
/* OC7RS: Output Compare 7 Secondary Register */
extern volatile unsigned int OC7RS __attribute__((__sfr__));
/* OC7R: Output Compare 7 Main Register */
extern volatile unsigned int OC7R __attribute__((__sfr__));
/* OC7CON: Output Compare 7 Control Register */
extern volatile unsigned int OC7CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC7CONbits __attribute__((__sfr__));
/* OC8RS: Output Compare 8 Secondary Register */
extern volatile unsigned int OC8RS __attribute__((__sfr__));
/* OC8R: Output Compare 8 Main Register */
extern volatile unsigned int OC8R __attribute__((__sfr__));
/* OC8CON: Output Compare 8 Control Register */
extern volatile unsigned int OC8CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC8CONbits __attribute__((__sfr__));
/* -------------------------------------- */
/* Motor Control PWM register definitions */
/* -------------------------------------- */
/* PTCON: PWM Timerbase Control Register */
extern volatile unsigned int PTCON __attribute__((__sfr__));
typedef struct tagPTCONBITS {
unsigned PTMOD :2;
unsigned PTCKPS :2;
unsigned PTOPS :4;
unsigned :5;
unsigned PTSIDL :1;
unsigned :1;
unsigned PTEN :1;
} PTCONBITS;
extern volatile PTCONBITS PTCONbits __attribute__((__sfr__));
/* PTMR: PWM Timebase Count Register */
extern volatile unsigned int PTMR __attribute__((__sfr__));
typedef struct tagPTMRBITS {
unsigned PTMR :15;
unsigned PTDIR :1;
} PTMRBITS;
extern volatile PTMRBITS PTMRbits __attribute__((__sfr__));
/* PTPER: PWM Timebase Period Register */
extern volatile unsigned int PTPER __attribute__((__sfr__));
typedef struct tagPTPERBITS {