From 1f9425f033c206528342eb9f1f2d788c238625a1 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 16 Dec 2024 18:11:49 +0100
Subject: [PATCH] peepopt: continue tests, mixed success

---
 tests/various/peepopt_muldiv_c.ys | 201 +++++++++++++++++++++++++++++-
 1 file changed, 199 insertions(+), 2 deletions(-)

diff --git a/tests/various/peepopt_muldiv_c.ys b/tests/various/peepopt_muldiv_c.ys
index fb9708b1938..4f6ac37f1b5 100644
--- a/tests/various/peepopt_muldiv_c.ys
+++ b/tests/various/peepopt_muldiv_c.ys
@@ -1,11 +1,208 @@
+# basic pattern: (a * b) / c
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
 	output signed [7:0] y,
 );
     wire signed [7:0] mul;
-	assign mul = a * 4'sd4;
+	assign mul = a * 4'sd6;
+	assign y = mul / 8'sd3;
+endmodule
+EOT
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$div
+design -reset
+
+read_verilog <<EOT
+module top(
+	input [3:0] a,
+	output [7:0] y,
+);
+    wire [7:0] mul;
+	assign mul = a * 4'd6;
+	assign y = mul / 8'd3;
+endmodule
+EOT
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$div
+design -reset
+
+# No transform when b not divisible by c
+read_verilog <<EOT
+module top(
+	input signed [3:0] a,
+	output signed [7:0] y,
+);
+    wire signed [7:0] mul;
+	assign mul = a * 4'sd3;
 	assign y = mul / 8'sd2;
 endmodule
 EOT
-equiv_opt peepopt
\ No newline at end of file
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 1 t:$div
+design -reset
+
+# No transform when product has a second fanout
+read_verilog <<EOT
+module top(
+	input signed [3:0] a,
+	output signed [7:0] y,
+	output signed [7:0] z,
+);
+    wire signed [7:0] mul;
+	assign mul = a * 4'sd6;
+	assign y = mul / 8'sd3;
+	assign z = mul;
+endmodule
+EOT
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 1 t:$div
+design -reset
+
+# SIGFPE!
+# No transform when divisor is 0
+# read_verilog <<EOT
+# module top(
+# 	input signed [3:0] a,
+# 	output signed [7:0] y,
+# );
+#     wire signed [7:0] mul;
+# 	assign mul = a * 4'sd4;
+# 	assign y = mul / 8'sd0;
+# endmodule
+# EOT
+# equiv_opt peepopt
+# design -load postopt
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+
+# No transform when (a*b) output can overflow (divider’s A input signed)
+# read_verilog <<EOT
+# module top(
+# 	input signed [3:0] a,
+# 	output signed [7:0] y,
+# );
+#     wire signed [5:0] mul;
+# 	assign mul = a * 4'sd6;
+# 	assign y = mul / 8'sd3;
+# endmodule
+# EOT
+# equiv_opt -assert peepopt
+# design -load postopt
+# write_verilog
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+# read_verilog <<EOT
+# module top(
+# 	input signed [3:0] a,
+# 	output signed [7:0] y,
+# );
+#     wire signed [6:0] mul;
+# 	assign mul = a * 4'sd6;
+# 	assign y = mul / 8'sd3;
+# endmodule
+# EOT
+# equiv_opt -assert peepopt
+# design -load postopt
+# write_verilog
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+
+# No transform when (a*b) output can overflow (divider’s A input unsigned)
+# read_verilog <<EOT
+# module top(
+# 	input [3:0] a,
+# 	output [7:0] y,
+# );
+#     wire [4:0] mul;
+# 	assign mul = a * 4'd4;
+# 	assign y = mul / 8'd2;
+# endmodule
+# EOT
+# equiv_opt -assert peepopt
+# design -load postopt
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+# read_verilog <<EOT
+# module top(
+# 	input [3:0] a,
+# 	output [7:0] y,
+# );
+#     wire [6:0] mul;
+# 	assign mul = a * 4'd4;
+# 	assign y = mul / 8'd2;
+# endmodule
+# EOT
+# equiv_opt -assert peepopt
+# design -load postopt
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+
+# No transform when (a*b) and x/c fitting criteria but not connected (x != a*b)
+# read_verilog <<EOT
+# module top(
+# 	input signed [3:0] a,
+# 	input signed [7:0] b,
+# 	output signed [7:0] y,
+# 	output signed [7:0] z,
+# );
+# 	assign y = a * 4'sd6;
+# 	assign z = b / 8'sd3;
+# endmodule
+# EOT
+# equiv_opt -assert peepopt
+# design -load postopt
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+
+# No transform when b only divisible by c if c misinterpreted as unsigned
+read_verilog <<EOT
+module top(
+	input signed [3:0] a,
+	output signed [7:0] y,
+);
+    wire signed [7:0] mul;
+	assign mul = a * 4'sd6;
+	assign y = mul / 3'sb110;
+endmodule
+EOT
+equiv_opt -assert peepopt
+# design -load postopt
+# show
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset
+
+# No transform when b only divisible by c if b misinterpreted as unsigned
+# read_verilog <<EOT
+# module top(
+# 	input signed [3:0] a,
+# 	output signed [7:0] y,
+# );
+#     wire signed [7:0] mul;
+# 	assign mul = a * -4'sd8;
+# 	assign y = mul / 8'sd2;
+# endmodule
+# EOT
+# dump
+# peepopt
+# show
+# equiv_opt -assert peepopt
+# design -load postopt
+# select -assert-count 1 t:$mul
+# select -assert-count 1 t:$div
+# design -reset