From 84bdaf610c654d4ce9773cdebfa0dd41f1cbd8b2 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 13 Dec 2024 11:06:48 +0100
Subject: [PATCH] splitfanout: added blackbox, alu, booth to test

---
 tests/various/splitfanout.ys | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/tests/various/splitfanout.ys b/tests/various/splitfanout.ys
index d89511487f4..dd7be03fd45 100644
--- a/tests/various/splitfanout.ys
+++ b/tests/various/splitfanout.ys
@@ -347,3 +347,43 @@ select -assert-count 1 t:$logic_not
 design -load postopt
 select -assert-count 2 t:$logic_not
 design -reset
+
+# Cell is a blackbox
+read_verilog <<EOT
+(* blackbox *)
+module MY_AND(input A, B, output Y);
+endmodule
+module top(input A, B, output Y, Z);
+wire X;
+MY_AND a(A,B,X);
+assign Y = X;
+assign Z = X;
+endmodule
+EOT
+proc -noopt
+hierarchy
+select -assert-count 1 t:MY_AND
+splitfanout
+select -assert-count 2 t:MY_AND
+design -reset
+
+# A less trivial design
+read_verilog ../sat/alu.v
+proc -noopt
+equiv_opt splitfanout
+design -load preopt
+select -assert-count 5 t:$dff
+design -load postopt
+select -assert-count 8 t:$dff
+design -reset
+
+# Booth-encoded 4x4->8 multiplier smoke test
+read_verilog <<EOT
+module top(input [3:0] A, input [3:0] B, output [7:0] Y);
+assign Y = A * B;
+endmodule
+EOT
+booth
+show
+equiv_opt splitfanout
+design -reset