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emax6.c
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emax6.c
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static char RcsHeader[] = "$Header: /usr/home/nakashim/proj-arm64/src/csim/RCS/emax6.c,v 1.408 2022/10/28 09:13:28 nakashim Exp nakashim $";
/* EMAX6 Simulator */
/* Copyright (C) 2012 by NAIST */
/* Primary writer: Y.Nakashima */
/* nakashim@is.naist.jp */
/* emax6.c 2012/9/22 */
#include <stdio.h>
#include "csim.h"
#include "../conv-c2c/emax6.h"
#include "../conv-c2c/emax6lib.c"
/* CGRA hardware */
struct axiif { /* axi status of EMAX6 */
/* physical interface of AXI/ZYNQ */
Ull axi_awaddr ; /* aligned-address of mm v */
Ull axi_awlen :16; /* aligned-length of mm v */
Ull axi_awvalid : 1; /* axi <- fsm */
Ull axi_awready : 1; /* axi -> fsm */
Ull axi_wstrb :32; /* axi byte-enable for 32B */
Ull axi_wdata[UNIT_WIDTH] ; /* axi -> write-data v */
Ull axi_wvalid : 1; /* axi -> fsm write-valid */
Ull axi_wlast : 1; /* axi -> fsm write-last */
Ull axi_wready : 1; /* axi <- fsm write-ready */
Ull axi_araddr ; /* aligned-address of mm v v v v v */
Ull axi_arlen :16; /* aligned-length of mm v v v v 1 */
Ull axi_arvalid : 1; /* axi <- fsm */
Ull axi_arready : 1; /* axi -> fsm */
Ull axi_rdata[UNIT_WIDTH] ; /* axi read-data v v v v v */
Ull axi_rvalid : 1; /* axi <- fsm read-valid */
Ull axi_rlast : 1; /* axi <- fsm read-last */
Ull axi_rready : 1; /* axi -> fsm read-ready */
/* work for axi-side */
Ull dma_stat : 2; /* 0:none, 2:dma_lmmread, 3:dma_lmmwrite */
Ull wadr_sent : 1; /* 0:none, 1:sent for write */
Ull radr_sent : 1; /* 0:none, 1:sent for read */
Ull dadr :31; /* ddr-adr (internal) */
Ull madr :31; /* lmm-adr (internal) */
Ull mlen :16; /* len (internal) */
Ull mreq :16; /* counter (internal) */
Ull fmask : 8; /* mask for first 32B-chunk */
Ull lmask : 8; /* mask for last 32B-chunk */
/* work for emax-side */
Ull wadr_recv : 1; /* 0:none, 1:recv for write */
Ull radr_recv : 1; /* 0:none, 1:recv for read */
Ull reqn :16; /* AXIから送出されたon-the-fly req数 */
Ull creg : 1; /* 0:RD unit regs, 1:RD control regs */
Ull srw : 1; /* 0:read, 1:write */
Ull sadr :31; /* adr (internal) */
Ull slen :16; /* len (internal) */
Ull sreq :16; /* counter (internal) */
/* physical interface (pipelined) to EMAX6-body */
Ull axring_ful2 : 2; /* 0:empty, 2:full */
Ull axring_b_top : 2; /* to be enqueued next */
Ull axring_b_bot : 2; /* to be dequeued next */
Ull exring_deq_wait : 1; /* synchronize exring deq */
#define AXRING_BR_BUF 2
struct axring_br {
Ull rw : 1; /* 0:read, 1:write */
Ull ty : 3; /* 0:reg/conf, 1:reg/breg, 2:reg/addr, 3:lddmq/tr, 4:lmm, 567:-- */
Ull col : 2; /* logical col# for target lmm */
Ull sq :16; /* sequential # for pipelined DMA 0:last, init by awlen/arlen and decremented */
Ull av : 1; /* address valid */
Ull a :31; /* logical addr reg/lmm */
Ull dm :32; /* <- lmm wdata */
Ull d[UNIT_WIDTH] ; /* <- lmm wdata/rdata */
} axring_br[AXRING_BR_BUF]; /* reg */
Ull deq_wait : 1; /* AXI->unit[EMAX_DEPTH/LMRING_MUX-1, EMAX_DEPTH/LMRING_MUX*2-1,...] */
} axiif[MAXCORE]; /* used as EMAX_NCHIP */
struct exring { /* ex status of EMAX6 */
Ull cmd_busy : 1; /* reg_ctrl.statに直接反映 */
Ull unit_busy : 1; /* reg_ctrl.statに直接反映 */
Ull cycle : 3;
struct unit { /* hardware status of EMAX6 units */
Ull cmd : 2; /* internal copy of reg_ctrl.cmd */
Ull cycle : 3; /* previous unit1_exec/stop is reffered every 4 cycles */
/* previous br[0/1] is switched every 4 cycles */
/* brout[cycle-4] is updated */
Ull l_row : 6; /* 0..63 *//* 0の物理行が起動の起点 */
Ull scon_count : 7; /* conf.mapdist*2 */
Ull one_shot : 1; /* reg *//* self_loop_control 0:init 1:self_loop, keep 0 in first 4 cycles */
Ull one_shot2 : 1; /* one_shot for stage2 */
Ull one_shot_fold : 1; /* folding用にone_shotから4τ遅延 */
Ull one_shot_fold2: 1; /* folding用にone_shotから5τ遅延 */
Ull one_shot_fold3: 1; /* folding用にone_shotから6τ遅延 */
Ull one_shot_fold4: 1; /* folding用にone_shotから7τ遅延 */
Ull unit1_exec : 1; /* 次の動作を指示 (cex,exe,eag), 0:wait 1:exec *//* reg_ctrl.statに直接反映 */
Ull unit1_fold : 1; /* folding用にunit1_execから4τ遅延 */
Ull stage_forstat : 2; /* from for()for(), bit0:LOOP0=zero, bit1:LOOP1=zero stage2において毎サイクル生成 */
Ull unit1_forstat : 2; /* from for()for(), bit0:LOOP0=zero, bit1:LOOP1=zero 4τ毎に生成 */
Ull unit1_forstat2: 2; /* unit1_forstat for stage2 */
Ull unit1_forstat_fold: 2; /* forstat+folding for stage1 */
Ull unit1_forstat_fold2: 2; /* forstat+folding for stage2 */
Ull unit1_forstat_fold3: 2; /* forstat+folding for stage3 */
Ull unit1_forstat_fold4: 2; /* forstat+folding for stage4 */
Ull unit1_arbrk : 1; /* loop最終命令の実行完了を表示 */
Ull unit1_stop : 1; /* 次の動作を指示 (cex,exe,eag), 0:wait 1:stop */
Ull tr_valid : 1; /* TRの状態を表示 */
Ull unit2_exec : 1; /* 次の動作を指示 (lmm), 0:wait 1:exec *//* reg_ctrl.statに直接反映 */
Ull unit2_fold : 1; /* folding用にunit2_execから4τ遅延 */
Ull unit2_forstat : 2; /* from for()for(), bit0:LOOP0=zero, bit1:LOOP1=zero */
Ull unit2_stop : 1; /* 次の動作を指示 (lmm), 0:wait 1:stop */
Ull brout_valid : 1; /* BRの状態を表示 常時tr_validを1τ後に伝搬 */
Ull stage2_exec : 1; /* unit1_exec -> stage2_exec */
Ull stage2_fold : 1; /* folding用にstage2_execから4τ遅延 */
Ull stage3_exec : 1; /* stage2_exec -> stage3_exec */
Ull stage3_fold : 1; /* folding用にstage3_execから4τ遅延 */
Ull stage4_exec : 1; /* stage3_exec -> stage4_exec */
Ull stage4_fold : 1; /* folding用にstage4_execから4τ遅延 */
Ull cx[EMAX_WIDTH] ; /* reg */
Ull cx2dr : 2; /* reg *//* bit1: 0:none 1:exec, bit0: 0:none 1:exec */
Ull cx3dr : 2; /* reg *//* bit1: 0:none 1:exec, bit0: 0:none 1:exec */
Ull ex1 ; /* reg *//* in for ALU */
Ull ex2 ; /* reg *//* in for ALU */
Ull ex3 ; /* reg *//* in for ALU */
Ull ex2passr1 : 8; /* reg *//* pass r1 for OP_SFMA */
Ull ex2passr2 ; /* reg *//* pass r4 for OP_SFMA/x11_softu64_dist */
Ull ex2passr3 ; /* reg *//* pass r4 for OP_SFMA/x11_softu64_dist */
Ull ex2passr4 : 8; /* reg *//* pass r4 for OP_SFMA */
Ull ex2dr ; /* reg *//* out from first-stage */
Ull ex2dr_sfma0 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma1 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma2 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma3 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma4 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma5 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma6 ; /* reg *//* out from first-stage/softu64 */
Ull ex2dr_sfma7 ; /* reg *//* out from first-stage/softu64 */
Ull ex3passr1 : 8; /* reg *//* pass r1 for OP_SFMA */
Ull ex3passr2 ; /* reg *//* pass r4 for OP_SFMA/x11_softu64_dist */
Ull ex3passr3 ; /* reg *//* pass r4 for OP_SFMA/x11_softu64_dist */
Ull ex3dr ; /* reg *//* out from second-stage */
Ull ex4dr_prev ; /* reg *//* for siml-loop only */
Ull ex4dr ; /* reg *//* out from third-stage */
Ull eab :18; /* wire *//* in for ALU */
Ull eao :64; /* wire *//* in for ALU */
Ull ea0b :18; /* reg *//* in for EA0 */
Ull ea0o :64; /* reg *//* in for EA0 */
Ull ea1b :18; /* reg *//* in for EA1 */
Ull ea1o :64; /* reg *//* in for EA1 */
Ull ea02dofs ; /* reg *//* ★for passing eag offset */
Ull ea02dr ; /* reg *//* for mex(&addr) pointer */
Ull ea12dofs ; /* reg *//* ★for passing eag offset */
Ull ea12dr ; /* reg *//* for mex(&addr) pointer */
Ull ea03woofs :18; /* reg *//* ★for mex(&addr) feedback */
Ull ea03dr ; /* reg *//* for eag(&addr) pointer */
Ull ea13woofs :18; /* reg *//* ★for mex(&addr) feedback */
Ull ea13dr ; /* reg *//* for eag(&addr) pointer */
Ull ea04_lmask :18; /* wire *//* offset */
Ull ea04_umask : 2; /* wire *//* partition */
Ull ea04woofs_prev:18; /* reg *//* ★for siml-loop only */
Ull ea04woofs :18; /* reg *//* ★for mex(&addr) feedback */
Ull ea04dr :18; /* reg *//* base+mex+ofs */
Ull ea14_lmask :18; /* wire *//* offset */
Ull ea14_umask : 2; /* wire *//* partition */
Ull ea14woofs_prev:18; /* reg *//* ★for siml-loop only */
Ull ea14woofs :18; /* reg *//* ★for mex(&addr) feedback */
Ull ea14dr :18; /* reg *//* base+mex+ofs */
Ull tx[UNIT_WIDTH] ; /* reg */
Ull tx2dr[UNIT_WIDTH]; /* reg */
Ull tx3dr[UNIT_WIDTH]; /* reg */
Ull tx4dr[UNIT_WIDTH]; /* reg */
Ull ranger_ok : 8; /* wire *//* lmring要求がread &ty==4&adr[col]<>lmm_range内 */
Ull rangew_ok : 8; /* wire *//* lmring要求がwrite&ty==4&adr[col]<>lmm_range内 */
Ull lmranger_ok : 8; /* wire *//* lmring要求がread &ty==4&adr[col]<>lmm_range内 */
Ull lmrangew_ok : 8; /* wire *//* lmring要求がwrite&ty==4&adr[col]<>lmm_range内 */
Ull lmlddmqw_ok : 1; /* wire *//* lmring要求がwrite&ty==3&op1[col]==LDDMQ */
Ull lmea0sfma : 1; /* wire *//* sfma+ea0.stbr存在 4サイクルに分けて実行 */
Ull lmea0strq : 1; /* wire *//* ea0.strq存在 4サイクルに分けて実行 */
Ull lmea0strqcol : 2; /* wire *//* ea0.strq_col番号 4サイクルに分けて実行 */
Ull lmring_ea0bsy : 1; /* wire *//* ea0有効 */
Ull lmring_ea1bsy : 1; /* wire *//* ea1有効 */
Ull lmring_ful : 1; /* wire *//* (ful2==3)|(ful1 & (ful2==2)) */
Ull deq_wait : 1; /* wire *//* lmring_ful|(ranger_ok&ea1)|(rangew_ok&ea0)|(lddmqw_ok&col!=j) */
Ull lmring_ful1 : 1; /* 0:rw/ty/co/sq/a/di/dm無効, 1:rw/ty/co/sq/a/di/dm有効 */
struct lmring_tr {
Ull rw : 1; /* 0:read, 1:write */
Ull ty : 3; /* 0:reg/conf, 1:reg/breg, 2:reg/addr, 3:lddmq/tr, 4:lmm, 567:-- */
Ull col : 2; /* logical col# for target lmm */
Ull sq :16; /* sequential # for pipelined DMA */
Ull av : 1; /* address valid */
Ull a :31; /* logical addr reg/lmm */
Ull dm :32; /* <- lmm wdata */
Ull d[UNIT_WIDTH] ; /* <- lmm wdata/rdata */
Ull merge : 8; /* wordwise 0:merge_lmm, 1:pass_lmm */
} lmring_tr; /* reg */
Ull lmco : 2; /* wire *//* -> col# */
Ull lmca :18; /* wire *//* -> ea01dr *//* col#による2bit補正前addr */
Ull lmwm :32; /* wire *//* <- axi */
Ull lmwd[UNIT_WIDTH] ; /* wire *//* <- axi */
Ull lmrd[UNIT_WIDTH] ; /* wire *//* -> axi */
Ull mwmux[UNIT_WIDTH]; /* wire for mw0[] */
struct lmm {
Ull en0 : 1; /* internal reg */
Ull en1 : 1; /* internal reg */
Ull rw0 : 1; /* 0:read, 1:write */
Ull rw1 : 1; /* 0:read,(1:write) */
Ull ma0 :18; /* internal reg addr(32B aligned) */
Ull ma1 :18; /* internal reg addr(32B aligned) */
Ull mm0 :32; /* internal reg mask */
Ull mw0[UNIT_WIDTH]; /* internal reg data */
Ull mr0[UNIT_WIDTH]; /* internal wire data */
Ull mr1[UNIT_WIDTH]; /* internal wire data */
Uchar m[LMEM_SIZE] ; /* local memory */
} lmm;
Ull mr0mux : 2; /* mr0[3-0] -> brs0 */
Ull mr1mux : 2; /* mr1[3-0] -> brs1 */
Ull mr0d ; /* muxed data for BR[0] */
Ull mr1d ; /* muxed data for BR[1] */
Ull mexmr0d_prev ; /* ★for mex */
Ull mexmr0d ; /* ★for mex */
Ull mexmr1d_prev ; /* ★for mex */
Ull mexmr1d ; /* ★for mex */
struct {Ull r[UNIT_WIDTH];} b[2][EMAX_WIDTH]; /* shadow_breg *//* constantは両方にセット */
Ull lmring_ful2 : 2; /* 0:empty, 3:full */
Ull lmring_b_top : 2; /* to be enqueued next */
Ull lmring_b_bot : 2; /* to be dequeued next */
#define LMRING_MUX 8
#define LMRING_BR_BUF 3
struct lmring_br {
Ull rw : 1; /* 0:read, 1:write */
Ull ty : 3; /* 0:reg/conf, 1:reg/breg, 2:reg/addr, 3:lddmq/tr, 4:lmm, 567:-- */
Ull col : 2; /* logical col# for target lmm */
Ull sq :16; /* sequential # for pipelined DMA */
Ull av : 1; /* address valid */
Ull a :31; /* logical addr reg/lmm */
Ull dm :32; /* <- lmm wdata */
Ull d[UNIT_WIDTH] ; /* <- lmm wdata/rdata */
} lmring_br[LMRING_BR_BUF]; /* reg */
} unit[AMAP_DEPTH];
} exring[MAXCORE];
Ull get_tcureg_valid(cid, col) int cid, col;
{
#ifndef IGNORE_LDDMQ_HANDSHAKE
return (emax5[cid].fsm[col].tcureg_valid);
#else
return (0);
#endif
}
put_tcureg_ready(cid, col) int cid, col;
{
#ifndef IGNORE_LDDMQ_HANDSHAKE
emax5[cid].fsm[col].tcureg_ready = 1;
#endif
}
Ull get_tcureg_last(cid, col) int cid, col;
{
#ifndef IGNORE_LDDMQ_HANDSHAKE
return (emax5[cid].fsm[col].tcureg_last);
#else
return (0);
#endif
}
put_tcureg_term(cid, col) int cid, col;
{
#ifndef IGNORE_LDDMQ_HANDSHAKE
emax5[cid].fsm[col].tcureg_term = 1;
#endif
}
Ull get_tcureg(cid, col, n) int cid, col, n;
{
#ifndef IGNORE_LDDMQ_HANDSHAKE
return (emax5[cid].fsm[col].tcureg[n]);
#else
return (0);
#endif
}
emax_lmm_init()
{
int i, j, k;
for (i=0; i<MAXCORE; i++) {
for (j=0; j<EMAX_DEPTH; j++) {
for (k=0; k<LMEM_SIZE; k++)
exring[i].unit[j].lmm.m[k] = 0xff;
}
}
}
/* EMAX6 control */
struct dma_ctrl dma_ctrl; /* body of dma_ctrl */
struct reg_ctrl reg_ctrl; /* body of reg_ctrl */
//application -> emax6_start((Ull*)emax6_conf_x1, (Ull*)emax6_lmmi_x1, (Ull*)emax6_regv_x1);
// -> svc 0xf1
siml_emax6(cid, trace, trace_pipe)
/* core毎にemaxは1つなので,t[cid]を使用 */
/* ただしEMAX6のカスケード接続版IMAXでは，core[0]に全EMAX6を接続. simlの都合上,EMAX_NCHIP <= MAXCORE */
Uint cid; Uint trace, trace_pipe;
{
/*┌─┐ ┌───────────────────┐┌─┐┌───────────────────┐ */
/*│ A│ │awaddr $1 WR/RD-req awaddr││ A││awaddr $1 WR/RD-req awaddr│ */
/*│ R│ │awdata ┌──────────┐awdata││ R││awdata ┌──────────┐awdata│ */
/*│ M│ │araddr │ ┌exring─←─┐ │araddr││ M││araddr │ ┌exring─←─┐ │araddr│ */
/*│─┤$1├─┐ $3│$3│┌┐┌┐┌┐│ │ ┌─┤│ │├─┐ $3│$3│┌┐┌┐┌┐│ │ ┌─┤ */
/*│ I├─┤PD├→─◆─□□□□□□□□┐└→┤PD├─→─┤PD├→─◆─□□□□□□□□┐└→┤PD├→ */
/*│ /│ │IM│SL l├─□□□□□□□□┤ MA│IM││ ││IM│SL l├─□□□□□□□□┤ MA│IM│ */
/*│ O├─┤OA├┐ m├─□□□□□□□□┤ ┌┤OA├─←─┤OA├┐ m├─□□□□□□□□┤ ┌┤OA├← */
/*│─┤$2├─┘│ r├─□□□□□□□□┤ │└─┤│ │├─┘│ r├─□□□□□□□□┤ │└─┤ */
/*│#0│ │ │ i├─□□□□□□□□┤ │ ││#1││ │ i├─□□□□□□□□┤ │ │ */
/*│ │ │ │ n├─□□□□□□□□┤ │ ││ ││ │ n├─□□□□□□□□┤ │ │ */
/*│ │ │ │ g├─□□□□□□□□┤ │ ││ ││ │ g├─□□□□□□□□┤ │ │ */
/*│ │ │ │ └─□□□□□□□□┤ │ ││ ││ │ └─□□□□□□□□┤ │ │ */
/*│ L│ │ │ └┘└┘└┘└┘↓$4│ ││ L││ │ └┘└┘└┘└┘↓$4│ │ */
/*│ 1│ │ └────────←──◆─┘ ││ 1││ └────────←──◆─┘ │ */
/*│ $│ │ardata $4 RD-wait ardata││ $││ardata $4 RD-wait ardata│ */
/*└─┘ └───────────────────┘└─┘└───────────────────┘ */
/* chip#0 | #1 #2 */
/* siml_axi_iorq(cid, trace) c[0].iorq <- axiif[0] $2 | - - */
/* siml_iorq_axi(cid, trace) c[0].iorq -> axiif[0] $1 | - - */
/* for (row) { */
/* siml_unit_lmm(cid, row) */
/* siml_unit_stage5(cid, i) */
/* } */
/* for (row) */
/* siml_unit_stage4_pre(cid, row)*/
/* siml_exring_deq_wait(cid) axiif.exring_deq_wait(axi->lmring) | */
/* for (row) { */
/* siml_unit_stage4(cid, row) bri: axring/lmring切替え */
/* siml_unit_stage3(cid, row) */
/* siml_unit_stage2(cid, row) */
/* siml_unit_stage1(cid, row) */
/* } */
/* siml_lmring_axi(cid, trace) axiif[0] <- lmring[0.term] $4 | lm[1.term] lm[2.term] */
/* siml_axi_lmring(cid, trace) axiif[0] -> axiif[0].axring $3 | */
int i, j, k, row0, prev_stat[EMAX_NCHIP], emax_stat, busy;
Ull a;
Ull steps = t[cid].total_steps;
Ull cycle = t[cid].total_cycle;
#if 1
if (cycle % ARM_EMAX6_RATIO) /* ARM:2.0GHz EMAX6:1.0GHz */
return (0);
#endif
if (cid>=EMAX_NCHIP) { /* EMAX6 is attached on cid=0:EMAX_NCHIP-1 */
if (EMAX_NCHIP > MAXCORE)
printf("EMAX_NCHIP(%d) should be <= MAXCORE(%d)\n", EMAX_NCHIP, MAXCORE);
return (0);
}
/* update LMRING/EXRING */
prev_stat[cid] = c[0].iorq.v_stat || (reg_ctrl.i[cid].stat & 0xffff00ff);
/* ソフトからのstat検査時に(c[cid].iorq.v_stat)を含めると常にbusy */
reg_ctrl.i[cid].stat = ((LMEM_SIZE==131072)?2:(LMEM_SIZE==65536)?1:0)<<12
| ((EMAX_DEPTH==64)?3:(EMAX_DEPTH==32)?2:(EMAX_DEPTH==16)?1:0)<<8
| (!(axiif[cid].axi_arvalid||axiif[cid].axi_awvalid||axiif[cid].axi_wvalid||axiif[cid].reqn)?LMRING_IDLE:LMRING_BUSY)<<4
| (!(exring[cid].cmd_busy||exring[cid].unit_busy)?EXRING_IDLE:EXRING_BUSY);
if (prev_stat[cid] && !c[0].iorq.v_stat && !(reg_ctrl.i[cid].stat & 0xffff00ff))
printf("%03.3d:EE %08.8x_%08.8x cycle=%08.8x_%08.8x ---EMAX6 IO/CMD-END----\n", cid, (Uint)(steps>>32), (Uint)steps, (Uint)(cycle>>32), (Uint)cycle);
#if 1
emax_stat = 0;
for (i=0; i<EMAX_NCHIP; i++) emax_stat |= (reg_ctrl.i[i].stat & 0xffff00ff);
if (!c[0].iorq.v_stat && !emax_stat) return (0);
#endif
if (cid == 0) { /* cid#0のみ */
siml_axi_iorq(cid, trace); /* AXI->IORQ */
siml_iorq_axi(cid, trace); /* IORQ->AXI */
}
/* find top_row */
for (row0=0; row0<EMAX_DEPTH; row0++) /* EXRINGは論理row0からsimlする必要があり,LMRINGも合わせる */
if (exring[cid].unit[row0].l_row == 0) break; /* LMRINGは実際には物理row0がfsmに接続されているが,siml時は論理row0が先頭と考えて問題ない */
/********************************************************/
siml_lmring_axi(cid, trace); /* LMRING->AXI */
/* siml_unit_stage4()の前にLMRING_MUX個のdeq_waitを集約 */
/* なお,全stage5と全stage4を交互にsimlすると,毎サイクルlmringが2stage進むことになる */
/* しかし.lmring_axiは1stageしか処理しないので,性能見積り上の弊害はない 20190828 */
for (i=(row0+EMAX_DEPTH-1)%EMAX_DEPTH;; i=(i+EMAX_DEPTH-1)%EMAX_DEPTH) { /* for each unit */
siml_unit_lmm(cid, i);
siml_unit_stage5(cid, i); /* stage-5 (4DR->BROUT)(LMRING_TR->LMRING_BROUT) */
if (i==row0)
break;
}
for (i=(row0+EMAX_DEPTH-1)%EMAX_DEPTH;; i=(i+EMAX_DEPTH-1)%EMAX_DEPTH) { /* for each unit */
siml_unit_stage4_pre(cid, i);
if (i==row0)
break;
}
siml_exring_deq_wait(cid, trace);
/* siml unit */
for (i=(row0+EMAX_DEPTH-1)%EMAX_DEPTH;; i=(i+EMAX_DEPTH-1)%EMAX_DEPTH) { /* for each unit */
siml_unit_stage4(cid, i); /* stage-4 (3DR->4DR) (LMRING_BRIN->LMRING_TR) */
siml_unit_stage3(cid, i); /* stage-3 (2DR->3DR) */
siml_unit_stage2(cid, i); /* stage-2 (EX/TX->2DR) */
siml_unit_stage1(cid, i); /* stage-1 (BRIN->EX/TX) */
if (i==row0)
break;
}
siml_axi_lmring(cid, trace); /* AXI->LMRING */
/********************************************************/
busy = 0;
for (i=0; i<EMAX_DEPTH; i++) { /* for each unit */
if (exring[cid].unit[i].unit1_exec || exring[cid].unit[i].unit1_fold || exring[cid].unit[i].unit1_stop || exring[cid].unit[i].unit2_exec || exring[cid].unit[i].unit2_fold || exring[cid].unit[i].unit2_stop)
busy = 1;
}
exring[cid].unit_busy = busy;
if (trace && trace_pipe)
show_emax6_status(cid);
#if 0
printf("@@@@ cid=%d c[0].iorq.v_stat=%d arvalid=%d, awvalid=%d, wvalid=%d, reqn=%d, cmd_busy=%d, unit_busy=%d axring_ful2=%d", cid, c[0].iorq.v_stat,
axiif[cid].axi_arvalid, axiif[cid].axi_awvalid, axiif[cid].axi_wvalid, axiif[cid].reqn, exring[cid].cmd_busy, exring[cid].unit_busy, axiif[cid].axring_ful2);
for (i=0; i<EMAX_DEPTH; i++) {
if (i%8==0) printf(" ");
printf("%d%d", exring[cid].unit[i].lmring_ful1, exring[cid].unit[i].lmring_ful2);
}
printf("\n");
#endif
return (0);
}
siml_axi_iorq(cid, trace) Uint cid, trace;
{
/* LMMのcolumnマルチスレッデイングは,EXRINGを優先し,LMRINGは隙間で動作させる */
/* LMRINGは実際には物理row0がfsmに接続されているが,siml時は論理row0が先頭と考えて問題ない */
/* *//* axi_write_busy axi_read_busy */
/* 論理番号 物理番号 V<--------ENQ (siml_axiifが先にENQ) *//* awaddr+awlen+awvalid ^> awready *//* wdata[]+wstrb+wvalid+wlast -> wready->next */
/* axiif.axring_br =======bri_ful2 物理#0のpiはaxringに差し替え *//* araddr+arlen+arvalid -> arready */
/* row0+DEPTH-2 0 | V^--------waiti(unit[0].deq_wait) */
/* unit[].lmring_br ------- 下からsiml.deq_waitが同一τにドミノ倒し. */
/* | 実機と違うがoutputの出方は同じ */
/* row0+DEPTH-1 1 | V ↑ */
/* siml起点(broutは定数) unit[].lmring_br ------- SIML起点(1τ前の次段deq_waitを使う.正常) */
/* row0 62 | V SIML最後(前段brの値が1τ未来になる) */
/* unit[].lmring_br ------- ↑ */
/* row0+1 63 | V */
/* unit[].lmring_br -------bro_ful2 */
/* |^--------waito(axiif.deq_wait) */
/* +-------->DEQ (siml_axiifが先にDEQ) *//* rdata[]+rvalid+rlast -> rready->next */
/* iorq.v_stat : 4; v 0:empty 1:reserve 3:inuse | stat 0:empty 1:busy 3:RD-ok */
/* iorq.tid :12; */
/* iorq.type : 4; type */
/* iorq.opcd : 6; opcd */
/* iorq.ADR ; 以前のADDRに対応 */
/* iorq.BUF[2] ; for load/store */
/* iorq.rob ; for DATA */
/* exring.deq_wait : 1; 0:deq,1:wait */
/* axring_ful2 : 2; 0:empty, 2:ful */
/* axring_br.rw : 1; 0:read, 1:write */
/* axring_br.ty : 3; 0:reg/conf, 1:reg/breg, 2:reg/addr, 3:lddmq/tr, 4:lmm, 567:-- */
/* axring_br.col : 2; logical col# for target lmm */
/* axring_br.sq :16; sequential # for pipelined DMA */
/* axring_br.a :31; logical addr reg/lmm */
/* axring_br.dm :32; <- lmm wdata */
/* axring_br.d[4] ; <- lmm wdata/rdata */
/* read: LMRING終端からの回収 bro->axiif->iorq */
/* HOST:AXIIF->IORQ (ARM-restartにより,iorqに該当エントリがない場合がある) */
/************************************************************************************************************************************************************************************************************/
/* | | | | | | | | | | | | | | | | | | | | | | | */
/* clk _/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/ */
/* iorq.v_stat : 4 *1101===X=0000==========X========1101===========================X=1111 */
/* iorq.tid :12 A */
/* iorq.type : 4 4:write 3:read | */
/* iorq.opcd : 6 2:LD/STRW 3:LD/STR 12:VLD/VSTRQ | */
/* iorq.ADR ===A====== | */
/* iorq.BUF[2] -----<=D=====>--- */
/* iorq.rob */
/* rdata[] SLAVE -----<=D=====>--- */
/* rvalid SLAVE _____/~~~~~~~\___ */
/* rlast SLAVE _____/~~~~~~~\___ */
/* rready MASTER* _____/~~~~~~~\___ */
/************************************************************************************************************************************************************************************************************/
axiif[cid].axi_rready = 1; /* always 1 */
if (axiif[cid].dma_stat == 2) { /* DMA RD active */
if (axiif[cid].mreq <= axiif[cid].mlen) { /* write active */
if (axiif[cid].axi_rvalid && axiif[cid].axi_rready) { /* new read_req starts */
printf("%03.3d:DMA RD adr=%08.8x data=%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x\n",
cid, axiif[cid].madr+axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH,
(Uint)(axiif[cid].axi_rdata[3]>>32), (Uint)axiif[cid].axi_rdata[3],
(Uint)(axiif[cid].axi_rdata[2]>>32), (Uint)axiif[cid].axi_rdata[2],
(Uint)(axiif[cid].axi_rdata[1]>>32), (Uint)axiif[cid].axi_rdata[1],
(Uint)(axiif[cid].axi_rdata[0]>>32), (Uint)axiif[cid].axi_rdata[0]);
if (axiif[cid].mreq == 0) {
if (axiif[cid].fmask&0x01) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 0, 0x00000000ffffffffLL, axiif[cid].axi_rdata[0]);
if (axiif[cid].fmask&0x02) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 0, 0xffffffff00000000LL, axiif[cid].axi_rdata[0]);
if (axiif[cid].fmask&0x04) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 8, 0x00000000ffffffffLL, axiif[cid].axi_rdata[1]);
if (axiif[cid].fmask&0x08) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 8, 0xffffffff00000000LL, axiif[cid].axi_rdata[1]);
if (axiif[cid].fmask&0x10) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 16, 0x00000000ffffffffLL, axiif[cid].axi_rdata[2]);
if (axiif[cid].fmask&0x20) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 16, 0xffffffff00000000LL, axiif[cid].axi_rdata[2]);
if (axiif[cid].fmask&0x40) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 24, 0x00000000ffffffffLL, axiif[cid].axi_rdata[3]);
if (axiif[cid].fmask&0x80) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 24, 0xffffffff00000000LL, axiif[cid].axi_rdata[3]);
}
else if (axiif[cid].mreq == axiif[cid].mlen) {
if (axiif[cid].lmask&0x01) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 0, 0x00000000ffffffffLL, axiif[cid].axi_rdata[0]);
if (axiif[cid].lmask&0x02) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 0, 0xffffffff00000000LL, axiif[cid].axi_rdata[0]);
if (axiif[cid].lmask&0x04) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 8, 0x00000000ffffffffLL, axiif[cid].axi_rdata[1]);
if (axiif[cid].lmask&0x08) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 8, 0xffffffff00000000LL, axiif[cid].axi_rdata[1]);
if (axiif[cid].lmask&0x10) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 16, 0x00000000ffffffffLL, axiif[cid].axi_rdata[2]);
if (axiif[cid].lmask&0x20) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 16, 0xffffffff00000000LL, axiif[cid].axi_rdata[2]);
if (axiif[cid].lmask&0x40) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 24, 0x00000000ffffffffLL, axiif[cid].axi_rdata[3]);
if (axiif[cid].lmask&0x80) mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 24, 0xffffffff00000000LL, axiif[cid].axi_rdata[3]);
}
else {
mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 0, 0xffffffffffffffffLL, axiif[cid].axi_rdata[0]);
mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 8, 0xffffffffffffffffLL, axiif[cid].axi_rdata[1]);
mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 16, 0xffffffffffffffffLL, axiif[cid].axi_rdata[2]);
mmw(axiif[cid].dadr + axiif[cid].mreq*sizeof(Ull)*UNIT_WIDTH + 24, 0xffffffffffffffffLL, axiif[cid].axi_rdata[3]);
}
axiif[cid].mreq++;
}
}
else { /* data完了 */
dma_ctrl.ZDMA_CH_STATUS = (dma_ctrl.ZDMA_CH_STATUS & ~3); /* free */
dma_ctrl.ZDMA_CH_CTRL2 = (dma_ctrl.ZDMA_CH_CTRL2 & ~1); /* free */
axiif[cid].dma_stat = 0; /* reset */
axiif[cid].radr_sent = 0; /* reset */
}
}
if (c[cid].iorq.v_stat == ((3<<2)|1) && c[cid].iorq.type == 3) { /* load *//* emax6_reg()機能は最終的には各担当stageに配置 */
/*emax6_reg(c[cid].iorq.tid, c[cid].iorq.type, c[cid].iorq.opcd, c[cid].iorq.ADR, c[cid].iorq.BUF);*/
if (c[cid].iorq.ADR < REG_BASE2_PHYS) { /* dma space ... 固定位置 (DMA_BASE2_PHYS-REG_BASE2_PHYS) */
switch (c[cid].iorq.opcd) {
case 2:if (c[cid].iorq.ADR & (sizeof(Uint)-1)) printf("%03.3d:emax6_ctl: dma_space load: opcd=%x adr=%08.8x (should be aligned to Uint)\n", c[cid].iorq.tid, c[cid].iorq.opcd, c[cid].iorq.ADR);
else c[cid].iorq.BUF[0] = *(Uint*)((Uchar*)&dma_ctrl+(c[cid].iorq.ADR-DMA_BASE2_PHYS)); break;
case 3:if (c[cid].iorq.ADR & (sizeof(Ull )-1)) printf("%03.3d:emax6_ctl: dma_space load: opcd=%x adr=%08.8x (should be aligned to Ull)\n", c[cid].iorq.tid, c[cid].iorq.opcd, c[cid].iorq.ADR);
else c[cid].iorq.BUF[0] = *(Ull *)((Uchar*)&dma_ctrl+(c[cid].iorq.ADR-DMA_BASE2_PHYS)); break;
default: printf("%03.3d:emax6_ctl: dma_space load: opcd=%x adr=%08.8x (should be LDRW/LDR)\n", c[cid].iorq.tid, c[cid].iorq.opcd, c[cid].iorq.ADR); break; }
c[cid].iorq.v_stat = (c[cid].iorq.v_stat&0xc)|3; /* return to sim-core.c */
if (trace)
printf("%03.3d:PIO->IORQ RD opcd=%d adr=%08.8x data=%08.8x_%08.8x\n", cid, c[cid].iorq.opcd, c[cid].iorq.ADR, (Uint)(c[cid].iorq.BUF[0]>>32), (Uint)c[cid].iorq.BUF[0]);
}
else if (axiif[cid].axi_rvalid && axiif[cid].axi_rready) { /* new read_req starts */
printf("%03.3d:PIO RD adr=%08.8x data=%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x\n",
cid, axiif[cid].sadr,
(Uint)(axiif[cid].axi_rdata[3]>>32), (Uint)axiif[cid].axi_rdata[3],
(Uint)(axiif[cid].axi_rdata[2]>>32), (Uint)axiif[cid].axi_rdata[2],
(Uint)(axiif[cid].axi_rdata[1]>>32), (Uint)axiif[cid].axi_rdata[1],
(Uint)(axiif[cid].axi_rdata[0]>>32), (Uint)axiif[cid].axi_rdata[0]);
switch (c[cid].iorq.opcd) { /* 2:LD/STRW 3:LD/STR 12:VLD/VSTRQ */
case 2: /* 32bit */
switch (c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull))) {
case 0: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[0]>>((c[cid].iorq.ADR & sizeof(int))*8); break;
case 8: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[1]>>((c[cid].iorq.ADR & sizeof(int))*8); break;
case 16: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[2]>>((c[cid].iorq.ADR & sizeof(int))*8); break;
case 24: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[3]>>((c[cid].iorq.ADR & sizeof(int))*8); break;
}
break;
case 3: /* 64bit */
switch (c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull))) {
case 0: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[0]; break;
case 8: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[1]; break;
case 16: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[2]; break;
case 24: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[3]; break;
}
break;
case 12: /* 128bit */
switch (c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull))) {
case 0: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[0];
c[cid].iorq.BUF[1] = axiif[cid].axi_rdata[1]; break;
case 16: c[cid].iorq.BUF[0] = axiif[cid].axi_rdata[2];
c[cid].iorq.BUF[1] = axiif[cid].axi_rdata[3]; break;
}
break;
}
c[cid].iorq.v_stat = (c[cid].iorq.v_stat&0xc)|3; /* return to sim-core.c */
axiif[cid].radr_sent = 0;
if (trace)
printf("%03.3d:AXIIF->IORQ RD opcd=%d adr=%08.8x data=%08.8x%08.8x_%08.8x%08.8x\n", cid, c[cid].iorq.opcd, c[cid].iorq.ADR,
(Uint)(c[cid].iorq.BUF[1]>>32), (Uint)c[cid].iorq.BUF[1],
(Uint)(c[cid].iorq.BUF[0]>>32), (Uint)c[cid].iorq.BUF[0]);
}
}
return (0);
}
siml_iorq_axi(cid, trace) Uint cid, trace;
{
int i, k;
/* read/write LMRING先端への投入 iorq->axiif->bri */
/* HOST:IORQ->AXIIF (ARM-restartにより,iorqに該当エントリがない場合がある) */
/************************************************************************************************************************************************************************************************************/
/* | | | | | | | | | | | | | | | | | | | | | | | */
/* clk _/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/ */
/* iorq.v_stat : 4 *1101===X=0000==========X========1101===========================X=1111 */
/* iorq.tid :12 */
/* iorq.type : 4 4:write 3:read */
/* iorq.opcd : 6 2:LD/STRW 3:LD/STR 12:VLD/VSTRQ */
/* iorq.ADR ===A====== ===A====== */
/* iorq.BUF[2] ===D====== */
/* iorq.rob */
/* awaddr MASTER* -----<=A=====>--- */
/* awlen MASTER* -----<=0=====>--- */
/* awvalid MASTER* _____/~~~~~~~\___ valid=1 */
/* awready SLAVE ~~~~~~~~~~~~~\___ ready=1時に授受 */
/* wstrb MASTER* -----<=M=====>--- */
/* wdata[] MASTER* -----<=D=====>--- */
/* wvalid MASTER* _____/~~~~~~~\___ */
/* wlast MASTER* _____/~~~~~~~\___ PIOの場合,常に1 */
/* wready SLAVE ~~~~~~~~~~~~~\___ */
/* araddr MASTER* -----<=A=====>--- */
/* arlen MASTER* -----<=0=====>--- */
/* arvalid MASTER* _____/~~~~~~~\___ */
/* arready SLAVE ~~~~~~~~~~~~~\___ */
/************************************************************************************************************************************************************************************************************/
if ((exring[cid].cycle&3) == 3 && (reg_ctrl.i[cid].cmd&3) == CMD_RESET) {
axiif[cid].dma_stat = 0;
axiif[cid].wadr_sent = 0;
axiif[cid].radr_sent = 0;
axiif[cid].dadr = 0;
axiif[cid].madr = 0;
axiif[cid].mlen = 0;
axiif[cid].mreq = 0;
axiif[cid].fmask = 0;
axiif[cid].lmask = 0;
}
if (axiif[cid].dma_stat == 3) { /* DMA WR active */
if (!axiif[cid].wadr_sent) {
if (!axiif[cid].axi_awvalid) {
axiif[cid].axi_awaddr = axiif[cid].madr;
axiif[cid].axi_awlen = axiif[cid].mlen;
axiif[cid].axi_awvalid = 1; /* on */
printf("%03.3d:DMA WR start ddradr=%08.8x lmmadr=%08.8x len=%04.4x\n",
cid, axiif[cid].dadr, axiif[cid].madr, axiif[cid].mlen);
}
else if (axiif[cid].axi_awready) { /* adr完了 */
axiif[cid].wadr_sent = 1; /* fin */
/*axiif[cid].mreq = 0; *//* length */
axiif[cid].axi_awvalid = 0; /* off */
}
}
else if (axiif[cid].mreq <= axiif[cid].mlen) { /* write active */
if (axiif[cid].mreq == 0)
axiif[cid].axi_wstrb = ((axiif[cid].fmask&0x80)?0xf0000000:0)
| ((axiif[cid].fmask&0x40)?0x0f000000:0)
| ((axiif[cid].fmask&0x20)?0x00f00000:0)
| ((axiif[cid].fmask&0x10)?0x000f0000:0)
| ((axiif[cid].fmask&0x08)?0x0000f000:0)
| ((axiif[cid].fmask&0x04)?0x00000f00:0)
| ((axiif[cid].fmask&0x02)?0x000000f0:0)
| ((axiif[cid].fmask&0x01)?0x0000000f:0);
else if (axiif[cid].mreq == axiif[cid].mlen)
axiif[cid].axi_wstrb = ((axiif[cid].lmask&0x80)?0xf0000000:0)
| ((axiif[cid].lmask&0x40)?0x0f000000:0)
| ((axiif[cid].lmask&0x20)?0x00f00000:0)
| ((axiif[cid].lmask&0x10)?0x000f0000:0)
| ((axiif[cid].lmask&0x08)?0x0000f000:0)
| ((axiif[cid].lmask&0x04)?0x00000f00:0)
| ((axiif[cid].lmask&0x02)?0x000000f0:0)
| ((axiif[cid].lmask&0x01)?0x0000000f:0);
else
axiif[cid].axi_wstrb = 0xffffffff;
axiif[cid].axi_wdata[0] = mmr(axiif[cid].dadr );
axiif[cid].axi_wdata[1] = mmr(axiif[cid].dadr|(sizeof(Ull)*1));
axiif[cid].axi_wdata[2] = mmr(axiif[cid].dadr|(sizeof(Ull)*2));
axiif[cid].axi_wdata[3] = mmr(axiif[cid].dadr|(sizeof(Ull)*3));
axiif[cid].axi_wvalid = 1; /* on */
if (axiif[cid].mreq == axiif[cid].mlen)
axiif[cid].axi_wlast = 1; /* on */
else
axiif[cid].axi_wlast = 0; /* off */
if (axiif[cid].axi_wready) { /* prepare next write */
printf("%03.3d:DMA WR mreq=%d last=%x wstrb=%08.8x data=%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x\n",
cid, axiif[cid].mreq, axiif[cid].axi_wlast, axiif[cid].axi_wstrb,
(Uint)(axiif[cid].axi_wdata[3]>>32), (Uint)axiif[cid].axi_wdata[3],
(Uint)(axiif[cid].axi_wdata[2]>>32), (Uint)axiif[cid].axi_wdata[2],
(Uint)(axiif[cid].axi_wdata[1]>>32), (Uint)axiif[cid].axi_wdata[1],
(Uint)(axiif[cid].axi_wdata[0]>>32), (Uint)axiif[cid].axi_wdata[0]);
axiif[cid].dadr+=sizeof(Ull)*UNIT_WIDTH;
axiif[cid].mreq++;
}
}
else { /* data完了 */
printf("%03.3d:DMA WR FIN\n", cid);
dma_ctrl.ZDMA_CH_STATUS = (dma_ctrl.ZDMA_CH_STATUS & ~3); /* free */
dma_ctrl.ZDMA_CH_CTRL2 = (dma_ctrl.ZDMA_CH_CTRL2 & ~1); /* free */
axiif[cid].dma_stat = 0; /* reset */
axiif[cid].wadr_sent = 0; /* reset */
axiif[cid].axi_wvalid = 0; /* off */
axiif[cid].axi_wlast = 0; /* off */
}
}
if (axiif[cid].dma_stat == 2) { /* DMA RD active */
if (!axiif[cid].radr_sent) {
if (!axiif[cid].axi_arvalid) {
axiif[cid].axi_araddr = axiif[cid].madr;
axiif[cid].axi_arlen = axiif[cid].mlen;
axiif[cid].axi_arvalid = 1; /* on */
printf("%03.3d:DMA RD start lmmadr=%08.8x ddradr=%08.8x len=%04.4x\n",
cid, axiif[cid].madr, axiif[cid].dadr, axiif[cid].mlen);
}
else if (axiif[cid].axi_arready) { /* adr完了 */
axiif[cid].radr_sent = 1; /* fin */
/*axiif[cid].mreq = 0; *//* length */
axiif[cid].axi_arvalid = 0; /* off */
}
}
}
if (c[cid].iorq.v_stat == ((3<<2)|1) && c[cid].iorq.type == 4) { /* store *//* emax6_reg()機能は最終的には各担当stageに配置 */
/*emax6_reg(c[cid].iorq.tid, c[cid].iorq.type, c[cid].iorq.opcd, c[cid].iorq.ADR, c[cid].iorq.BUF);*/
if (c[cid].iorq.ADR < REG_BASE2_PHYS) { /* dma space ... 固定位置 (DMA_BASE2_PHYS-REG_BASE2_PHYS) */
switch (c[cid].iorq.opcd) {
case 2:if (c[cid].iorq.ADR & (sizeof(Uint)-1)) printf("%03.3d:emax6_ctl: dma_space store: opcd=%x adr=%08.8x (should be aligned to Uint)\n", c[cid].iorq.tid, c[cid].iorq.opcd, c[cid].iorq.ADR);
else *(Uint*)((Uchar*)&dma_ctrl+(c[cid].iorq.ADR-DMA_BASE2_PHYS)) = c[cid].iorq.BUF[0]; break;
case 3:if (c[cid].iorq.ADR & (sizeof(Ull )-1)) printf("%03.3d:emax6_ctl: dma_space store: opcd=%x adr=%08.8x (should be aligned to Ull)\n", c[cid].iorq.tid, c[cid].iorq.opcd, c[cid].iorq.ADR);
else *(Ull *)((Uchar*)&dma_ctrl+(c[cid].iorq.ADR-DMA_BASE2_PHYS)) = c[cid].iorq.BUF[0]; break;
default: printf("%03.3d:emax6_ctl: dma_space store: opcd=%x adr=%08.8x (should be STRW/STR)\n", c[cid].iorq.tid, c[cid].iorq.opcd, c[cid].iorq.ADR); break; }
c[cid].iorq.v_stat = 0; /* immediately finished */
if (trace)
printf("%03.3d:IORQ->PIO WR opcd=%d adr=%08.8x data=%08.8x_%08.8x\n", cid, c[cid].iorq.opcd, c[cid].iorq.ADR, (Uint)(c[cid].iorq.BUF[0]>>32), (Uint)c[cid].iorq.BUF[0]);
if ((dma_ctrl.ZDMA_CH_STATUS&3) != 2 && (dma_ctrl.ZDMA_CH_CTRL2 & 1)) {
dma_ctrl.ZDMA_CH_STATUS = (dma_ctrl.ZDMA_CH_STATUS & ~3) | 2; /* busy */
if (dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0 < LMM_BASE2_PHYS) { /* mem->lmm */
axiif[cid].dma_stat = 3; /* write */
axiif[cid].dadr = dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0 & ~(sizeof(Ull)*UNIT_WIDTH-1); /* mem addr */
axiif[cid].madr = dma_ctrl.ZDMA_CH_DST_DSCR_WORD0 & ~(sizeof(Ull)*UNIT_WIDTH-1); /* lmm addr */
axiif[cid].mlen = ((dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint)+dma_ctrl.ZDMA_CH_SRC_DSCR_WORD2/sizeof(Uint)-1)/(UNIT_WIDTH*2))
- ((dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint) )/(UNIT_WIDTH*2)); /* 0:1cycle, 1:2cycle */
axiif[cid].mreq = 0;
axiif[cid].fmask = 0xff << ( (dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint) ) & (UNIT_WIDTH*2-1));
axiif[cid].lmask = 0xff >> (~(dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint)+dma_ctrl.ZDMA_CH_SRC_DSCR_WORD2/sizeof(Uint)-1) & (UNIT_WIDTH*2-1));
if (axiif[cid].mlen==0) {
axiif[cid].fmask &= axiif[cid].lmask;
axiif[cid].lmask &= axiif[cid].fmask;
}
printf("%03.3d:DMA WR src=%08.8x dst=%08.8x len=%04.4x\n", cid,
axiif[cid].dadr, axiif[cid].madr, axiif[cid].mlen);
}
else { /* lmm->mem */
axiif[cid].dma_stat = 2; /* read */
axiif[cid].dadr = dma_ctrl.ZDMA_CH_DST_DSCR_WORD0 & ~(sizeof(Ull)*UNIT_WIDTH-1); /* mem addr */
axiif[cid].madr = dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0 & ~(sizeof(Ull)*UNIT_WIDTH-1); /* lmm addr */
axiif[cid].mlen = ((dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint)+dma_ctrl.ZDMA_CH_SRC_DSCR_WORD2/sizeof(Uint)-1)/(UNIT_WIDTH*2))
- ((dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint) )/(UNIT_WIDTH*2)); /* 0:1cycle, 1:2cycle */
axiif[cid].mreq = 0;
axiif[cid].fmask = 0xff << ( (dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint) ) & (UNIT_WIDTH*2-1));
axiif[cid].lmask = 0xff >> (~(dma_ctrl.ZDMA_CH_SRC_DSCR_WORD0/sizeof(Uint)+dma_ctrl.ZDMA_CH_SRC_DSCR_WORD2/sizeof(Uint)-1) & (UNIT_WIDTH*2-1));
if (axiif[cid].mlen==0) {
axiif[cid].fmask &= axiif[cid].lmask;
axiif[cid].lmask &= axiif[cid].fmask;
}
printf("%03.3d:DMA RD src=%08.8x dst=%08.8x len=%04.4x\n", cid,
axiif[cid].madr, axiif[cid].dadr, axiif[cid].mlen);
}
}
}
else if (!axiif[cid].dma_stat) { /* DMA is inactive */
if (!axiif[cid].wadr_sent) {
if (!axiif[cid].axi_awvalid) {
axiif[cid].axi_awaddr = c[cid].iorq.ADR & ~(sizeof(Ull)*UNIT_WIDTH-1);
axiif[cid].axi_awlen = 0;
axiif[cid].axi_awvalid = 1; /* on */
if (trace)
printf("%03.3d:IORQ->AXIIF WR opcd=%x adr=%08.8x\n",
cid, c[cid].iorq.opcd, (Uint)axiif[cid].axi_awaddr);
}
else if (axiif[cid].axi_awready) { /* adr完了 */
axiif[cid].wadr_sent = 1; /* fin */
axiif[cid].mreq = 0; /* length */
axiif[cid].axi_awvalid = 0; /* off */
}
}
else if (axiif[cid].mreq <= 0) { /* write active */
switch (c[cid].iorq.opcd) { /* 2:LD/STRW 3:LD/STR 12:VLD/VSTRQ */
case 2: /* 32bit */
axiif[cid].axi_wstrb = ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))== 0 ? 0x0000000f<<(c[cid].iorq.ADR&sizeof(int)) : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))== 8 ? 0x00000f00<<(c[cid].iorq.ADR&sizeof(int)) : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))==16 ? 0x000f0000<<(c[cid].iorq.ADR&sizeof(int)) : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))==24 ? 0x0f000000<<(c[cid].iorq.ADR&sizeof(int)) : 0x00000000);
axiif[cid].axi_wdata[0] = c[cid].iorq.BUF[0]<<(c[cid].iorq.ADR & sizeof(int))*8;
axiif[cid].axi_wdata[1] = c[cid].iorq.BUF[0]<<(c[cid].iorq.ADR & sizeof(int))*8;
axiif[cid].axi_wdata[2] = c[cid].iorq.BUF[0]<<(c[cid].iorq.ADR & sizeof(int))*8;
axiif[cid].axi_wdata[3] = c[cid].iorq.BUF[0]<<(c[cid].iorq.ADR & sizeof(int))*8;
break;
case 3: /* 64bit */
axiif[cid].axi_wstrb = ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))== 0 ? 0x000000ff : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))== 8 ? 0x0000ff00 : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))==16 ? 0x00ff0000 : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))==24 ? 0xff000000 : 0x00000000);
axiif[cid].axi_wdata[0] = c[cid].iorq.BUF[0];
axiif[cid].axi_wdata[1] = c[cid].iorq.BUF[0];
axiif[cid].axi_wdata[2] = c[cid].iorq.BUF[0];
axiif[cid].axi_wdata[3] = c[cid].iorq.BUF[0];
break;
case 12: /* 128bit */
axiif[cid].axi_wstrb = ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))== 0 ? 0x0000ffff : 0x00000000)
| ((c[cid].iorq.ADR&((UNIT_WIDTH-1)*sizeof(Ull)))==16 ? 0xffff0000 : 0x00000000);
axiif[cid].axi_wdata[0] = c[cid].iorq.BUF[0];
axiif[cid].axi_wdata[1] = c[cid].iorq.BUF[1];
axiif[cid].axi_wdata[2] = c[cid].iorq.BUF[0];
axiif[cid].axi_wdata[3] = c[cid].iorq.BUF[1];
break;
}
axiif[cid].axi_wvalid = 1; /* on */
if (axiif[cid].mreq == 0)
axiif[cid].axi_wlast = 1; /* on */
else
axiif[cid].axi_wlast = 0; /* off */
printf("%03.3d:PIO WR adr=%08.8x msk=%08.8x data=%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x_%08.8x%08.8x\n",
cid, (Uint)axiif[cid].axi_awaddr, axiif[cid].axi_wstrb,
(Uint)(axiif[cid].axi_wdata[3]>>32), (Uint)axiif[cid].axi_wdata[3],
(Uint)(axiif[cid].axi_wdata[2]>>32), (Uint)axiif[cid].axi_wdata[2],
(Uint)(axiif[cid].axi_wdata[1]>>32), (Uint)axiif[cid].axi_wdata[1],
(Uint)(axiif[cid].axi_wdata[0]>>32), (Uint)axiif[cid].axi_wdata[0]);
if (axiif[cid].axi_wready) { /* data完了 */
axiif[cid].mreq++;
}
}
else {
c[cid].iorq.v_stat = 0; /* immediately finished */
axiif[cid].wadr_sent = 0; /* reset */
axiif[cid].axi_wvalid = 0; /* off */
axiif[cid].axi_wlast = 0; /* off */
}
}
}
if (c[cid].iorq.v_stat == ((3<<2)|1) && c[cid].iorq.type == 3) { /* load *//* emax6_reg()機能は最終的には各担当stageに配置 */
/*emax6_reg(c[cid].iorq.tid, c[cid].iorq.type, c[cid].iorq.opcd, c[cid].iorq.ADR, c[cid].iorq.BUF);*/
if (c[cid].iorq.ADR < REG_BASE2_PHYS) { /* dma space ... 固定位置 (DMA_BASE2_PHYS-REG_BASE2_PHYS) */
}
else if (!axiif[cid].dma_stat) { /* DMA is inactive */
if (!axiif[cid].radr_sent) {
if (!axiif[cid].axi_arvalid) {
axiif[cid].axi_araddr = c[cid].iorq.ADR & ~(sizeof(Ull)*UNIT_WIDTH-1); /* 全dword読み出し */
axiif[cid].axi_arlen = 0;
axiif[cid].axi_arvalid = 1; /* on */
if (trace)
printf("%03.3d:IORQ->AXIIF AR opcd=%x adr=%08.8x\n",
cid, c[cid].iorq.opcd, (Uint)axiif[cid].axi_araddr);
}
else if (axiif[cid].axi_arready) { /* adr完了 */
axiif[cid].radr_sent = 1;
axiif[cid].mreq = 0; /* length */
axiif[cid].axi_arvalid = 0; /* off */
}
}
}
}
return (0);
}
siml_exring_deq_wait(cid, trace) Uint cid, trace;
{
int i;
/* axiifw側の準備 */
/* 先頭のexring.deq_waitを集めておき,siml_stage4()の前にaxiif[cid].exring_deq_waitを確定 */
axiif[cid].exring_deq_wait=0;
for (i=0; i<LMRING_MUX; i++)
axiif[cid].exring_deq_wait |= exring[cid].unit[EMAX_DEPTH/LMRING_MUX*i].deq_wait;/* top deq_wait */
}
siml_lmring_axi(cid, trace) Uint cid, trace;
{
/* LMMのcolumnマルチスレッデイングは,EXRINGを優先し,LMRINGは隙間で動作させる */
/* LMRINGは実際には物理row0がfsmに接続されているが,siml時は論理row0が先頭と考えて問題ない */
/* *//* axi_write_busy axi_read_busy */
/* 論理番号 物理番号 V<--------ENQ (siml_axiifが先にENQ) *//* awaddr+awlen+awvalid ^> awready *//* wdata[]+wstrb+wvalid+wlast -> wready->next */
/* axiif.axring_br =======bri_ful2 物理#0のpiはaxringに差し替え *//* araddr+arlen+arvalid -> arready */
/* row0+DEPTH-2 0 | V^--------waiti(unit[0].deq_wait) */
/* unit[].lmring_br ------- 下からsiml.deq_waitが同一τにドミノ倒し. */
/* | 実機と違うがoutputの出方は同じ */
/* row0+DEPTH-1 1 | V ↑ */
/* siml起点(broutは定数) unit[].lmring_br ------- SIML起点(1τ前の次段deq_waitを使う.正常) */
/* row0 62 | V SIML最後(前段brの値が1τ未来になる) */
/* unit[].lmring_br ------- ↑ */
/* row0+1 63 | V */
/* unit[].lmring_br -------bro_ful2 */
/* |^--------waito(axiif.deq_wait) */
/* +-------->DEQ (siml_axiifが先にDEQ) *//* rdata[]+rvalid+rlast -> rready->next */
/* exring.deq_wait : 1; 0:deq,1:wait */
/* axring_ful2 : 2; 0:empty, 2:ful */
/* axring_br.rw : 1; 0:read, 1:write */
/* axring_br.ty : 3; 0:reg/conf, 1:reg/breg, 2:reg/addr, 3:lddmq/tr, 4:lmm, 567:-- */
/* axring_br.col : 2; logical col# for target lmm */
/* axring_br.sq :16; sequential # for pipelined DMA */
/* axring_br.a :31; logical addr reg/lmm */
/* axring_br.dm :32; <- lmm wdata */
/* axring_br.d[4] ; <- lmm wdata/rdata */
/* axiif.deq_wait : 1; 0:deq,1:wait */
/* lmring_ful2 : 2; 0:empty, 3:ful */
/* lmring_br.rw : 1; 0:read, 1:write */
/* lmring_br.ty : 3; 0:reg/conf, 1:reg/breg, 2:reg/addr, 3:lddmq/tr, 4:lmm, 567:-- */
/* lmring_br.col : 2; logical col# for target lmm */
/* lmring_br.sq :16; sequential # for pipelined DMA */
/* lmring_br.a :31; logical addr reg/lmm */
/* lmring_br.dm :32; <- lmm wdata */
/* lmring_br.d[4] ; <- lmm wdata/rdata */
int i, k;
int bro_ful2, bro_av;
struct lmring_br *bro[LMRING_MUX]; /* wire */
for (i=0, bro_ful2=1, bro_av=0; i<LMRING_MUX; i++) {
bro_ful2 &= (exring[cid].unit[EMAX_DEPTH/LMRING_MUX*(i+1)-1].lmring_ful2 > 0);
bro[i] = &exring[cid].unit[EMAX_DEPTH/LMRING_MUX*(i+1)-1].lmring_br[exring[cid].unit[EMAX_DEPTH/LMRING_MUX*(i+1)-1].lmring_b_bot]; /* AXI<-EMAX側 */
bro_av |= bro[i]->av;
}
/* read: LMRING終端からの回収 bro->axiif->iorq */
/* EMAX:BRO->AXIIF */
/************************************************************************************************************************************************************************************************************/
/* | | | | | | | | | | | | | | | | | | | | | | | */
/* clk _/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/~~~\___/ */
/* bro_ful2 0:emp,3:ful 0_/~1~~~~~\ */
/* bro.rw 0:rd.1:wr --<=0=====>- */
/* bro.ty 0:reg,4:lmm --<=*=====>- */
/* bro.col : 2 reg_ctrl.csel */
/* bro.sq : 16 --<=0=====>- */
/* bro.av : 1 --<=0=====>- */
/* bro.a : 31 --<=A=====>- */
/* bro.dm : 32 ------------ */
/* bro.d[4] :256 --<=D=====>- */
/* axiif_reqn _____/~~~~~~~~~~~ */
/* axiif_srw -----<=1=====>--- -----<=0=====>--- */
/* axiif_sadr -----<=A=====>--- -----<=A=====>--- */
/* axiif_sreq -----<=0=====>--- -----<=0=====>--- */
/* rdata[] SLAVE* -----<=D=====>--- */
/* rvalid SLAVE* _____/~~~~~~~\___ */
/* rlast SLAVE* _____/~~~~~~~\___ */
/* rready MASTER ~~~~~~~~~~~~~~~~~ */
/************************************************************************************************************************************************************************************************************/
/* 以下,cid<(EMAX_NCHIP-1)の場合,次段IMAXが存在 */
/*┌─┐ ┌───────────────────┐┌─┐┌───────────────────┐ */
/*│ │ │ ┌──────────┐ ││ ││ ┌──────────┐ │ */
/*│─┤$1├─┐ $3│$3 │ ┌─┤│ │├─┐ $3│$3 │ ┌─┤ */
/*│ I├─┤PD├→─◇─┌──────┐┐└→┤PD├─→─┤PD├→─◇─┌──────┐┐└→┤PD├→ */
/*│ O├─┤OA├┐ ├─│ │┤ ┌┤OA├─←─┤OA├┐ ├─│ │┤ ┌┤OA├← */
/*│─┤$2├─┘│ ├─│ │┤ │└─┤│ │├─┘│ ├─│ │┤ │└─┤ */
/*│ │ │ │ └─└──────┘┤ │ ││ ││ │ └─└──────┘┤ │ │ */
/*│ │ │ │ ↓$4│ ││ ││ │ ↓$4│ │ */
/*│ │ │ └────────←──◆─┘ ││ ││ └────────←──◆─┘ │ */
/*└─┘ └───────────────────┘└─┘└───────────────────┘ */
/* | IMAX[cid] | IMAX[cid+1] */
/* rready> | <rvalid <deq_wait bro+rw rready> | <rvalid <deq_wait */
/* x | <0 <1 0x 0> | x ... do nothing */
/* x | <0 <0 11 0> | x ... deq bro */
/* 0 | <0 <1 10 0> | x ... wait for left-rready */
/* | | */
/* 1 | <0 <1 10 0> | 0 ... ↓へ遷移 */
/* 1 | <0 <1 10 1> | 0 ... wait for right-rready */
/* 1 | <1 <0 10 1> | 1 ... deq bro */
if (bro_ful2 && bro[0]->rw==1) { /* WRは無条件にdequeue */
/* writeの場合,UNIT毎にreqn復帰.後段を待たない */
axiif[cid].deq_wait = 0; /* 上流axiによるdeq-OK */
axiif[cid].reqn--;
axiif[cid].axi_rvalid = 0; /* 上流axiはread不可 */
if (cid < EMAX_NCHIP-1)
axiif[cid+1].axi_rready = 0; /* 下流axiからの受取不可 */
if (!bro_av)
printf("%03.3d:BRO WR no unit covers ty=%x adr=%08.8x(%08.8x) (maybe out-of-order/speculative load)\n", cid, bro[0]->ty, bro[0]->a, bro[0]->a-reg_ctrl.i[cid].adtr);
if (trace)
printf("%03.3d:BRO->AXIIF WR reqn--=%d ty=%x adr=%08.8x dm=%08.8x\n",
cid, axiif[cid].reqn, bro[0]->ty, bro[0]->a, bro[0]->dm);
}
else if (bro_ful2 && bro[0]->rw==0) { /* lmringにRD要求有り */
/* readの場合,後段を待ち,結果merge axiif[cid+1].axi_rdata[UNIT_WIDTH] */
/* axiif[cid+1].axi_rvalid */