From 6a834beec95503261eefd8668f30226cab804413 Mon Sep 17 00:00:00 2001 From: Tu Nguyen Van Date: Thu, 12 Sep 2024 09:21:10 +0700 Subject: [PATCH] s32: mcux: s32z270: add support dspi over mcux drivers add support dspi over mcux drivers Signed-off-by: Tu Nguyen Van --- s32/mcux/devices/S32Z270/S32Z270_device.h | 820 +++++++++++++++++++ s32/mcux/devices/S32Z270/S32Z270_features.h | 29 + s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h | 12 + 3 files changed, 861 insertions(+) diff --git a/s32/mcux/devices/S32Z270/S32Z270_device.h b/s32/mcux/devices/S32Z270/S32Z270_device.h index bb8c5b4c5..578e0f1ea 100644 --- a/s32/mcux/devices/S32Z270/S32Z270_device.h +++ b/s32/mcux/devices/S32Z270/S32Z270_device.h @@ -1865,4 +1865,824 @@ typedef struct { /* The count of CAN_ERFFEL */ #define CAN_ERFFEL_COUNT (128U) +/* ---------------------------------------------------------------------------- + -- DSPI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSPI_Peripheral_Access_Layer DSPI Peripheral Access Layer + * @{ + */ + +/** DSPI - Register Layout Typedef */ + +typedef struct { + __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ + uint8_t RESERVED_0[4]; + __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ + union { /* offset: 0xC */ + __IO uint32_t CTAR[6]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ + }; + uint8_t RESERVED_1[8]; + __IO uint32_t SR; /**< Status Register, offset: 0x2C */ + __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ + union { /* offset: 0x34 */ + __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ + }; + __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ + __I uint32_t TXFR[16]; /**< Transmit FIFO Registers, array offset: 0x3C, array step: 0x4 */ + __I uint32_t RXFR[16]; /**< Receive FIFO Registers, array offset: 0x7C, array step: 0x4 */ + __IO uint32_t DSICR0; /**< DSI Configuration Register 0, offset: 0xBC */ + __I uint32_t SDR0; /**< DSI Serialization Data Register 0, offset: 0xC0 */ + __IO uint32_t ASDR0; /**< DSI Alternate Serialization Data Register 0, offset: 0xC4 */ + __I uint32_t COMPR0; /**< DSI Transmit Comparison Register 0, offset: 0xC8 */ + __I uint32_t DDR0; /**< DSI Deserialization Data Register 0, offset: 0xCC */ + __IO uint32_t DSICR1; /**< DSI Configuration Register 1, offset: 0xD0 */ + __IO uint32_t SSR0; /**< DSI Serialization Source Select Register 0, offset: 0xD4 */ + uint8_t RESERVED_2[16]; + __IO uint32_t DIMR0; /**< DSI Deserialized Data Interrupt Mask Register 0, offset: 0xE8 */ + __IO uint32_t DPIR0; /**< DSI Deserialized Data Polarity Interrupt Register 0, offset: 0xEC */ + __I uint32_t SDR1; /**< DSI Serialization Data Register 1, offset: 0xF0 */ + __IO uint32_t ASDR1; /**< DSI Alternate Serialization Data Register 1, offset: 0xF4 */ + __I uint32_t COMPR1; /**< DSI Transmit Comparison Register 1, offset: 0xF8 */ + __I uint32_t DDR1; /**< DSI Deserialization Data Register 1, offset: 0xFC */ + __IO uint32_t SSR1; /**< DSI Serialization Source Select Register 1, offset: 0x100 */ + uint8_t RESERVED_3[16]; + __IO uint32_t DIMR1; /**< DSI Deserialized Data Interrupt Mask Register 1, offset: 0x114 */ + __IO uint32_t DPIR1; /**< DSI Deserialized Data Polarity Interrupt Register 1, offset: 0x118 */ + __IO uint32_t CTARE[6]; /**< Clock and Transfer Attributes Register Extended, array offset: 0x11C, array step: 0x4 */ + uint8_t RESERVED_4[8]; + __I uint32_t SREX; /**< Status Register Extended, offset: 0x13C */ + uint8_t RESERVED_5[16]; + __IO uint32_t TSL; /**< Time Slot Length Register, offset: 0x150 */ + __IO uint32_t TS_CONF; /**< Time Slot Configuration Register, offset: 0x154 */ +} SPI_Type; + + +/* ---------------------------------------------------------------------------- + -- DSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSPI_Register_Masks DSPI Register Masks + * @{ + */ + +/*! @name MCR - Module Configuration Register */ +/*! @{ */ + +#define SPI_MCR_HALT_MASK DSPI_MCR_HALT_MASK +#define SPI_MCR_HALT_SHIFT DSPI_MCR_HALT_SHIFT +#define SPI_MCR_HALT_WIDTH DSPI_MCR_HALT_WIDTH +#define SPI_MCR_HALT(x) DSPI_MCR_HALT(x) + +#define SPI_MCR_PES_MASK DSPI_MCR_PES_MASK +#define SPI_MCR_PES_SHIFT DSPI_MCR_PES_SHIFT +#define SPI_MCR_PES_WIDTH DSPI_MCR_PES_WIDTH +#define SPI_MCR_PES(x) DSPI_MCR_PES(x) + +#define SPI_MCR_FCPCS_MASK DSPI_MCR_FCPCS_MASK +#define SPI_MCR_FCPCS_SHIFT DSPI_MCR_FCPCS_SHIFT +#define SPI_MCR_FCPCS_WIDTH DSPI_MCR_FCPCS_WIDTH +#define SPI_MCR_FCPCS(x) DSPI_MCR_FCPCS(x) + +#define SPI_MCR_XSPI_MASK DSPI_MCR_XSPI_MASK +#define SPI_MCR_XSPI_SHIFT DSPI_MCR_XSPI_SHIFT +#define SPI_MCR_XSPI_WIDTH DSPI_MCR_XSPI_WIDTH +#define SPI_MCR_XSPI(x) DSPI_MCR_XSPI(x) + +#define SPI_MCR_SMPL_PT_MASK DSPI_MCR_SMPL_PT_MASK +#define SPI_MCR_SMPL_PT_SHIFT DSPI_MCR_SMPL_PT_SHIFT +#define SPI_MCR_SMPL_PT_WIDTH DSPI_MCR_SMPL_PT_WIDTH +#define SPI_MCR_SMPL_PT(x) DSPI_MCR_SMPL_PT(x) + +#define SPI_MCR_CLR_RXF_MASK DSPI_MCR_CLR_RXF_MASK +#define SPI_MCR_CLR_RXF_SHIFT DSPI_MCR_CLR_RXF_SHIFT +#define SPI_MCR_CLR_RXF_WIDTH DSPI_MCR_CLR_RXF_WIDTH +#define SPI_MCR_CLR_RXF(x) DSPI_MCR_CLR_RXF(x) + +#define SPI_MCR_CLR_TXF_MASK DSPI_MCR_CLR_TXF_MASK +#define SPI_MCR_CLR_TXF_SHIFT DSPI_MCR_CLR_TXF_SHIFT +#define SPI_MCR_CLR_TXF_WIDTH DSPI_MCR_CLR_TXF_WIDTH +#define SPI_MCR_CLR_TXF(x) DSPI_MCR_CLR_TXF(x) + +#define SPI_MCR_DIS_RXF_MASK DSPI_MCR_DIS_RXF_MASK +#define SPI_MCR_DIS_RXF_SHIFT DSPI_MCR_DIS_RXF_SHIFT +#define SPI_MCR_DIS_RXF_WIDTH DSPI_MCR_DIS_RXF_WIDTH +#define SPI_MCR_DIS_RXF(x) DSPI_MCR_DIS_RXF(x) + +#define SPI_MCR_DIS_TXF_MASK DSPI_MCR_DIS_TXF_MASK +#define SPI_MCR_DIS_TXF_SHIFT DSPI_MCR_DIS_TXF_SHIFT +#define SPI_MCR_DIS_TXF_WIDTH DSPI_MCR_DIS_TXF_WIDTH +#define SPI_MCR_DIS_TXF(x) DSPI_MCR_DIS_TXF(x) + +#define SPI_MCR_MDIS_MASK DSPI_MCR_MDIS_MASK +#define SPI_MCR_MDIS_SHIFT DSPI_MCR_MDIS_SHIFT +#define SPI_MCR_MDIS_WIDTH DSPI_MCR_MDIS_WIDTH +#define SPI_MCR_MDIS(x) DSPI_MCR_MDIS(x) + +#define SPI_MCR_PCSIS_MASK DSPI_MCR_PCSIS_MASK +#define SPI_MCR_PCSIS_SHIFT DSPI_MCR_PCSIS_SHIFT +#define SPI_MCR_PCSIS_WIDTH DSPI_MCR_PCSIS_WIDTH +#define SPI_MCR_PCSIS(x) DSPI_MCR_PCSIS(x) + +#define SPI_MCR_ROOE_MASK DSPI_MCR_ROOE_MASK +#define SPI_MCR_ROOE_SHIFT DSPI_MCR_ROOE_SHIFT +#define SPI_MCR_ROOE_WIDTH DSPI_MCR_ROOE_WIDTH +#define SPI_MCR_ROOE(x) DSPI_MCR_ROOE(x) + +#define SPI_MCR_MTFE_MASK DSPI_MCR_MTFE_MASK +#define SPI_MCR_MTFE_SHIFT DSPI_MCR_MTFE_SHIFT +#define SPI_MCR_MTFE_WIDTH DSPI_MCR_MTFE_WIDTH +#define SPI_MCR_MTFE(x) DSPI_MCR_MTFE(x) + +#define SPI_MCR_FRZ_MASK DSPI_MCR_FRZ_MASK +#define SPI_MCR_FRZ_SHIFT DSPI_MCR_FRZ_SHIFT +#define SPI_MCR_FRZ_WIDTH DSPI_MCR_FRZ_WIDTH +#define SPI_MCR_FRZ(x) DSPI_MCR_FRZ(x) + +#define SPI_MCR_DCONF_MASK DSPI_MCR_DCONF_MASK +#define SPI_MCR_DCONF_SHIFT DSPI_MCR_DCONF_SHIFT +#define SPI_MCR_DCONF_WIDTH DSPI_MCR_DCONF_WIDTH +#define SPI_MCR_DCONF(x) DSPI_MCR_DCONF(x) + +#define SPI_MCR_CONT_SCKE_MASK DSPI_MCR_CONT_SCKE_MASK +#define SPI_MCR_CONT_SCKE_SHIFT DSPI_MCR_CONT_SCKE_SHIFT +#define SPI_MCR_CONT_SCKE_WIDTH DSPI_MCR_CONT_SCKE_WIDTH +#define SPI_MCR_CONT_SCKE(x) DSPI_MCR_CONT_SCKE(x) + +#define SPI_MCR_MSTR_MASK DSPI_MCR_MSTR_MASK +#define SPI_MCR_MSTR_SHIFT DSPI_MCR_MSTR_SHIFT +#define SPI_MCR_MSTR_WIDTH DSPI_MCR_MSTR_WIDTH +#define SPI_MCR_MSTR(x) DSPI_MCR_MSTR(x) +/*! @} */ + +/*! @name TCR - Transfer Count Register */ +/*! @{ */ + +#define SPI_TCR_SPI_TCNT_MASK DSPI_TCR_SPI_TCNT_MASK +#define SPI_TCR_SPI_TCNT_SHIFT DSPI_TCR_SPI_TCNT_SHIFT +#define SPI_TCR_SPI_TCNT_WIDTH DSPI_TCR_SPI_TCNT_WIDTH +#define SPI_TCR_SPI_TCNT(x) DSPI_TCR_SPI_TCNT(x) +/*! @} */ + +/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ +/*! @{ */ + +#define SPI_CTAR_BR_MASK DSPI_CTAR_BR_MASK +#define SPI_CTAR_BR_SHIFT DSPI_CTAR_BR_SHIFT +#define SPI_CTAR_BR_WIDTH DSPI_CTAR_BR_WIDTH +#define SPI_CTAR_BR(x) DSPI_CTAR_BR(x) + +#define SPI_CTAR_DT_MASK DSPI_CTAR_DT_MASK +#define SPI_CTAR_DT_SHIFT DSPI_CTAR_DT_SHIFT +#define SPI_CTAR_DT_WIDTH DSPI_CTAR_DT_WIDTH +#define SPI_CTAR_DT(x) DSPI_CTAR_DT(x) + +#define SPI_CTAR_ASC_MASK DSPI_CTAR_ASC_MASK +#define SPI_CTAR_ASC_SHIFT DSPI_CTAR_ASC_SHIFT +#define SPI_CTAR_ASC_WIDTH DSPI_CTAR_ASC_WIDTH +#define SPI_CTAR_ASC(x) DSPI_CTAR_ASC(x) + +#define SPI_CTAR_CSSCK_MASK DSPI_CTAR_CSSCK_MASK +#define SPI_CTAR_CSSCK_SHIFT DSPI_CTAR_CSSCK_SHIFT +#define SPI_CTAR_CSSCK_WIDTH DSPI_CTAR_CSSCK_WIDTH +#define SPI_CTAR_CSSCK(x) DSPI_CTAR_CSSCK(x) + +#define SPI_CTAR_PBR_MASK DSPI_CTAR_PBR_MASK +#define SPI_CTAR_PBR_SHIFT DSPI_CTAR_PBR_SHIFT +#define SPI_CTAR_PBR_WIDTH DSPI_CTAR_PBR_WIDTH +#define SPI_CTAR_PBR(x) DSPI_CTAR_PBR(x) + +#define SPI_CTAR_PDT_MASK DSPI_CTAR_PDT_MASK +#define SPI_CTAR_PDT_SHIFT DSPI_CTAR_PDT_SHIFT +#define SPI_CTAR_PDT_WIDTH DSPI_CTAR_PDT_WIDTH +#define SPI_CTAR_PDT(x) DSPI_CTAR_PDT(x) + +#define SPI_CTAR_PASC_MASK DSPI_CTAR_PASC_MASK +#define SPI_CTAR_PASC_SHIFT DSPI_CTAR_PASC_SHIFT +#define SPI_CTAR_PASC_WIDTH DSPI_CTAR_PASC_WIDTH +#define SPI_CTAR_PASC(x) DSPI_CTAR_PASC(x) + +#define SPI_CTAR_PCSSCK_MASK DSPI_CTAR_PCSSCK_MASK +#define SPI_CTAR_PCSSCK_SHIFT DSPI_CTAR_PCSSCK_SHIFT +#define SPI_CTAR_PCSSCK_WIDTH DSPI_CTAR_PCSSCK_WIDTH +#define SPI_CTAR_PCSSCK(x) DSPI_CTAR_PCSSCK(x) + +#define SPI_CTAR_LSBFE_MASK DSPI_CTAR_LSBFE_MASK +#define SPI_CTAR_LSBFE_SHIFT DSPI_CTAR_LSBFE_SHIFT +#define SPI_CTAR_LSBFE_WIDTH DSPI_CTAR_LSBFE_WIDTH +#define SPI_CTAR_LSBFE(x) DSPI_CTAR_LSBFE(x) + +#define SPI_CTAR_CPHA_MASK DSPI_CTAR_CPHA_MASK +#define SPI_CTAR_CPHA_SHIFT DSPI_CTAR_CPHA_SHIFT +#define SPI_CTAR_CPHA_WIDTH DSPI_CTAR_CPHA_WIDTH +#define SPI_CTAR_CPHA(x) DSPI_CTAR_CPHA(x) + +#define SPI_CTAR_CPOL_MASK DSPI_CTAR_CPOL_MASK +#define SPI_CTAR_CPOL_SHIFT DSPI_CTAR_CPOL_SHIFT +#define SPI_CTAR_CPOL_WIDTH DSPI_CTAR_CPOL_WIDTH +#define SPI_CTAR_CPOL(x) DSPI_CTAR_CPOL(x) + +#define SPI_CTAR_FMSZ_MASK DSPI_CTAR_FMSZ_MASK +#define SPI_CTAR_FMSZ_SHIFT DSPI_CTAR_FMSZ_SHIFT +#define SPI_CTAR_FMSZ_WIDTH DSPI_CTAR_FMSZ_WIDTH +#define SPI_CTAR_FMSZ(x) DSPI_CTAR_FMSZ(x) + +#define SPI_CTAR_DBR_MASK DSPI_CTAR_DBR_MASK +#define SPI_CTAR_DBR_SHIFT DSPI_CTAR_DBR_SHIFT +#define SPI_CTAR_DBR_WIDTH DSPI_CTAR_DBR_WIDTH +#define SPI_CTAR_DBR(x) DSPI_CTAR_DBR(x) +/*! @} */ + +/*! @name SR - Status Register */ +/*! @{ */ + +#define SPI_SR_POPNXTPTR_MASK DSPI_SR_POPNXTPTR_MASK +#define SPI_SR_POPNXTPTR_SHIFT DSPI_SR_POPNXTPTR_SHIFT +#define SPI_SR_POPNXTPTR_WIDTH DSPI_SR_POPNXTPTR_WIDTH +#define SPI_SR_POPNXTPTR(x) DSPI_SR_POPNXTPTR(x) + +#define SPI_SR_RXCTR_MASK DSPI_SR_RXCTR_MASK +#define SPI_SR_RXCTR_SHIFT DSPI_SR_RXCTR_SHIFT +#define SPI_SR_RXCTR_WIDTH DSPI_SR_RXCTR_WIDTH +#define SPI_SR_RXCTR(x) DSPI_SR_RXCTR(x) + +#define SPI_SR_TXNXTPTR_MASK DSPI_SR_TXNXTPTR_MASK +#define SPI_SR_TXNXTPTR_SHIFT DSPI_SR_TXNXTPTR_SHIFT +#define SPI_SR_TXNXTPTR_WIDTH DSPI_SR_TXNXTPTR_WIDTH +#define SPI_SR_TXNXTPTR(x) DSPI_SR_TXNXTPTR(x) + +#define SPI_SR_TXCTR_MASK DSPI_SR_TXCTR_MASK +#define SPI_SR_TXCTR_SHIFT DSPI_SR_TXCTR_SHIFT +#define SPI_SR_TXCTR_WIDTH DSPI_SR_TXCTR_WIDTH +#define SPI_SR_TXCTR(x) DSPI_SR_TXCTR(x) + +#define SPI_SR_CMDFFF_MASK DSPI_SR_CMDFFF_MASK +#define SPI_SR_CMDFFF_SHIFT DSPI_SR_CMDFFF_SHIFT +#define SPI_SR_CMDFFF_WIDTH DSPI_SR_CMDFFF_WIDTH +#define SPI_SR_CMDFFF(x) DSPI_SR_CMDFFF(x) + +#define SPI_SR_RFDF_MASK DSPI_SR_RFDF_MASK +#define SPI_SR_RFDF_SHIFT DSPI_SR_RFDF_SHIFT +#define SPI_SR_RFDF_WIDTH DSPI_SR_RFDF_WIDTH +#define SPI_SR_RFDF(x) DSPI_SR_RFDF(x) + +#define SPI_SR_TFIWF_MASK DSPI_SR_TFIWF_MASK +#define SPI_SR_TFIWF_SHIFT DSPI_SR_TFIWF_SHIFT +#define SPI_SR_TFIWF_WIDTH DSPI_SR_TFIWF_WIDTH +#define SPI_SR_TFIWF(x) DSPI_SR_TFIWF(x) + +#define SPI_SR_RFOF_MASK DSPI_SR_RFOF_MASK +#define SPI_SR_RFOF_SHIFT DSPI_SR_RFOF_SHIFT +#define SPI_SR_RFOF_WIDTH DSPI_SR_RFOF_WIDTH +#define SPI_SR_RFOF(x) DSPI_SR_RFOF(x) + +#define SPI_SR_DDIF_MASK DSPI_SR_DDIF_MASK +#define SPI_SR_DDIF_SHIFT DSPI_SR_DDIF_SHIFT +#define SPI_SR_DDIF_WIDTH DSPI_SR_DDIF_WIDTH +#define SPI_SR_DDIF(x) DSPI_SR_DDIF(x) + +#define SPI_SR_SPEF_MASK DSPI_SR_SPEF_MASK +#define SPI_SR_SPEF_SHIFT DSPI_SR_SPEF_SHIFT +#define SPI_SR_SPEF_WIDTH DSPI_SR_SPEF_WIDTH +#define SPI_SR_SPEF(x) DSPI_SR_SPEF(x) + +#define SPI_SR_DPEF_MASK DSPI_SR_DPEF_MASK +#define SPI_SR_DPEF_SHIFT DSPI_SR_DPEF_SHIFT +#define SPI_SR_DPEF_WIDTH DSPI_SR_DPEF_WIDTH +#define SPI_SR_DPEF(x) DSPI_SR_DPEF(x) + +#define SPI_SR_CMDTCF_MASK DSPI_SR_CMDTCF_MASK +#define SPI_SR_CMDTCF_SHIFT DSPI_SR_CMDTCF_SHIFT +#define SPI_SR_CMDTCF_WIDTH DSPI_SR_CMDTCF_WIDTH +#define SPI_SR_CMDTCF(x) DSPI_SR_CMDTCF(x) + +#define SPI_SR_BSYF_MASK DSPI_SR_BSYF_MASK +#define SPI_SR_BSYF_SHIFT DSPI_SR_BSYF_SHIFT +#define SPI_SR_BSYF_WIDTH DSPI_SR_BSYF_WIDTH +#define SPI_SR_BSYF(x) DSPI_SR_BSYF(x) + +#define SPI_SR_TFFF_MASK DSPI_SR_TFFF_MASK +#define SPI_SR_TFFF_SHIFT DSPI_SR_TFFF_SHIFT +#define SPI_SR_TFFF_WIDTH DSPI_SR_TFFF_WIDTH +#define SPI_SR_TFFF(x) DSPI_SR_TFFF(x) + +#define SPI_SR_EOQF_MASK DSPI_SR_EOQF_MASK +#define SPI_SR_EOQF_SHIFT DSPI_SR_EOQF_SHIFT +#define SPI_SR_EOQF_WIDTH DSPI_SR_EOQF_WIDTH +#define SPI_SR_EOQF(x) DSPI_SR_EOQF(x) + +#define SPI_SR_SPITCF_MASK DSPI_SR_SPITCF_MASK +#define SPI_SR_SPITCF_SHIFT DSPI_SR_SPITCF_SHIFT +#define SPI_SR_SPITCF_WIDTH DSPI_SR_SPITCF_WIDTH +#define SPI_SR_SPITCF(x) DSPI_SR_SPITCF(x) + +#define SPI_SR_TXRXS_MASK DSPI_SR_TXRXS_MASK +#define SPI_SR_TXRXS_SHIFT DSPI_SR_TXRXS_SHIFT +#define SPI_SR_TXRXS_WIDTH DSPI_SR_TXRXS_WIDTH +#define SPI_SR_TXRXS(x) DSPI_SR_TXRXS(x) + +#define SPI_SR_TCF_MASK DSPI_SR_TCF_MASK +#define SPI_SR_TCF_SHIFT DSPI_SR_TCF_SHIFT +#define SPI_SR_TCF_WIDTH DSPI_SR_TCF_WIDTH +#define SPI_SR_TCF(x) DSPI_SR_TCF(x) +/*! @} */ + +/*! @name RSER - DMA/Interrupt Request Select and Enable Register */ +/*! @{ */ + +#define SPI_RSER_DDIF_DIRS_MASK DSPI_RSER_DDIF_DIRS_MASK +#define SPI_RSER_DDIF_DIRS_SHIFT DSPI_RSER_DDIF_DIRS_SHIFT +#define SPI_RSER_DDIF_DIRS_WIDTH DSPI_RSER_DDIF_DIRS_WIDTH +#define SPI_RSER_DDIF_DIRS(x) DSPI_RSER_DDIF_DIRS(x) + +#define SPI_RSER_CMDFFF_DIRS_MASK DSPI_RSER_CMDFFF_DIRS_MASK +#define SPI_RSER_CMDFFF_DIRS_SHIFT DSPI_RSER_CMDFFF_DIRS_SHIFT +#define SPI_RSER_CMDFFF_DIRS_WIDTH DSPI_RSER_CMDFFF_DIRS_WIDTH +#define SPI_RSER_CMDFFF_DIRS(x) DSPI_RSER_CMDFFF_DIRS(x) + +#define SPI_RSER_RFDF_DIRS_MASK DSPI_RSER_RFDF_DIRS_MASK +#define SPI_RSER_RFDF_DIRS_SHIFT DSPI_RSER_RFDF_DIRS_SHIFT +#define SPI_RSER_RFDF_DIRS_WIDTH DSPI_RSER_RFDF_DIRS_WIDTH +#define SPI_RSER_RFDF_DIRS(x) DSPI_RSER_RFDF_DIRS(x) + +#define SPI_RSER_RFDF_RE_MASK DSPI_RSER_RFDF_RE_MASK +#define SPI_RSER_RFDF_RE_SHIFT DSPI_RSER_RFDF_RE_SHIFT +#define SPI_RSER_RFDF_RE_WIDTH DSPI_RSER_RFDF_RE_WIDTH +#define SPI_RSER_RFDF_RE(x) DSPI_RSER_RFDF_RE(x) + +#define SPI_RSER_TFIWF_RE_MASK DSPI_RSER_TFIWF_RE_MASK +#define SPI_RSER_TFIWF_RE_SHIFT DSPI_RSER_TFIWF_RE_SHIFT +#define SPI_RSER_TFIWF_RE_WIDTH DSPI_RSER_TFIWF_RE_WIDTH +#define SPI_RSER_TFIWF_RE(x) DSPI_RSER_TFIWF_RE(x) + +#define SPI_RSER_RFOF_RE_MASK DSPI_RSER_RFOF_RE_MASK +#define SPI_RSER_RFOF_RE_SHIFT DSPI_RSER_RFOF_RE_SHIFT +#define SPI_RSER_RFOF_RE_WIDTH DSPI_RSER_RFOF_RE_WIDTH +#define SPI_RSER_RFOF_RE(x) DSPI_RSER_RFOF_RE(x) + +#define SPI_RSER_DDIF_RE_MASK DSPI_RSER_DDIF_RE_MASK +#define SPI_RSER_DDIF_RE_SHIFT DSPI_RSER_DDIF_RE_SHIFT +#define SPI_RSER_DDIF_RE_WIDTH DSPI_RSER_DDIF_RE_WIDTH +#define SPI_RSER_DDIF_RE(x) DSPI_RSER_DDIF_RE(x) + +#define SPI_RSER_SPEF_RE_MASK DSPI_RSER_SPEF_RE_MASK +#define SPI_RSER_SPEF_RE_SHIFT DSPI_RSER_SPEF_RE_SHIFT +#define SPI_RSER_SPEF_RE_WIDTH DSPI_RSER_SPEF_RE_WIDTH +#define SPI_RSER_SPEF_RE(x) DSPI_RSER_SPEF_RE(x) + +#define SPI_RSER_DPEF_RE_MASK DSPI_RSER_DPEF_RE_MASK +#define SPI_RSER_DPEF_RE_SHIFT DSPI_RSER_DPEF_RE_SHIFT +#define SPI_RSER_DPEF_RE_WIDTH DSPI_RSER_DPEF_RE_WIDTH +#define SPI_RSER_DPEF_RE(x) DSPI_RSER_DPEF_RE(x) + +#define SPI_RSER_CMDTCF_RE_MASK DSPI_RSER_CMDTCF_RE_MASK +#define SPI_RSER_CMDTCF_RE_SHIFT DSPI_RSER_CMDTCF_RE_SHIFT +#define SPI_RSER_CMDTCF_RE_WIDTH DSPI_RSER_CMDTCF_RE_WIDTH +#define SPI_RSER_CMDTCF_RE(x) DSPI_RSER_CMDTCF_RE(x) + +#define SPI_RSER_TFFF_DIRS_MASK DSPI_RSER_TFFF_DIRS_MASK +#define SPI_RSER_TFFF_DIRS_SHIFT DSPI_RSER_TFFF_DIRS_SHIFT +#define SPI_RSER_TFFF_DIRS_WIDTH DSPI_RSER_TFFF_DIRS_WIDTH +#define SPI_RSER_TFFF_DIRS(x) DSPI_RSER_TFFF_DIRS(x) + +#define SPI_RSER_TFFF_RE_MASK DSPI_RSER_TFFF_RE_MASK +#define SPI_RSER_TFFF_RE_SHIFT DSPI_RSER_TFFF_RE_SHIFT +#define SPI_RSER_TFFF_RE_WIDTH DSPI_RSER_TFFF_RE_WIDTH +#define SPI_RSER_TFFF_RE(x) DSPI_RSER_TFFF_RE(x) + +#define SPI_RSER_EOQF_RE_MASK DSPI_RSER_EOQF_RE_MASK +#define SPI_RSER_EOQF_RE_SHIFT DSPI_RSER_EOQF_RE_SHIFT +#define SPI_RSER_EOQF_RE_WIDTH DSPI_RSER_EOQF_RE_WIDTH +#define SPI_RSER_EOQF_RE(x) DSPI_RSER_EOQF_RE(x) + +#define SPI_RSER_CMDFFF_RE_MASK DSPI_RSER_CMDFFF_RE_MASK +#define SPI_RSER_CMDFFF_RE_SHIFT DSPI_RSER_CMDFFF_RE_SHIFT +#define SPI_RSER_CMDFFF_RE_WIDTH DSPI_RSER_CMDFFF_RE_WIDTH +#define SPI_RSER_CMDFFF_RE(x) DSPI_RSER_CMDFFF_RE(x) + +#define SPI_RSER_TCF_RE_MASK DSPI_RSER_TCF_RE_MASK +#define SPI_RSER_TCF_RE_SHIFT DSPI_RSER_TCF_RE_SHIFT +#define SPI_RSER_TCF_RE_WIDTH DSPI_RSER_TCF_RE_WIDTH +#define SPI_RSER_TCF_RE(x) DSPI_RSER_TCF_RE(x) +/*! @} */ + +/*! @name TX - DSPI_TX register */ +/*! @{ */ + +#define SPI_TX_TX_MASK DSPI_TX_TX_MASK +#define SPI_TX_TX_SHIFT DSPI_TX_TX_SHIFT +#define SPI_TX_TX_WIDTH DSPI_TX_TX_WIDTH +#define SPI_TX_TX(x) DSPI_TX_TX(x) +/*! @} */ + +/*! @name CMD - DSPI_CMD register */ +/*! @{ */ + +#define SPI_CMD_CMD_MASK DSPI_CMD_CMD_MASK +#define SPI_CMD_CMD_SHIFT DSPI_CMD_CMD_SHIFT +#define SPI_CMD_CMD_WIDTH DSPI_CMD_CMD_WIDTH +#define SPI_CMD_CMD(x) DSPI_CMD_CMD(x) +/*! @} */ + +/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ +/*! @{ */ + +#define SPI_PUSHR_TXDATA_MASK DSPI_PUSHR_TXDATA_MASK +#define SPI_PUSHR_TXDATA_SHIFT DSPI_PUSHR_TXDATA_SHIFT +#define SPI_PUSHR_TXDATA_WIDTH DSPI_PUSHR_TXDATA_WIDTH +#define SPI_PUSHR_TXDATA(x) DSPI_PUSHR_TXDATA(x) + +#define SPI_PUSHR_PCS_MASK DSPI_PUSHR_PCS_MASK +#define SPI_PUSHR_PCS_SHIFT DSPI_PUSHR_PCS_SHIFT +#define SPI_PUSHR_PCS_WIDTH DSPI_PUSHR_PCS_WIDTH +#define SPI_PUSHR_PCS(x) DSPI_PUSHR_PCS(x) + +#define SPI_PUSHR_PP_MCSC_MASK DSPI_PUSHR_PP_MCSC_MASK +#define SPI_PUSHR_PP_MCSC_SHIFT DSPI_PUSHR_PP_MCSC_SHIFT +#define SPI_PUSHR_PP_MCSC_WIDTH DSPI_PUSHR_PP_MCSC_WIDTH +#define SPI_PUSHR_PP_MCSC(x) DSPI_PUSHR_PP_MCSC(x) + +#define SPI_PUSHR_PE_MASC_MASK DSPI_PUSHR_PE_MASC_MASK +#define SPI_PUSHR_PE_MASC_SHIFT DSPI_PUSHR_PE_MASC_SHIFT +#define SPI_PUSHR_PE_MASC_WIDTH DSPI_PUSHR_PE_MASC_WIDTH +#define SPI_PUSHR_PE_MASC(x) DSPI_PUSHR_PE_MASC(x) + +#define SPI_PUSHR_CTCNT_MASK DSPI_PUSHR_CTCNT_MASK +#define SPI_PUSHR_CTCNT_SHIFT DSPI_PUSHR_CTCNT_SHIFT +#define SPI_PUSHR_CTCNT_WIDTH DSPI_PUSHR_CTCNT_WIDTH +#define SPI_PUSHR_CTCNT(x) DSPI_PUSHR_CTCNT(x) + +#define SPI_PUSHR_EOQ_MASK DSPI_PUSHR_EOQ_MASK +#define SPI_PUSHR_EOQ_SHIFT DSPI_PUSHR_EOQ_SHIFT +#define SPI_PUSHR_EOQ_WIDTH DSPI_PUSHR_EOQ_WIDTH +#define SPI_PUSHR_EOQ(x) DSPI_PUSHR_EOQ(x) + +#define SPI_PUSHR_CTAS_MASK DSPI_PUSHR_CTAS_MASK +#define SPI_PUSHR_CTAS_SHIFT DSPI_PUSHR_CTAS_SHIFT +#define SPI_PUSHR_CTAS_WIDTH DSPI_PUSHR_CTAS_WIDTH +#define SPI_PUSHR_CTAS(x) DSPI_PUSHR_CTAS(x) + +#define SPI_PUSHR_CONT_MASK DSPI_PUSHR_CONT_MASK +#define SPI_PUSHR_CONT_SHIFT DSPI_PUSHR_CONT_SHIFT +#define SPI_PUSHR_CONT_WIDTH DSPI_PUSHR_CONT_WIDTH +#define SPI_PUSHR_CONT(x) DSPI_PUSHR_CONT(x) +/*! @} */ + +/*! @name POPR - POP RX FIFO Register */ +/*! @{ */ + +#define SPI_POPR_RXDATA_MASK DSPI_POPR_RXDATA_MASK +#define SPI_POPR_RXDATA_SHIFT DSPI_POPR_RXDATA_SHIFT +#define SPI_POPR_RXDATA_WIDTH DSPI_POPR_RXDATA_WIDTH +#define SPI_POPR_RXDATA(x) DSPI_POPR_RXDATA(x) +/*! @} */ + +/*! @name TXFR - Transmit FIFO Registers */ +/*! @{ */ + +#define SPI_TXFR_TXDATA_MASK DSPI_TXFR_TXDATA_MASK +#define SPI_TXFR_TXDATA_SHIFT DSPI_TXFR_TXDATA_SHIFT +#define SPI_TXFR_TXDATA_WIDTH DSPI_TXFR_TXDATA_WIDTH +#define SPI_TXFR_TXDATA(x) DSPI_TXFR_TXDATA(x) + +#define SPI_TXFR_TXCMD_TXDATA_MASK DSPI_TXFR_TXCMD_TXDATA_MASK +#define SPI_TXFR_TXCMD_TXDATA_SHIFT DSPI_TXFR_TXCMD_TXDATA_SHIFT +#define SPI_TXFR_TXCMD_TXDATA_WIDTH DSPI_TXFR_TXCMD_TXDATA_WIDTH +#define SPI_TXFR_TXCMD_TXDATA(x) DSPI_TXFR_TXCMD_TXDATA(x) +/*! @} */ + +/*! @name RXFR - Receive FIFO Registers */ +/*! @{ */ + +#define SPI_RXFR_RXDATA_MASK DSPI_RXFR_RXDATA_MASK +#define SPI_RXFR_RXDATA_SHIFT DSPI_RXFR_RXDATA_SHIFT +#define SPI_RXFR_RXDATA_WIDTH DSPI_RXFR_RXDATA_WIDTH +#define SPI_RXFR_RXDATA(x) DSPI_RXFR_RXDATA(x) +/*! @} */ + +/*! @name DSICR0 - DSI Configuration Register 0 */ +/*! @{ */ + +#define SPI_DSICR0_DPCSx_MASK DSPI_DSICR0_DPCSx_MASK +#define SPI_DSICR0_DPCSx_SHIFT DSPI_DSICR0_DPCSx_SHIFT +#define SPI_DSICR0_DPCSx_WIDTH DSPI_DSICR0_DPCSx_WIDTH +#define SPI_DSICR0_DPCSx(x) DSPI_DSICR0_DPCSx(x) + +#define SPI_DSICR0_PP_MASK DSPI_DSICR0_PP_MASK +#define SPI_DSICR0_PP_SHIFT DSPI_DSICR0_PP_SHIFT +#define SPI_DSICR0_PP_WIDTH DSPI_DSICR0_PP_WIDTH +#define SPI_DSICR0_PP(x) DSPI_DSICR0_PP(x) + +#define SPI_DSICR0_PE_MASK DSPI_DSICR0_PE_MASK +#define SPI_DSICR0_PE_SHIFT DSPI_DSICR0_PE_SHIFT +#define SPI_DSICR0_PE_WIDTH DSPI_DSICR0_PE_WIDTH +#define SPI_DSICR0_PE(x) DSPI_DSICR0_PE(x) + +#define SPI_DSICR0_PES_MASK DSPI_DSICR0_PES_MASK +#define SPI_DSICR0_PES_SHIFT DSPI_DSICR0_PES_SHIFT +#define SPI_DSICR0_PES_WIDTH DSPI_DSICR0_PES_WIDTH +#define SPI_DSICR0_PES(x) DSPI_DSICR0_PES(x) + +#define SPI_DSICR0_DMS_MASK DSPI_DSICR0_DMS_MASK +#define SPI_DSICR0_DMS_SHIFT DSPI_DSICR0_DMS_SHIFT +#define SPI_DSICR0_DMS_WIDTH DSPI_DSICR0_DMS_WIDTH +#define SPI_DSICR0_DMS(x) DSPI_DSICR0_DMS(x) + +#define SPI_DSICR0_DSICTAS_MASK DSPI_DSICR0_DSICTAS_MASK +#define SPI_DSICR0_DSICTAS_SHIFT DSPI_DSICR0_DSICTAS_SHIFT +#define SPI_DSICR0_DSICTAS_WIDTH DSPI_DSICR0_DSICTAS_WIDTH +#define SPI_DSICR0_DSICTAS(x) DSPI_DSICR0_DSICTAS(x) + +#define SPI_DSICR0_DCONT_MASK DSPI_DSICR0_DCONT_MASK +#define SPI_DSICR0_DCONT_SHIFT DSPI_DSICR0_DCONT_SHIFT +#define SPI_DSICR0_DCONT_WIDTH DSPI_DSICR0_DCONT_WIDTH +#define SPI_DSICR0_DCONT(x) DSPI_DSICR0_DCONT(x) + +#define SPI_DSICR0_CID_MASK DSPI_DSICR0_CID_MASK +#define SPI_DSICR0_CID_SHIFT DSPI_DSICR0_CID_SHIFT +#define SPI_DSICR0_CID_WIDTH DSPI_DSICR0_CID_WIDTH +#define SPI_DSICR0_CID(x) DSPI_DSICR0_CID(x) + +#define SPI_DSICR0_TXSS_MASK DSPI_DSICR0_TXSS_MASK +#define SPI_DSICR0_TXSS_SHIFT DSPI_DSICR0_TXSS_SHIFT +#define SPI_DSICR0_TXSS_WIDTH DSPI_DSICR0_TXSS_WIDTH +#define SPI_DSICR0_TXSS(x) DSPI_DSICR0_TXSS(x) + +#define SPI_DSICR0_TSBC_MASK DSPI_DSICR0_TSBC_MASK +#define SPI_DSICR0_TSBC_SHIFT DSPI_DSICR0_TSBC_SHIFT +#define SPI_DSICR0_TSBC_WIDTH DSPI_DSICR0_TSBC_WIDTH +#define SPI_DSICR0_TSBC(x) DSPI_DSICR0_TSBC(x) + +#define SPI_DSICR0_ITSB_MASK DSPI_DSICR0_ITSB_MASK +#define SPI_DSICR0_ITSB_SHIFT DSPI_DSICR0_ITSB_SHIFT +#define SPI_DSICR0_ITSB_WIDTH DSPI_DSICR0_ITSB_WIDTH +#define SPI_DSICR0_ITSB(x) DSPI_DSICR0_ITSB(x) + +#define SPI_DSICR0_FMSZ5_MASK DSPI_DSICR0_FMSZ5_MASK +#define SPI_DSICR0_FMSZ5_SHIFT DSPI_DSICR0_FMSZ5_SHIFT +#define SPI_DSICR0_FMSZ5_WIDTH DSPI_DSICR0_FMSZ5_WIDTH +#define SPI_DSICR0_FMSZ5(x) DSPI_DSICR0_FMSZ5(x) + +#define SPI_DSICR0_FMSZ4_MASK DSPI_DSICR0_FMSZ4_MASK +#define SPI_DSICR0_FMSZ4_SHIFT DSPI_DSICR0_FMSZ4_SHIFT +#define SPI_DSICR0_FMSZ4_WIDTH DSPI_DSICR0_FMSZ4_WIDTH +#define SPI_DSICR0_FMSZ4(x) DSPI_DSICR0_FMSZ4(x) +/*! @} */ + +/*! @name SDR0 - DSI Serialization Data Register 0 */ +/*! @{ */ + +#define SPI_SDR0_SER_DATA_MASK DSPI_SDR0_SER_DATA_MASK +#define SPI_SDR0_SER_DATA_SHIFT DSPI_SDR0_SER_DATA_SHIFT +#define SPI_SDR0_SER_DATA_WIDTH DSPI_SDR0_SER_DATA_WIDTH +#define SPI_SDR0_SER_DATA(x) DSPI_SDR0_SER_DATA(x) +/*! @} */ + +/*! @name ASDR0 - DSI Alternate Serialization Data Register 0 */ +/*! @{ */ + +#define SPI_ASDR0_ASER_DATA_MASK DSPI_ASDR0_ASER_DATA_MASK +#define SPI_ASDR0_ASER_DATA_SHIFT DSPI_ASDR0_ASER_DATA_SHIFT +#define SPI_ASDR0_ASER_DATA_WIDTH DSPI_ASDR0_ASER_DATA_WIDTH +#define SPI_ASDR0_ASER_DATA(x) DSPI_ASDR0_ASER_DATA(x) +/*! @} */ + +/*! @name COMPR0 - DSI Transmit Comparison Register 0 */ +/*! @{ */ + +#define SPI_COMPR0_COMP_DATA_MASK DSPI_COMPR0_COMP_DATA_MASK +#define SPI_COMPR0_COMP_DATA_SHIFT DSPI_COMPR0_COMP_DATA_SHIFT +#define SPI_COMPR0_COMP_DATA_WIDTH DSPI_COMPR0_COMP_DATA_WIDTH +#define SPI_COMPR0_COMP_DATA(x) DSPI_COMPR0_COMP_DATA(x) +/*! @} */ + +/*! @name DDR0 - DSI Deserialization Data Register 0 */ +/*! @{ */ + +#define SPI_DDR0_DESER_DATA_MASK DSPI_DDR0_DESER_DATA_MASK +#define SPI_DDR0_DESER_DATA_SHIFT DSPI_DDR0_DESER_DATA_SHIFT +#define SPI_DDR0_DESER_DATA_WIDTH DSPI_DDR0_DESER_DATA_WIDTH +#define SPI_DDR0_DESER_DATA(x) DSPI_DDR0_DESER_DATA(x) +/*! @} */ + +/*! @name DSICR1 - DSI Configuration Register 1 */ +/*! @{ */ + +#define SPI_DSICR1_DPCS1_x_MASK DSPI_DSICR1_DPCS1_x_MASK +#define SPI_DSICR1_DPCS1_x_SHIFT DSPI_DSICR1_DPCS1_x_SHIFT +#define SPI_DSICR1_DPCS1_x_WIDTH DSPI_DSICR1_DPCS1_x_WIDTH +#define SPI_DSICR1_DPCS1_x(x) DSPI_DSICR1_DPCS1_x(x) + +#define SPI_DSICR1_DSE0_MASK DSPI_DSICR1_DSE0_MASK +#define SPI_DSICR1_DSE0_SHIFT DSPI_DSICR1_DSE0_SHIFT +#define SPI_DSICR1_DSE0_WIDTH DSPI_DSICR1_DSE0_WIDTH +#define SPI_DSICR1_DSE0(x) DSPI_DSICR1_DSE0(x) + +#define SPI_DSICR1_DSE1_MASK DSPI_DSICR1_DSE1_MASK +#define SPI_DSICR1_DSE1_SHIFT DSPI_DSICR1_DSE1_SHIFT +#define SPI_DSICR1_DSE1_WIDTH DSPI_DSICR1_DSE1_WIDTH +#define SPI_DSICR1_DSE1(x) DSPI_DSICR1_DSE1(x) + +#define SPI_DSICR1_DSI64E_MASK DSPI_DSICR1_DSI64E_MASK +#define SPI_DSICR1_DSI64E_SHIFT DSPI_DSICR1_DSI64E_SHIFT +#define SPI_DSICR1_DSI64E_WIDTH DSPI_DSICR1_DSI64E_WIDTH +#define SPI_DSICR1_DSI64E(x) DSPI_DSICR1_DSI64E(x) + +#define SPI_DSICR1_CSE_MASK DSPI_DSICR1_CSE_MASK +#define SPI_DSICR1_CSE_SHIFT DSPI_DSICR1_CSE_SHIFT +#define SPI_DSICR1_CSE_WIDTH DSPI_DSICR1_CSE_WIDTH +#define SPI_DSICR1_CSE(x) DSPI_DSICR1_CSE(x) + +#define SPI_DSICR1_TSBCNT_MASK DSPI_DSICR1_TSBCNT_MASK +#define SPI_DSICR1_TSBCNT_SHIFT DSPI_DSICR1_TSBCNT_SHIFT +#define SPI_DSICR1_TSBCNT_WIDTH DSPI_DSICR1_TSBCNT_WIDTH +#define SPI_DSICR1_TSBCNT(x) DSPI_DSICR1_TSBCNT(x) +/*! @} */ + +/*! @name SSR0 - DSI Serialization Source Select Register 0 */ +/*! @{ */ + +#define SPI_SSR0_SS_MASK DSPI_SSR0_SS_MASK +#define SPI_SSR0_SS_SHIFT DSPI_SSR0_SS_SHIFT +#define SPI_SSR0_SS_WIDTH DSPI_SSR0_SS_WIDTH +#define SPI_SSR0_SS(x) DSPI_SSR0_SS(x) +/*! @} */ + +/*! @name DIMR0 - DSI Deserialized Data Interrupt Mask Register 0 */ +/*! @{ */ + +#define SPI_DIMR0_MASK_MASK DSPI_DIMR0_MASK_MASK +#define SPI_DIMR0_MASK_SHIFT DSPI_DIMR0_MASK_SHIFT +#define SPI_DIMR0_MASK_WIDTH DSPI_DIMR0_MASK_WIDTH +#define SPI_DIMR0_MASK(x) DSPI_DIMR0_MASK(x) +/*! @} */ + +/*! @name DPIR0 - DSI Deserialized Data Polarity Interrupt Register 0 */ +/*! @{ */ + +#define SPI_DPIR0_DP_MASK DSPI_DPIR0_DP_MASK +#define SPI_DPIR0_DP_SHIFT DSPI_DPIR0_DP_SHIFT +#define SPI_DPIR0_DP_WIDTH DSPI_DPIR0_DP_WIDTH +#define SPI_DPIR0_DP(x) DSPI_DPIR0_DP(x) +/*! @} */ + +/*! @name SDR1 - DSI Serialization Data Register 1 */ +/*! @{ */ + +#define SPI_SDR1_SER_DATA_MASK DSPI_SDR1_SER_DATA_MASK +#define SPI_SDR1_SER_DATA_SHIFT DSPI_SDR1_SER_DATA_SHIFT +#define SPI_SDR1_SER_DATA_WIDTH DSPI_SDR1_SER_DATA_WIDTH +#define SPI_SDR1_SER_DATA(x) DSPI_SDR1_SER_DATA(x) +/*! @} */ + +/*! @name ASDR1 - DSI Alternate Serialization Data Register 1 */ +/*! @{ */ + +#define SPI_ASDR1_ASER_DATA_MASK DSPI_ASDR1_ASER_DATA_MASK +#define SPI_ASDR1_ASER_DATA_SHIFT DSPI_ASDR1_ASER_DATA_SHIFT +#define SPI_ASDR1_ASER_DATA_WIDTH DSPI_ASDR1_ASER_DATA_WIDTH +#define SPI_ASDR1_ASER_DATA(x) DSPI_ASDR1_ASER_DATA(x) +/*! @} */ + +/*! @name COMPR1 - DSI Transmit Comparison Register 1 */ +/*! @{ */ + +#define SPI_COMPR1_COMP_DATA_MASK DSPI_COMPR1_COMP_DATA_MASK +#define SPI_COMPR1_COMP_DATA_SHIFT DSPI_COMPR1_COMP_DATA_SHIFT +#define SPI_COMPR1_COMP_DATA_WIDTH DSPI_COMPR1_COMP_DATA_WIDTH +#define SPI_COMPR1_COMP_DATA(x) DSPI_COMPR1_COMP_DATA(x) +/*! @} */ + +/*! @name DDR1 - DSI Deserialization Data Register 1 */ +/*! @{ */ + +#define SPI_DDR1_DESER_DATA_MASK DSPI_DDR1_DESER_DATA_MASK +#define SPI_DDR1_DESER_DATA_SHIFT DSPI_DDR1_DESER_DATA_SHIFT +#define SPI_DDR1_DESER_DATA_WIDTH DSPI_DDR1_DESER_DATA_WIDTH +#define SPI_DDR1_DESER_DATA(x) DSPI_DDR1_DESER_DATA(x) +/*! @} */ + +/*! @name SSR1 - DSI Serialization Source Select Register 1 */ +/*! @{ */ + +#define SPI_SSR1_SS_MASK DSPI_SSR1_SS_MASK +#define SPI_SSR1_SS_SHIFT DSPI_SSR1_SS_SHIFT +#define SPI_SSR1_SS_WIDTH DSPI_SSR1_SS_WIDTH +#define SPI_SSR1_SS(x) DSPI_SSR1_SS(x) +/*! @} */ + +/*! @name DIMR1 - DSI Deserialized Data Interrupt Mask Register 1 */ +/*! @{ */ + +#define SPI_DIMR1_MASK_MASK DSPI_DIMR1_MASK_MASK +#define SPI_DIMR1_MASK_SHIFT DSPI_DIMR1_MASK_SHIFT +#define SPI_DIMR1_MASK_WIDTH DSPI_DIMR1_MASK_WIDTH +#define SPI_DIMR1_MASK(x) DSPI_DIMR1_MASK(x) +/*! @} */ + +/*! @name DPIR1 - DSI Deserialized Data Polarity Interrupt Register 1 */ +/*! @{ */ + +#define SPI_DPIR1_DP_MASK DSPI_DPIR1_DP_MASK +#define SPI_DPIR1_DP_SHIFT DSPI_DPIR1_DP_SHIFT +#define SPI_DPIR1_DP_WIDTH DSPI_DPIR1_DP_WIDTH +#define SPI_DPIR1_DP(x) DSPI_DPIR1_DP(x) +/*! @} */ + +/*! @name CTARE - Clock and Transfer Attributes Register Extended */ +/*! @{ */ + +#define SPI_CTARE_DTCP_MASK DSPI_CTARE_DTCP_MASK +#define SPI_CTARE_DTCP_SHIFT DSPI_CTARE_DTCP_SHIFT +#define SPI_CTARE_DTCP_WIDTH DSPI_CTARE_DTCP_WIDTH +#define SPI_CTARE_DTCP(x) DSPI_CTARE_DTCP(x) + +#define SPI_CTARE_FMSZE_MASK DSPI_CTARE_FMSZE_MASK +#define SPI_CTARE_FMSZE_SHIFT DSPI_CTARE_FMSZE_SHIFT +#define SPI_CTARE_FMSZE_WIDTH DSPI_CTARE_FMSZE_WIDTH +#define SPI_CTARE_FMSZE(x) DSPI_CTARE_FMSZE(x) +/*! @} */ + +/*! @name SREX - Status Register Extended */ +/*! @{ */ + +#define SPI_SREX_CMDNXTPTR_MASK DSPI_SREX_CMDNXTPTR_MASK +#define SPI_SREX_CMDNXTPTR_SHIFT DSPI_SREX_CMDNXTPTR_SHIFT +#define SPI_SREX_CMDNXTPTR_WIDTH DSPI_SREX_CMDNXTPTR_WIDTH +#define SPI_SREX_CMDNXTPTR(x) DSPI_SREX_CMDNXTPTR(x) + +#define SPI_SREX_CMDCTR_MASK DSPI_SREX_CMDCTR_MASK +#define SPI_SREX_CMDCTR_SHIFT DSPI_SREX_CMDCTR_SHIFT +#define SPI_SREX_CMDCTR_WIDTH DSPI_SREX_CMDCTR_WIDTH +#define SPI_SREX_CMDCTR(x) DSPI_SREX_CMDCTR(x) + +#define SPI_SREX_RXCTR4_MASK DSPI_SREX_RXCTR4_MASK +#define SPI_SREX_RXCTR4_SHIFT DSPI_SREX_RXCTR4_SHIFT +#define SPI_SREX_RXCTR4_WIDTH DSPI_SREX_RXCTR4_WIDTH +#define SPI_SREX_RXCTR4(x) DSPI_SREX_RXCTR4(x) + +#define SPI_SREX_TXCTR4_MASK DSPI_SREX_TXCTR4_MASK +#define SPI_SREX_TXCTR4_SHIFT DSPI_SREX_TXCTR4_SHIFT +#define SPI_SREX_TXCTR4_WIDTH DSPI_SREX_TXCTR4_WIDTH +#define SPI_SREX_TXCTR4(x) DSPI_SREX_TXCTR4(x) +/*! @} */ + +/*! @name TSL - Time Slot Length Register */ +/*! @{ */ + +#define SPI_TSL_TS0_LEN_MASK DSPI_TSL_TS0_LEN_MASK +#define SPI_TSL_TS0_LEN_SHIFT DSPI_TSL_TS0_LEN_SHIFT +#define SPI_TSL_TS0_LEN_WIDTH DSPI_TSL_TS0_LEN_WIDTH +#define SPI_TSL_TS0_LEN(x) DSPI_TSL_TS0_LEN(x) + +#define SPI_TSL_TS1_LEN_MASK DSPI_TSL_TS1_LEN_MASK +#define SPI_TSL_TS1_LEN_SHIFT DSPI_TSL_TS1_LEN_SHIFT +#define SPI_TSL_TS1_LEN_WIDTH DSPI_TSL_TS1_LEN_WIDTH +#define SPI_TSL_TS1_LEN(x) DSPI_TSL_TS1_LEN(x) + +#define SPI_TSL_TS2_LEN_MASK DSPI_TSL_TS2_LEN_MASK +#define SPI_TSL_TS2_LEN_SHIFT DSPI_TSL_TS2_LEN_SHIFT +#define SPI_TSL_TS2_LEN_WIDTH DSPI_TSL_TS2_LEN_WIDTH +#define SPI_TSL_TS2_LEN(x) DSPI_TSL_TS2_LEN(x) + +#define SPI_TSL_TS3_LEN_MASK DSPI_TSL_TS3_LEN_MASK +#define SPI_TSL_TS3_LEN_SHIFT DSPI_TSL_TS3_LEN_SHIFT +#define SPI_TSL_TS3_LEN_WIDTH DSPI_TSL_TS3_LEN_WIDTH +#define SPI_TSL_TS3_LEN(x) DSPI_TSL_TS3_LEN(x) +/*! @} */ + +/*! @name TS_CONF - Time Slot Configuration Register */ +/*! @{ */ + +#define SPI_TS_CONF_TS0_MASK DSPI_TS_CONF_TS0_MASK +#define SPI_TS_CONF_TS0_SHIFT DSPI_TS_CONF_TS0_SHIFT +#define SPI_TS_CONF_TS0_WIDTH DSPI_TS_CONF_TS0_WIDTH +#define SPI_TS_CONF_TS0(x) DSPI_TS_CONF_TS0(x) + +#define SPI_TS_CONF_TS1_MASK DSPI_TS_CONF_TS1_MASK +#define SPI_TS_CONF_TS1_SHIFT DSPI_TS_CONF_TS1_SHIFT +#define SPI_TS_CONF_TS1_WIDTH DSPI_TS_CONF_TS1_WIDTH +#define SPI_TS_CONF_TS1(x) DSPI_TS_CONF_TS1(x) + +#define SPI_TS_CONF_TS2_MASK DSPI_TS_CONF_TS2_MASK +#define SPI_TS_CONF_TS2_SHIFT DSPI_TS_CONF_TS2_SHIFT +#define SPI_TS_CONF_TS2_WIDTH DSPI_TS_CONF_TS2_WIDTH +#define SPI_TS_CONF_TS2(x) DSPI_TS_CONF_TS2(x) + +#define SPI_TS_CONF_TS3_MASK DSPI_TS_CONF_TS3_MASK +#define SPI_TS_CONF_TS3_SHIFT DSPI_TS_CONF_TS3_SHIFT +#define SPI_TS_CONF_TS3_WIDTH DSPI_TS_CONF_TS3_WIDTH +#define SPI_TS_CONF_TS3(x) DSPI_TS_CONF_TS3(x) +/*! @} */ + +/*! + * @} + */ /* end of group DSPI_Register_Masks */ + +/*! + * @} + */ /* end of group DSPI_Peripheral_Access_Layer */ + #endif /* _S32Z270_DEVICE_H_ */ diff --git a/s32/mcux/devices/S32Z270/S32Z270_features.h b/s32/mcux/devices/S32Z270/S32Z270_features.h index 82b9def3e..da3e2f34f 100644 --- a/s32/mcux/devices/S32Z270/S32Z270_features.h +++ b/s32/mcux/devices/S32Z270/S32Z270_features.h @@ -120,4 +120,33 @@ /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (8) +/* DSPI module features */ + +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (1) +/* @brief Receive/transmit FIFO size in number of items. */ +#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (16) +/* @brief Maximum transfer data width in bits. */ +#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) +/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ +#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (3) +/* @brief Number of chip select pins. */ +#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) +/* @brief Number of CTAR registers. */ +#define FSL_FEATURE_DSPI_CTAR_COUNT (6) +/* @brief Has chip select strobe capability on the PCS5 pin. */ +#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) +/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) +/* @brief Has 16-bit data transfer support. */ +#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) +/* @brief Has separate DMA RX and TX requests. */ +#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) +/* @brief Does not support Transmit FIFO Fill Flag (bitfield SR[TFUF]. */ +#define FSL_FEATURE_DSPI_HAS_NO_SR_TFUF_SUPPORT (1) +/* @brief Does not support Transmit FIFO Underflow Request Enable (bitfield RSER[TFUF_RE]. */ +#define FSL_FEATURE_DSPI_HAS_NO_RSER_TFUF_RE_SUPPORT (1) +/* @brief Does not support Slave mode . */ +#define FSL_FEATURE_DSPI_HAS_NO_SLAVE_SUPPORT (1) + #endif /* _S32Z270_FEATURES_H_ */ diff --git a/s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h b/s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h index 47681e954..77ae81c0a 100644 --- a/s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h +++ b/s32/mcux/devices/S32Z270/S32Z270_glue_mcux.h @@ -50,6 +50,18 @@ #define I3C_IBIEXT2_EXT6(x) 0 #define I3C_IBIEXT2_EXT7(x) 0 +/* SPI - Peripheral instance base addresses */ +/** Peripheral MSC_0_DSPI base address */ +#define SPI0_BASE IP_MSC_0_DSPI_BASE +/** Peripheral MSC_0_DSPI base pointer */ +#define SPI0 ((SPI_Type *)SPI0_BASE) +/** Array initializer of DSPI peripheral base addresses */ +#define SPI_BASE_ADDRS { SPI0_BASE } +/** Array initializer of DSPI peripheral base pointers */ +#define SPI_BASE_PTRS { SPI0 } + +#define SPI_IRQS { RTU_MSC0_DSPI_IRQn } + /* CAN - Peripheral instance base addresses */ /** Peripheral CAN_0 base address */ #define CAN0_BASE IP_CE_CAN_0_BASE