diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst
index ba3f5627a6f76c1..39a74a81ab734b1 100644
--- a/boards/st/nucleo_h745zi_q/doc/index.rst
+++ b/boards/st/nucleo_h745zi_q/doc/index.rst
@@ -112,6 +112,8 @@ features:
 +-------------+------------+-------------------------------------+
 | SPI         | on-chip    | spi                                 |
 +-------------+------------+-------------------------------------+
+| FDCAN       | on-chip    | CAN-FD Control Area Network         |
++-------------+------------+-------------------------------------+
 
 Other hardware features are not yet supported on this Zephyr port.
 
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
index bce218ae37da149..960c4207a6fd911 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
@@ -144,3 +144,13 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&fdcan1 {
+	pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb9>;
+	// HSE will be used by default. Uncomment below to enable APB1.2 120MHz clock
+	// clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
+	//	    <&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
+	pinctrl-names = "default";
+	// pins are confilcting with i2c1 - disable i2c1 first to enable
+	status = "disabled";
+};
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
index ff551e718374a6b..259cd29438b6626 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
@@ -16,6 +16,7 @@ supported:
   - counter
   - i2c
   - pwm
+  - can
   - netif:eth
   - spi
   - usb_device