diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 6243a03fe7dbf95..15427fa82be847e 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -594,7 +594,7 @@ if BUILD_OUTPUT_UF2 config BUILD_OUTPUT_UF2_FAMILY_ID string "UF2 device family ID" - default "0x1c5f21b0" if SOC_ESP32 + default "0x1c5f21b0" if SOC_SERIES_ESP32 default "0x621e937a" if SOC_NRF52833_QIAA default "0xada52840" if SOC_NRF52840_QIAA default "0x4fb2d5bd" if SOC_SERIES_IMX_RT diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 93216a5aa247edb..5d042c1d4758c0b 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -46,7 +46,7 @@ config XTENSA_USE_CORE_CRT1 config XTENSA_ENABLE_BACKTRACE bool "Backtrace on panic exception" default y - depends on SOC_ESP32 || SOC_FAMILY_INTEL_ADSP + depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP help Enable this config option to print backtrace on panic exception diff --git a/arch/xtensa/core/coredump.c b/arch/xtensa/core/coredump.c index 55b1a77884e250d..8f15ca39c585341 100644 --- a/arch/xtensa/core/coredump.c +++ b/arch/xtensa/core/coredump.c @@ -109,13 +109,13 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf) #if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER; - #elif CONFIG_SOC_ESP32 - arch_blk.soc = XTENSA_SOC_ESP32; #elif CONFIG_SOC_FAMILY_INTEL_ADSP arch_blk.soc = XTENSA_SOC_INTEL_ADSP; - #elif CONFIG_SOC_ESP32S2 + #elif CONFIG_SOC_SERIES_ESP32 + arch_blk.soc = XTENSA_SOC_ESP32; + #elif CONFIG_SOC_SERIES_ESP32S2 arch_blk.soc = XTENSA_SOC_ESP32S2; - #elif CONFIG_SOC_ESP32S3 + #elif CONFIG_SOC_SERIES_ESP32S3 arch_blk.soc = XTENSA_SOC_ESP32S3; #else arch_blk.soc = XTENSA_SOC_UNKNOWN; diff --git a/arch/xtensa/core/xtensa_backtrace.c b/arch/xtensa/core/xtensa_backtrace.c index 9b5af2e8753e1fd..4f767f6904235d7 100644 --- a/arch/xtensa/core/xtensa_backtrace.c +++ b/arch/xtensa/core/xtensa_backtrace.c @@ -7,7 +7,7 @@ #include "xtensa/corebits.h" #include "xtensa_backtrace.h" #include -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) #include "soc/soc_memory_layout.h" #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) #include "debug_helpers.h" @@ -34,7 +34,7 @@ static inline uint32_t z_xtensa_cpu_process_stack_pc(uint32_t pc) static inline bool z_xtensa_stack_ptr_is_sane(uint32_t sp) { -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) return esp_stack_ptr_is_sane(sp); #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) return intel_adsp_ptr_is_sane(sp); @@ -45,7 +45,7 @@ static inline bool z_xtensa_stack_ptr_is_sane(uint32_t sp) static inline bool z_xtensa_ptr_executable(const void *p) { -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) return esp_ptr_executable(p); #elif defined(CONFIG_SOC_FAMILY_INTEL_ADSP) return intel_adsp_ptr_executable(p); diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.board b/boards/riscv/esp32c3_devkitm/Kconfig.board index 3a4d97f35236eca..51f0f3957df987a 100644 --- a/boards/riscv/esp32c3_devkitm/Kconfig.board +++ b/boards/riscv/esp32c3_devkitm/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_ESP32C3_DEVKITM bool "ESP32C3 Devkit-M Board" - depends on SOC_ESP32C3 + depends on SOC_SERIES_ESP32C3 + +choice SOC_PART_NUMBER + default SOC_ESP32C3_MINI_N4 +endchoice diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig index 080bd50908d835c..1ca521d9d959155 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig +++ b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig @@ -1,11 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_BOARD_ESP32C3_DEVKITM=y -CONFIG_SOC_ESP32C3=y +CONFIG_SOC_SERIES_ESP32C3=y + CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 + CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/riscv/icev_wireless/icev_wireless_defconfig b/boards/riscv/icev_wireless/icev_wireless_defconfig index 78e4586e0864093..c5be5732a71be99 100644 --- a/boards/riscv/icev_wireless/icev_wireless_defconfig +++ b/boards/riscv/icev_wireless/icev_wireless_defconfig @@ -1,11 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_BOARD_ICEV_WIRELESS=y -CONFIG_SOC_ESP32C3=y +CONFIG_SOC_SERIES_ESP32C3=y + CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 + CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/riscv/stamp_c3/Kconfig.board b/boards/riscv/stamp_c3/Kconfig.board index 314bbeb0ce7d7c5..09ec15d63482957 100644 --- a/boards/riscv/stamp_c3/Kconfig.board +++ b/boards/riscv/stamp_c3/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_STAMP_C3 bool "M5Stack STAMP-C3 Board" - depends on SOC_ESP32C3 + depends on SOC_SERIES_ESP32C3 + +choice SOC_PART_NUMBER + default SOC_ESP32C3_FX4 +endchoice diff --git a/boards/riscv/stamp_c3/stamp_c3_defconfig b/boards/riscv/stamp_c3/stamp_c3_defconfig index 56515384f21fd99..3b5efc64fa11f11 100644 --- a/boards/riscv/stamp_c3/stamp_c3_defconfig +++ b/boards/riscv/stamp_c3/stamp_c3_defconfig @@ -1,12 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_BOARD_STAMP_C3=y -CONFIG_SOC_ESP32C3=y +CONFIG_SOC_SERIES_ESP32C3=y + CONFIG_MAIN_STACK_SIZE=2048 + CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 + CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/riscv/xiao_esp32c3/Kconfig.board b/boards/riscv/xiao_esp32c3/Kconfig.board index 28d520d15750c0c..f8a7e0ecb5b2acd 100644 --- a/boards/riscv/xiao_esp32c3/Kconfig.board +++ b/boards/riscv/xiao_esp32c3/Kconfig.board @@ -3,4 +3,8 @@ config BOARD_XIAO_ESP32C3 bool "XIAO ESP32C3 Board" - depends on SOC_ESP32C3 + depends on SOC_SERIES_ESP32C3 + +choice SOC_PART_NUMBER + default SOC_ESP32C3_FX4 +endchoice diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig b/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig index 28204464d8130c6..0dc868fa60a9340 100644 --- a/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig +++ b/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig @@ -1,11 +1,11 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_BOARD_XIAO_ESP32C3=y -CONFIG_SOC_ESP32C3=y +CONFIG_SOC_SERIES_ESP32C3=y + CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 + CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.board b/boards/xtensa/esp32_devkitc_wroom/Kconfig.board index ae0f2c2897b6ca0..5c3fa887b575534 100644 --- a/boards/xtensa/esp32_devkitc_wroom/Kconfig.board +++ b/boards/xtensa/esp32_devkitc_wroom/Kconfig.board @@ -3,4 +3,8 @@ config BOARD_ESP32_DEVKITC_WROOM bool "ESP32-DEVKITC-WROOM Development Board" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_WROOM_32UE_N4 +endchoice diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig index a5c32af0d88f2c4..ead6203b86e595b 100644 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig +++ b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig @@ -1,10 +1,8 @@ # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ESP32_DEVKITC_WROOM=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -12,11 +10,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.board b/boards/xtensa/esp32_devkitc_wrover/Kconfig.board index 0aa7ae576cc8901..b345a9dff448b26 100644 --- a/boards/xtensa/esp32_devkitc_wrover/Kconfig.board +++ b/boards/xtensa/esp32_devkitc_wrover/Kconfig.board @@ -3,4 +3,8 @@ config BOARD_ESP32_DEVKITC_WROVER bool "ESP32-DEVKITC-WROVER-E Development board" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_WROVER_E_N4R8 +endchoice diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig index 45db3662dcfab7a..ad08ccede28bd34 100644 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig +++ b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig @@ -1,10 +1,8 @@ # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ESP32_DEVKITC_WROVER=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -12,11 +10,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.board b/boards/xtensa/esp32_ethernet_kit/Kconfig.board index b4d48cc7f05c06e..28a8995bbdf287b 100644 --- a/boards/xtensa/esp32_ethernet_kit/Kconfig.board +++ b/boards/xtensa/esp32_ethernet_kit/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_ESP32_ETHERNET_KIT bool "ESP32-ETHERNET-KIT Development Board" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_WROVER_E_N4R8 +endchoice diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig index f5be5006b4c2934..a9c99bec06b74cd 100644 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig +++ b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ESP32_ETHERNET_KIT=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,11 +9,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32_net/Kconfig.board b/boards/xtensa/esp32_net/Kconfig.board index e7405295d4093e1..946a59dce7fbd85 100644 --- a/boards/xtensa/esp32_net/Kconfig.board +++ b/boards/xtensa/esp32_net/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_ESP32_NET bool "ESP32 Board configuration for APP_CPU" - depends on SOC_ESP32_NET + depends on SOC_SERIES_ESP32_NET + +choice SOC_PART_NUMBER + default SOC_ESP32_NET +endchoice diff --git a/boards/xtensa/esp32_net/esp32_net_defconfig b/boards/xtensa/esp32_net/esp32_net_defconfig index f7846c524029831..94fed73bc45988f 100644 --- a/boards/xtensa/esp32_net/esp32_net_defconfig +++ b/boards/xtensa/esp32_net/esp32_net_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ESP32_NET=y -CONFIG_SOC_ESP32_NET=y +CONFIG_SOC_SERIES_ESP32_NET=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,13 +9,7 @@ CONFIG_CONSOLE=n CONFIG_SERIAL=n CONFIG_UART_CONSOLE=n -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=n CONFIG_GPIO_ESP32=n -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - CONFIG_I2C=n -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.board b/boards/xtensa/esp32s2_franzininho/Kconfig.board index 3f78d5baf931e0f..7b52b4d88b12e19 100644 --- a/boards/xtensa/esp32s2_franzininho/Kconfig.board +++ b/boards/xtensa/esp32s2_franzininho/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_ESP32S2_FRANZININHO bool "ESP32S2 Franzininho Board" - depends on SOC_ESP32S2 + depends on SOC_SERIES_ESP32S2 + +choice SOC_PART_NUMBER + default SOC_ESP32S2_WROOM +endchoice diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig index 3a17ce5b5478420..6d95a2f5567bf41 100644 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig +++ b/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig @@ -1,20 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n CONFIG_BOARD_ESP32S2_FRANZININHO=y -CONFIG_SOC_ESP32S2=y +CONFIG_SOC_SERIES_ESP32S2=y + CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s2_saola/Kconfig.board b/boards/xtensa/esp32s2_saola/Kconfig.board index 5accd94308af76e..7d9e3a717ae2ed6 100644 --- a/boards/xtensa/esp32s2_saola/Kconfig.board +++ b/boards/xtensa/esp32s2_saola/Kconfig.board @@ -1,8 +1,10 @@ -# ESP32S2 saola board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 config BOARD_ESP32S2_SAOLA bool "ESP32S2 Saola Board" - depends on SOC_ESP32S2 + depends on SOC_SERIES_ESP32S2 + +choice SOC_PART_NUMBER + default SOC_ESP32S2_WROVER_N4R2 +endchoice diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig index f1402eace807d80..c7bacdd2ec6219e 100644 --- a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig +++ b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig @@ -1,20 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ESP32S2_SAOLA=y -CONFIG_SOC_ESP32S2=y +CONFIG_SOC_SERIES_ESP32S2=y + CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.board b/boards/xtensa/esp32s3_devkitm/Kconfig.board index 38d8db7a1127ea9..96de0fb06f76210 100644 --- a/boards/xtensa/esp32s3_devkitm/Kconfig.board +++ b/boards/xtensa/esp32s3_devkitm/Kconfig.board @@ -1,8 +1,11 @@ -# ESP32S3 DevKitM board configuration - # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 +# ESP32S3 DevKitM board configuration config BOARD_ESP32S3_DEVKITM bool "ESP32S3 DevKitM Board" - depends on SOC_ESP32S3 + depends on SOC_SERIES_ESP32S3 + +choice SOC_PART_NUMBER + default SOC_ESP32S3_MINI_N8 +endchoice diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig index 65acf1b660d0c5d..1f8b52aa3604bca 100644 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig +++ b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig @@ -1,14 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n CONFIG_BOARD_ESP32S3_DEVKITM=y -CONFIG_SOC_ESP32S3=y +CONFIG_SOC_SERIES_ESP32S3=y + CONFIG_MAIN_STACK_SIZE=2048 + CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n CONFIG_GPIO=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.board b/boards/xtensa/esp_wrover_kit/Kconfig.board index 7067d53cd5cd71c..eb255c7ec55f06b 100644 --- a/boards/xtensa/esp_wrover_kit/Kconfig.board +++ b/boards/xtensa/esp_wrover_kit/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_ESP_WROVER_KIT bool "ESP-WROVER-KIT Development Board" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_WROVER_E_N4R8 +endchoice diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig b/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig index 68ef048f0eb9b61..f2b8f7b663c22df 100644 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig +++ b/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ESP_WROVER_KIT=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,11 +9,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board b/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board index bd176b95089289a..b364fad83fdf065 100644 --- a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board +++ b/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_HELTEC_WIFI_LORA32 bool "HELTEC WiFi LoRa 32 (V2) Board" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_D0WD_V3 +endchoice diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig index 766659e89ba6f30..ac8cf88d7494468 100644 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig +++ b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_HELTEC_WIFI_LORA32=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,11 +9,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/m5stickc_plus/Kconfig.board b/boards/xtensa/m5stickc_plus/Kconfig.board index c034b8763ff7f09..91e31bc959521cb 100644 --- a/boards/xtensa/m5stickc_plus/Kconfig.board +++ b/boards/xtensa/m5stickc_plus/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_M5STICKC_PLUS bool "M5StickC PLUS Development Board" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_PICO_D4 +endchoice diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig b/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig index 071ce0845c4a72e..cc30c956bafd177 100644 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig +++ b/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_M5STICKC_PLUS=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,12 +9,5 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - CONFIG_I2C=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/odroid_go/Kconfig.board b/boards/xtensa/odroid_go/Kconfig.board index ad5a4838ba69871..f815a4e7e8823db 100644 --- a/boards/xtensa/odroid_go/Kconfig.board +++ b/boards/xtensa/odroid_go/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_ODROID_GO bool "ODROID-GO Game Kit" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_WROVER_E_N16R2 +endchoice diff --git a/boards/xtensa/odroid_go/odroid_go_defconfig b/boards/xtensa/odroid_go/odroid_go_defconfig index 4a88a4a3365e1f8..3bda04a1ed3a71e 100644 --- a/boards/xtensa/odroid_go/odroid_go_defconfig +++ b/boards/xtensa/odroid_go/odroid_go_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_ODROID_GO=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,14 +9,7 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y - # required to enable LCD backlight CONFIG_REGULATOR=y diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.board b/boards/xtensa/olimex_esp32_evb/Kconfig.board index 2b230816edc7780..7bb6c2295b79830 100644 --- a/boards/xtensa/olimex_esp32_evb/Kconfig.board +++ b/boards/xtensa/olimex_esp32_evb/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_OLIMEX_ESP32_EVB bool "Olimex ESP32-EVB" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 + +choice SOC_PART_NUMBER + default SOC_ESP32_WROVER_E_N8R2 +endchoice diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig index 20f21d98a2a9829..a89b387d08441e3 100644 --- a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig +++ b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n - CONFIG_BOARD_OLIMEX_ESP32_EVB=y -CONFIG_SOC_ESP32=y +CONFIG_SOC_SERIES_ESP32=y CONFIG_MAIN_STACK_SIZE=2048 @@ -11,11 +9,4 @@ CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n - CONFIG_GPIO=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.board b/boards/xtensa/xiao_esp32s3/Kconfig.board index aa4b08ecf0f06fe..99669d929e3f3a6 100644 --- a/boards/xtensa/xiao_esp32s3/Kconfig.board +++ b/boards/xtensa/xiao_esp32s3/Kconfig.board @@ -5,4 +5,8 @@ config BOARD_XIAO_ESP32S3 bool "XIAO ESP32S3 Board" - depends on SOC_ESP32S3 + depends on SOC_SERIES_ESP32S3 + +choice SOC_PART_NUMBER + default SOC_ESP32S3_WROOM_N8R8 +endchoice diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig b/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig index df75dd7d28367b4..978da251a5897be 100644 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig +++ b/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig @@ -1,14 +1,9 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_XTENSA_RESET_VECTOR=n CONFIG_BOARD_XIAO_ESP32S3=y -CONFIG_SOC_ESP32S3=y +CONFIG_SOC_SERIES_ESP32S3=y CONFIG_MAIN_STACK_SIZE=2048 CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y -CONFIG_XTENSA_USE_CORE_CRT1=n CONFIG_GPIO=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_CLOCK_CONTROL=y diff --git a/drivers/adc/adc_esp32.c b/drivers/adc/adc_esp32.c index 01bd54c32b5aa78..cbf64ea4c458ada 100644 --- a/drivers/adc/adc_esp32.c +++ b/drivers/adc/adc_esp32.c @@ -20,7 +20,7 @@ #include LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL); -#if CONFIG_SOC_ESP32 +#if CONFIG_SOC_SERIES_ESP32 #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH @@ -31,12 +31,12 @@ LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL); */ #define ADC_CLIP_MVOLT_11DB 2550 -#elif CONFIG_SOC_ESP32S2 +#elif CONFIG_SOC_SERIES_ESP32S2 #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_MAX_BITWIDTH -#elif CONFIG_SOC_ESP32C3 +#elif CONFIG_SOC_SERIES_ESP32C3 #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH @@ -165,14 +165,14 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s data->resolution[channel_id] = seq->resolution; -#if CONFIG_SOC_ESP32C3 +#if CONFIG_SOC_SERIES_ESP32C3 /* NOTE: nothing to set on ESP32C3 SoC */ if (conf->unit == ADC_UNIT_1) { adc1_config_width(ADC_WIDTH_BIT_DEFAULT); } #else adc_set_data_width(conf->unit, WIDTH_MASK(data->resolution[channel_id])); -#endif /* CONFIG_SOC_ESP32C3 */ +#endif /* CONFIG_SOC_SERIES_ESP32C3 */ /* Read raw value */ if (conf->unit == ADC_UNIT_1) { @@ -191,13 +191,13 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s /* Get corrected voltage output */ cal = cal_mv = esp_adc_cal_raw_to_voltage(reading, &data->chars[channel_id]); -#if CONFIG_SOC_ESP32 +#if CONFIG_SOC_SERIES_ESP32 if (data->attenuation[channel_id] == ADC_ATTEN_DB_11) { if (cal > ADC_CLIP_MVOLT_11DB) { cal = ADC_CLIP_MVOLT_11DB; } } -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ /* Fit according to selected attenuation */ atten_to_gain(data->attenuation[channel_id], &cal); diff --git a/drivers/bluetooth/hci/hci_esp32.c b/drivers/bluetooth/hci/hci_esp32.c index bdcdb7db99aa012..8dae220dd944d94 100644 --- a/drivers/bluetooth/hci/hci_esp32.c +++ b/drivers/bluetooth/hci/hci_esp32.c @@ -280,7 +280,7 @@ static int bt_esp32_ble_init(void) int ret; esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); -#if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_SERIES_ESP32) esp_bt_mode_t mode = ESP_BT_MODE_BTDM; #else esp_bt_mode_t mode = ESP_BT_MODE_BLE; diff --git a/drivers/can/can_esp32_twai.c b/drivers/can/can_esp32_twai.c index cd0d6bad6ec3c6c..0d745dccdbefe24 100644 --- a/drivers/can/can_esp32_twai.c +++ b/drivers/can/can_esp32_twai.c @@ -26,7 +26,7 @@ LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL); * The names with TWAI_ prefixes from Espressif reference manuals are used for these incompatible * registers. */ -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* TWAI_BUS_TIMING_0_REG is incompatible with CAN_SJA1000_BTR0 */ #define TWAI_BUS_TIMING_0_REG (6U) @@ -63,7 +63,7 @@ LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL); #define TWAI_CD_MASK GENMASK(2, 0) #define TWAI_CLOCK_OFF BIT(3) -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ struct can_esp32_twai_config { mm_reg_t base; @@ -71,10 +71,10 @@ struct can_esp32_twai_config { const struct device *clock_dev; const clock_control_subsys_t clock_subsys; int irq_source; -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* 32-bit variant of output clock divider register required for non-ESP32 MCUs */ uint32_t cdr32; -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ }; static uint8_t can_esp32_twai_read_reg(const struct device *dev, uint8_t reg) @@ -95,7 +95,7 @@ static void can_esp32_twai_write_reg(const struct device *dev, uint8_t reg, uint sys_write32(val & 0xFF, addr); } -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* * Required for newer ESP32-series MCUs which violate the original SJA1000 8-bit register size. @@ -157,7 +157,7 @@ static int can_esp32_twai_set_timing(const struct device *dev, const struct can_ return 0; } -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ static int can_esp32_twai_get_core_clock(const struct device *dev, uint32_t *rate) { @@ -205,7 +205,7 @@ static int can_esp32_twai_init(const struct device *dev) return err; } -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* * TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR for non-ESP32 MCUs * - TWAI_CD has length of 8 bits instead of 3 bits @@ -215,7 +215,7 @@ static int can_esp32_twai_init(const struct device *dev) * Overwrite with 32-bit register variant configured via devicetree. */ can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32); -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ esp_intr_alloc(twai_config->irq_source, 0, can_esp32_twai_isr, (void *)dev, NULL); @@ -227,11 +227,11 @@ const struct can_driver_api can_esp32_twai_driver_api = { .start = can_sja1000_start, .stop = can_sja1000_stop, .set_mode = can_sja1000_set_mode, -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 .set_timing = can_sja1000_set_timing, #else .set_timing = can_esp32_twai_set_timing, -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ .send = can_sja1000_send, .add_rx_filter = can_sja1000_add_rx_filter, .remove_rx_filter = can_sja1000_remove_rx_filter, @@ -244,7 +244,7 @@ const struct can_driver_api can_esp32_twai_driver_api = { .recover = can_sja1000_recover, #endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ .timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER, -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 .timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER, #else /* larger prescaler allowed for newer ESP32-series MCUs */ @@ -255,16 +255,16 @@ const struct can_driver_api can_esp32_twai_driver_api = { .phase_seg2 = 0x8, .prescaler = 0x2000, } -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ }; -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #define TWAI_CLKOUT_DIVIDER_MAX (14) #define TWAI_CDR32_INIT(inst) #else #define TWAI_CLKOUT_DIVIDER_MAX (490) #define TWAI_CDR32_INIT(inst) .cdr32 = CAN_ESP32_TWAI_DT_CDR_INST_GET(inst) -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ #define CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst) \ BUILD_ASSERT(COND_CODE_0(DT_INST_NODE_HAS_PROP(inst, clkout_divider), (1), \ @@ -295,7 +295,7 @@ const struct can_driver_api can_esp32_twai_driver_api = { CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_esp32_twai_config_##inst, \ can_esp32_twai_read_reg, can_esp32_twai_write_reg, \ CAN_SJA1000_OCR_OCMODE_BIPHASE, \ - COND_CODE_0(IS_ENABLED(CONFIG_SOC_ESP32), (0), \ + COND_CODE_0(IS_ENABLED(CONFIG_SOC_SERIES_ESP32), (0), \ (CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)))); \ \ static struct can_sja1000_data can_sja1000_data_##inst = \ diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index d7bda543bb2b466..ea8836d8d751edb 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -9,32 +9,32 @@ #define CPU_RESET_REASON RTC_SW_CPU_RESET -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6 #undef CPU_RESET_REASON #define CPU_RESET_REASON SW_CPU_RESET #include #include "esp32/rom/rtc.h" #include "soc/dport_reg.h" -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #include #include "esp32s2/rom/rtc.h" #include "soc/dport_reg.h" -#elif defined(CONFIG_SOC_ESP32S3) +#elif defined(CONFIG_SOC_SERIES_ESP32S3) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #include #include "esp32s3/rom/rtc.h" #include "soc/dport_reg.h" #include "esp32s3/clk.h" -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_SOC_SERIES_ESP32C3 #define DT_CPU_COMPAT espressif_riscv #include #include "esp32c3/rom/rtc.h" #include #include #include -#endif +#endif /* CONFIG_SOC_SERIES_ESP32xx */ #include "esp_rom_sys.h" #include @@ -55,14 +55,16 @@ struct esp32_clock_config { }; static uint8_t const xtal_freq[] = { -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) || defined(CONFIG_SOC_ESP32S3) +#if defined(CONFIG_SOC_SERIES_ESP32) || \ + defined(CONFIG_SOC_SERIES_ESP32_NET) || \ + defined(CONFIG_SOC_SERIES_ESP32S3) [ESP32_CLK_XTAL_24M] = 24, [ESP32_CLK_XTAL_26M] = 26, [ESP32_CLK_XTAL_40M] = 40, [ESP32_CLK_XTAL_AUTO] = 0 -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) [ESP32_CLK_XTAL_40M] = 40, -#elif defined(CONFIG_SOC_ESP32C3) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) [ESP32_CLK_XTAL_32M] = 32, [ESP32_CLK_XTAL_40M] = 40, #endif @@ -124,7 +126,7 @@ static int clock_control_esp32_get_rate(const struct device *dev, return 0; } -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk; @@ -217,9 +219,9 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32 */ -#if defined(CONFIG_SOC_ESP32S2) +#if defined(CONFIG_SOC_SERIES_ESP32S2) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk; @@ -321,9 +323,9 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32S2 */ -#if defined(CONFIG_SOC_ESP32S3) +#if defined(CONFIG_SOC_SERIES_ESP32S3) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; @@ -421,9 +423,9 @@ static void esp32_clock_perip_init(void) esp_rom_uart_tx_wait_idle(0); esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32S3 */ -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk; @@ -510,7 +512,7 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32C3 */ static int clock_control_esp32_init(const struct device *dev) { @@ -596,7 +598,7 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc), CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_esp32_api); -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency), "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); diff --git a/drivers/counter/counter_esp32_rtc.c b/drivers/counter/counter_esp32_rtc.c index 7b157414b57db3d..0b7e8bbbb27cc12 100644 --- a/drivers/counter/counter_esp32_rtc.c +++ b/drivers/counter/counter_esp32_rtc.c @@ -18,7 +18,7 @@ #include #include -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) #include #else #include @@ -27,7 +27,7 @@ #include LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL); -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) #define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t #else #define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t @@ -88,7 +88,7 @@ static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks) ARG_UNUSED(dev); SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { /* might take 1 RTC slowclk period, don't flood RTC bus */ k_sleep(K_USEC(1)); diff --git a/drivers/counter/counter_esp32_tmr.c b/drivers/counter/counter_esp32_tmr.c index d664aed46fc56a8..77890f5e8fba47c 100644 --- a/drivers/counter/counter_esp32_tmr.c +++ b/drivers/counter/counter_esp32_tmr.c @@ -17,7 +17,7 @@ #include #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -26,7 +26,7 @@ #include LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL); -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t diff --git a/drivers/dma/dma_esp32_gdma.c b/drivers/dma/dma_esp32_gdma.c index fc3116bfe49369e..588b3fe9414ec16 100644 --- a/drivers/dma/dma_esp32_gdma.c +++ b/drivers/dma/dma_esp32_gdma.c @@ -21,13 +21,13 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL); #include #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include #endif -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t @@ -53,7 +53,7 @@ struct dma_esp32_channel { dma_callback_t cb; void *user_data; dma_descriptor_t desc; -#if defined(CONFIG_SOC_ESP32S3) +#if defined(CONFIG_SOC_SERIES_ESP32S3) struct intr_handle_data_t *intr_handle; #endif }; @@ -120,7 +120,7 @@ static void IRAM_ATTR dma_esp32_isr_handle(const struct device *dev, uint8_t rx_ } } -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) static int dma_esp32_enable_interrupt(const struct device *dev, struct dma_esp32_channel *dma_channel) { @@ -467,7 +467,7 @@ static int dma_esp32_reload(const struct device *dev, uint32_t channel, uint32_t return 0; } -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) static int dma_esp32_configure_irq(const struct device *dev) { struct dma_esp32_config *config = (struct dma_esp32_config *)dev->config; diff --git a/drivers/ethernet/Kconfig.esp32 b/drivers/ethernet/Kconfig.esp32 index e919e10b707997b..8adb24cfb7716bb 100644 --- a/drivers/ethernet/Kconfig.esp32 +++ b/drivers/ethernet/Kconfig.esp32 @@ -5,7 +5,7 @@ menuconfig ETH_ESP32 bool "ESP32 Ethernet driver" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 select MDIO help Enable ESP32 Ethernet driver. diff --git a/drivers/flash/flash_esp32.c b/drivers/flash/flash_esp32.c index a7c13b332cbf318..419daa342ff700a 100644 --- a/drivers/flash/flash_esp32.c +++ b/drivers/flash/flash_esp32.c @@ -30,20 +30,20 @@ #include #include -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) #include "soc/dport_reg.h" #include "esp32/rom/cache.h" #include "esp32/rom/spi_flash.h" #include "esp32/spiram.h" -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) #include "soc/spi_mem_reg.h" #include "esp32s2/rom/cache.h" #include "esp32s2/rom/spi_flash.h" -#elif defined(CONFIG_SOC_ESP32S3) +#elif defined(CONFIG_SOC_SERIES_ESP32S3) #include "soc/spi_mem_reg.h" #include "esp32s3/rom/cache.h" #include "esp32s3/rom/spi_flash.h" -#elif defined(CONFIG_SOC_ESP32C3) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) #include "soc/spi_periph.h" #include "soc/spi_mem_reg.h" #include "soc/dport_access.h" diff --git a/drivers/gpio/gpio_esp32.c b/drivers/gpio/gpio_esp32.c index e67ffd33fee0a58..3851200b1813022 100644 --- a/drivers/gpio/gpio_esp32.c +++ b/drivers/gpio/gpio_esp32.c @@ -20,7 +20,7 @@ #include #include #include -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -33,7 +33,7 @@ #include LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL); -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 /* gpio structs in esp32c3 series are different from xtensa ones */ #define out out.data #define in in.data diff --git a/drivers/hwinfo/hwinfo_esp32.c b/drivers/hwinfo/hwinfo_esp32.c index fd466c32704a501..df4d67321120d8e 100644 --- a/drivers/hwinfo/hwinfo_esp32.c +++ b/drivers/hwinfo/hwinfo_esp32.c @@ -15,7 +15,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { -#if !defined(CONFIG_SOC_ESP32) && !defined(CONFIG_SOC_ESP32_NET) +#if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32_NET) uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG); uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG); #else diff --git a/drivers/i2c/i2c_esp32.c b/drivers/i2c/i2c_esp32.c index 267c49793e4a447..0730fd1a6d6323b 100644 --- a/drivers/i2c/i2c_esp32.c +++ b/drivers/i2c/i2c_esp32.c @@ -255,7 +255,7 @@ static void IRAM_ATTR i2c_esp32_configure_timeout(const struct device *dev) * at least for ESP32-C3 (tested with communication to bq76952 chip). So we set the * timeout to maximum supported value instead. */ -#if defined(CONFIG_SOC_ESP32C3) || defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32) i2c_hal_set_tout(&data->hal, I2C_LL_MAX_TIMEOUT); #else i2c_hal_set_tout_en(&data->hal, 0); diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32 index 6080dcbc318e986..dd8599bfbd22e5d 100644 --- a/drivers/interrupt_controller/Kconfig.esp32 +++ b/drivers/interrupt_controller/Kconfig.esp32 @@ -5,7 +5,7 @@ config INTC_ESP32 bool "Interrupt allocator for Xtensa-based Espressif SoCs" - default y if SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32_NET || SOC_ESP32S3 + default y if SOC_FAMILY_ESP32 && !SOC_SERIES_ESP32C3 help Enable custom interrupt allocator for Espressif SoCs based on Xtensa architecture. diff --git a/drivers/interrupt_controller/Kconfig.esp32c3 b/drivers/interrupt_controller/Kconfig.esp32c3 index dfcb0f06f992dba..c6d4b7da88f6fac 100644 --- a/drivers/interrupt_controller/Kconfig.esp32c3 +++ b/drivers/interrupt_controller/Kconfig.esp32c3 @@ -3,7 +3,7 @@ config INTC_ESP32C3 bool "ESP32C3 interrupt controller driver" - depends on SOC_ESP32C3 + depends on SOC_SERIES_ESP32C3 default y help Enables the esp32c3 interrupt controller driver to handle ISR diff --git a/drivers/mdio/Kconfig.esp32 b/drivers/mdio/Kconfig.esp32 index 39c98eaa3bd92d1..bdc8fb1221eee82 100644 --- a/drivers/mdio/Kconfig.esp32 +++ b/drivers/mdio/Kconfig.esp32 @@ -3,7 +3,7 @@ config MDIO_ESP32 bool "ESP32 MDIO driver" - depends on SOC_ESP32 + depends on SOC_SERIES_ESP32 default y help Enable ESP32 MCU Family MDIO driver. diff --git a/drivers/pinctrl/pinctrl_esp32.c b/drivers/pinctrl/pinctrl_esp32.c index d716dd4defa4131..ee3811604511e94 100644 --- a/drivers/pinctrl/pinctrl_esp32.c +++ b/drivers/pinctrl/pinctrl_esp32.c @@ -12,7 +12,7 @@ #include #include -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 /* gpio structs in esp32c3 series are different from xtensa ones */ #define out out.data #define in in.data diff --git a/drivers/sensor/esp32_temp/Kconfig b/drivers/sensor/esp32_temp/Kconfig index 93568b416a9e707..22f31ed86253cbd 100644 --- a/drivers/sensor/esp32_temp/Kconfig +++ b/drivers/sensor/esp32_temp/Kconfig @@ -5,6 +5,6 @@ config ESP32_TEMP bool "ESP32 Temperature Sensor" default y depends on DT_HAS_ESPRESSIF_ESP32_TEMP_ENABLED - depends on !SOC_ESP32 + depends on !SOC_SERIES_ESP32 help Enable driver for temperature sensor on certain ESP targets. diff --git a/drivers/sensor/esp32_temp/esp32_temp.c b/drivers/sensor/esp32_temp/esp32_temp.c index 1ceb13bde088329..5deaecc3430fabe 100644 --- a/drivers/sensor/esp32_temp/esp32_temp.c +++ b/drivers/sensor/esp32_temp/esp32_temp.c @@ -16,7 +16,7 @@ #include LOG_MODULE_REGISTER(esp32_temp, CONFIG_SENSOR_LOG_LEVEL); -#if CONFIG_SOC_ESP32 +#if CONFIG_SOC_SERIES_ESP32 #error "Temperature sensor not supported on ESP32" #endif /* CONFIG_IDF_TARGET_ESP32 */ diff --git a/drivers/sensor/pcnt_esp32/pcnt_esp32.c b/drivers/sensor/pcnt_esp32/pcnt_esp32.c index 21da92897356cc3..487e1352156a83c 100644 --- a/drivers/sensor/pcnt_esp32/pcnt_esp32.c +++ b/drivers/sensor/pcnt_esp32/pcnt_esp32.c @@ -29,12 +29,12 @@ LOG_MODULE_REGISTER(pcnt_esp32, CONFIG_SENSOR_LOG_LEVEL); #define PCNT_INTR_UNIT_1 BIT(1) #define PCNT_INTR_UNIT_2 BIT(2) #define PCNT_INTR_UNIT_3 BIT(3) -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #define PCNT_INTR_UNIT_4 BIT(4) #define PCNT_INTR_UNIT_5 BIT(5) #define PCNT_INTR_UNIT_6 BIT(6) #define PCNT_INTR_UNIT_7 BIT(7) -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ #ifdef CONFIG_PCNT_ESP32_TRIGGER #define PCNT_INTR_THRES_1 BIT(2) @@ -293,7 +293,7 @@ static void IRAM_ATTR pcnt_esp32_isr(const struct device *dev) pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 2); } else if (pcnt_intr_status & PCNT_INTR_UNIT_3) { pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 3); -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 } else if (pcnt_intr_status & PCNT_INTR_UNIT_4) { pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 4); } else if (pcnt_intr_status & PCNT_INTR_UNIT_5) { @@ -302,7 +302,7 @@ static void IRAM_ATTR pcnt_esp32_isr(const struct device *dev) pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 6); } else if (pcnt_intr_status & PCNT_INTR_UNIT_7) { pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 7); -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ } else { return; } diff --git a/drivers/serial/Kconfig.esp32 b/drivers/serial/Kconfig.esp32 index 729d61b35ff9cd6..f6fa5ac9d937e33 100644 --- a/drivers/serial/Kconfig.esp32 +++ b/drivers/serial/Kconfig.esp32 @@ -7,7 +7,7 @@ config UART_ESP32 depends on DT_HAS_ESPRESSIF_ESP32_UART_ENABLED select SERIAL_HAS_DRIVER select SERIAL_SUPPORT_INTERRUPT - select SERIAL_SUPPORT_ASYNC if (SOC_ESP32C3 || SOC_ESP32S3) + select SERIAL_SUPPORT_ASYNC if (SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32S3) select GPIO_ESP32 help Enable the ESP32 UART. diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c index a1054ba7d853962..6608d91a44ade37 100644 --- a/drivers/serial/uart_esp32.c +++ b/drivers/serial/uart_esp32.c @@ -9,19 +9,19 @@ /* Include esp-idf headers first to avoid redefining BIT() macro */ /* TODO: include w/o prefix */ -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #include #include #include -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) #include #include #include -#elif defined(CONFIG_SOC_ESP32S3) +#elif defined(CONFIG_SOC_SERIES_ESP32S3) #include #include #include -#elif defined(CONFIG_SOC_ESP32C3) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) #include #include #include @@ -43,7 +43,7 @@ #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -55,7 +55,7 @@ #include LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL); -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t diff --git a/drivers/spi/spi_esp32_spim.c b/drivers/spi/spi_esp32_spim.c index 74b5d7c82b9b40e..3a1a5dc244a75b2 100644 --- a/drivers/spi/spi_esp32_spim.c +++ b/drivers/spi/spi_esp32_spim.c @@ -16,7 +16,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL); #include #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -29,7 +29,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL); #include "spi_context.h" #include "spi_esp32_spim.h" -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t @@ -180,11 +180,11 @@ static int spi_esp32_init_dma(const struct device *dev) #else channel_offset = 1; #endif /* SOC_GDMA_SUPPORTED */ -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 /*Connect SPI and DMA*/ DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, cfg->dma_host + 1, ((cfg->dma_host + 1) * 2)); -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ data->hal_config.dma_in = (spi_dma_dev_t *)cfg->spi; data->hal_config.dma_out = (spi_dma_dev_t *)cfg->spi; @@ -351,7 +351,7 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev, * Workaround for ESP32S3 and ESP32C3 SoC. This dummy transaction is needed to sync CLK and * software controlled CS when SPI is in mode 3 */ -#if defined(CONFIG_SOC_ESP32S3) || defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3) if (ctx->num_cs_gpios && (hal_dev->mode & (SPI_MODE_CPOL | SPI_MODE_CPHA))) { spi_esp32_transfer(dev); } @@ -463,7 +463,7 @@ static const struct spi_driver_api spi_api = { .release = spi_esp32_release }; -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #define GET_AS_CS(idx) .as_cs = DT_INST_PROP(idx, clk_as_cs), #else #define GET_AS_CS(idx) diff --git a/drivers/timer/Kconfig.esp32c3_sys b/drivers/timer/Kconfig.esp32c3_sys index 8bf5580c52bf2fd..366cfcd8526e79e 100644 --- a/drivers/timer/Kconfig.esp32c3_sys +++ b/drivers/timer/Kconfig.esp32c3_sys @@ -5,7 +5,7 @@ config ESP32C3_SYS_TIMER bool "ESP32C3 sys-timer support" - depends on SOC_ESP32C3 + depends on SOC_SERIES_ESP32C3 default y select TICKLESS_CAPABLE select TIMER_HAS_64BIT_CYCLE_COUNTER diff --git a/drivers/watchdog/wdt_esp32.c b/drivers/watchdog/wdt_esp32.c index c99c2b6f93a67fc..460f130c1b5f5f6 100644 --- a/drivers/watchdog/wdt_esp32.c +++ b/drivers/watchdog/wdt_esp32.c @@ -15,7 +15,7 @@ #include #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -25,7 +25,7 @@ #include LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL); -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t diff --git a/modules/Kconfig.esp32 b/modules/Kconfig.esp32 index 8c432032a9fa110..4022f7534b03244 100644 --- a/modules/Kconfig.esp32 +++ b/modules/Kconfig.esp32 @@ -3,4 +3,4 @@ config HAS_ESPRESSIF_HAL bool - depends on SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32C3 || SOC_ESP32_NET || SOC_ESP32S3 + depends on SOC_FAMILY_ESP32 diff --git a/samples/boards/esp32/flash_encryption/src/main.c b/samples/boards/esp32/flash_encryption/src/main.c index adbc6326bcef9cd..414376495ca1456 100644 --- a/samples/boards/esp32/flash_encryption/src/main.c +++ b/samples/boards/esp32/flash_encryption/src/main.c @@ -16,7 +16,7 @@ #include LOG_MODULE_REGISTER(flash_encryption, CONFIG_LOG_DEFAULT_LEVEL); -#if !defined(CONFIG_SOC_ESP32) +#if !defined(CONFIG_SOC_SERIES_ESP32) #error Flash encryption feature is only available for ESP32 SOC yet. #endif diff --git a/soc/riscv/esp32c3/Kconfig.defconfig b/soc/riscv/esp32c3/Kconfig.defconfig deleted file mode 100644 index adc9eca040ea2cd..000000000000000 --- a/soc/riscv/esp32c3/Kconfig.defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# ESP32C3 board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ESP32C3 - -if BOOTLOADER_MCUBOOT - -config HAS_FLASH_LOAD_OFFSET - default y - -config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - -config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - -config ROM_START_OFFSET - default 0x20 - -endif - -config SOC - default "esp32c3" - -config NUM_IRQS - default 62 - -config GEN_ISR_TABLES - default y - -config GEN_SW_ISR_TABLE - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config DYNAMIC_INTERRUPTS - default y - -config ISR_STACK_SIZE - default 2048 - -config ATOMIC_OPERATIONS_C - default y - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 16000000 - -endif diff --git a/soc/riscv/espressif_esp32/CMakeLists.txt b/soc/riscv/espressif_esp32/CMakeLists.txt new file mode 100644 index 000000000000000..31ef76aadeef99d --- /dev/null +++ b/soc/riscv/espressif_esp32/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/riscv/espressif_esp32/Kconfig b/soc/riscv/espressif_esp32/Kconfig new file mode 100644 index 000000000000000..a5012a706c47520 --- /dev/null +++ b/soc/riscv/espressif_esp32/Kconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ESP32 + bool + +if SOC_FAMILY_ESP32 + +config SOC_FAMILY + string + default "espressif_esp32" + +config SOC_PART_NUMBER + string + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +source "soc/riscv/espressif_esp32/common/Kconfig.soc" +source "soc/riscv/espressif_esp32/*/Kconfig.soc" + +endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/Kconfig.defconfig b/soc/riscv/espressif_esp32/Kconfig.defconfig new file mode 100644 index 000000000000000..ee9d04c4daba5ac --- /dev/null +++ b/soc/riscv/espressif_esp32/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/riscv/espressif_esp32/common/Kconfig.defconfig.series" +source "soc/riscv/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/riscv/espressif_esp32/Kconfig.soc b/soc/riscv/espressif_esp32/Kconfig.soc new file mode 100644 index 000000000000000..ce15ddcf10e3ab5 --- /dev/null +++ b/soc/riscv/espressif_esp32/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/riscv/espressif_esp32/*/Kconfig.series" diff --git a/soc/riscv/espressif_esp32/common/CMakeLists.txt b/soc/riscv/espressif_esp32/common/CMakeLists.txt new file mode 100644 index 000000000000000..9edbe85c8217b70 --- /dev/null +++ b/soc/riscv/espressif_esp32/common/CMakeLists.txt @@ -0,0 +1,2 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 diff --git a/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series new file mode 100644 index 000000000000000..a0a4b4f49432dc0 --- /dev/null +++ b/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series @@ -0,0 +1,52 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESP32 + +config GEN_ISR_TABLES + default y + +config GEN_SW_ISR_TABLE + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config DYNAMIC_INTERRUPTS + default y + +config ISR_STACK_SIZE + default 2048 + +config ATOMIC_OPERATIONS_C + default y + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 16000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config CLOCK_CONTROL + default y + +if BOOTLOADER_MCUBOOT + + config HAS_FLASH_LOAD_OFFSET + default y + config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + config ROM_START_OFFSET + default 0x20 + +endif # BOOTLOADER_MCUBOOT config + +endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/common/Kconfig.soc b/soc/riscv/espressif_esp32/common/Kconfig.soc new file mode 100644 index 000000000000000..5eb40f3b3405e85 --- /dev/null +++ b/soc/riscv/espressif_esp32/common/Kconfig.soc @@ -0,0 +1,15 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESP32 + +config ESPTOOLPY_FLASHFREQ_80M + bool + +config FLASH_SIZE + int + +config FLASH_BASE_ADDRESS + hex + +endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/esp32c3/CMakeLists.txt b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt similarity index 98% rename from soc/riscv/esp32c3/CMakeLists.txt rename to soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt index 49c3f57b9e89c84..8f27b8d9d3e6933 100644 --- a/soc/riscv/esp32c3/CMakeLists.txt +++ b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt @@ -39,7 +39,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF) ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} -S ${espidf_components_dir}/bootloader/subproject -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} -DPYTHON_DEPS_CHECKED=1 -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series new file mode 100644 index 000000000000000..50d52b3f5bfc3bc --- /dev/null +++ b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +config SOC_SERIES + default "esp32c3" + +config NUM_IRQS + default 62 + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series new file mode 100644 index 000000000000000..d506898f5b23629 --- /dev/null +++ b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series @@ -0,0 +1,20 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32C3 + bool "ESP32C3" + select RISCV + select RISCV_GP + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select HAS_ESPRESSIF_HAL + select SOC_FAMILY_ESP32 + select XIP if !MCUBOOT + select HAS_PM + help + Enable support for Espressif ESP32-C3 diff --git a/soc/riscv/esp32c3/Kconfig.soc b/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc similarity index 78% rename from soc/riscv/esp32c3/Kconfig.soc rename to soc/riscv/espressif_esp32/esp32c3/Kconfig.soc index 56d2a64a63ced8f..dce91fcc86a448e 100644 --- a/soc/riscv/esp32c3/Kconfig.soc +++ b/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc @@ -1,42 +1,28 @@ -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config SOC_ESP32C3 - bool "ESP32C3" - select RISCV - select RISCV_GP - select DYNAMIC_INTERRUPTS - select CLOCK_CONTROL - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select HAS_PM - -if SOC_ESP32C3 - -config SOC_FAMILY_ESP32 - bool - default y +if SOC_SERIES_ESP32C3 config IDF_TARGET_ESP32C3 bool "ESP32C3 as target board" default y -config ESPTOOLPY_FLASHFREQ_80M - bool - default y +choice SOC_PART_NUMBER + prompt "ESP32-C3 SOC Selection" + depends on SOC_SERIES_ESP32C3 -config FLASH_SIZE - int - default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + config SOC_ESP32C3 + bool "ESP32C3" + config SOC_ESP32C3_FX4 + bool "ESP32C3_FX4" + config SOC_ESP32C3_MINI_N4 + bool "ESP32C3_MINI_N4" + config SOC_ESP32C3_WROOM_H2 + bool "ESP32C3_MINI_N4" + config SOC_ESP32C3_WROOM_H4 + bool "ESP32C3_MINI_N4" -config FLASH_BASE_ADDRESS - hex - default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) +endchoice # SOC_PART_NUMBER config ESP_SYSTEM_RTC_EXT_XTAL bool @@ -64,7 +50,7 @@ config ESP32C3_RTC_CLK_SRC_EXT_OSC config ESP32C3_RTC_CLK_SRC_INT_8MD256 bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" -endchoice +endchoice # ESP32C3_RTC_CLK_SRC config ESP32C3_RTC_CLK_CAL_CYCLES int "Number of cycles for RTC_SLOW_CLK calibration" @@ -102,7 +88,7 @@ config ESP32_PHY_MAX_TX_POWER config MAC_BB_PD bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" - depends on SOC_ESP32C3 && TICKLESS_KERNEL + depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL default n help If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered @@ -110,4 +96,4 @@ config MAC_BB_PD by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only), 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth). -endif +endif # SOC_SERIES_ESP32C3 diff --git a/soc/riscv/esp32c3/default.ld b/soc/riscv/espressif_esp32/esp32c3/default.ld similarity index 100% rename from soc/riscv/esp32c3/default.ld rename to soc/riscv/espressif_esp32/esp32c3/default.ld diff --git a/soc/riscv/esp32c3/idle.c b/soc/riscv/espressif_esp32/esp32c3/idle.c similarity index 100% rename from soc/riscv/esp32c3/idle.c rename to soc/riscv/espressif_esp32/esp32c3/idle.c diff --git a/soc/riscv/esp32c3/linker.ld b/soc/riscv/espressif_esp32/esp32c3/linker.ld similarity index 100% rename from soc/riscv/esp32c3/linker.ld rename to soc/riscv/espressif_esp32/esp32c3/linker.ld diff --git a/soc/riscv/esp32c3/loader.c b/soc/riscv/espressif_esp32/esp32c3/loader.c similarity index 97% rename from soc/riscv/esp32c3/loader.c rename to soc/riscv/espressif_esp32/esp32c3/loader.c index bf1665d76eb3359..d4740fd23549eee 100644 --- a/soc/riscv/esp32c3/loader.c +++ b/soc/riscv/espressif_esp32/esp32c3/loader.c @@ -18,7 +18,7 @@ #ifdef CONFIG_BOOTLOADER_MCUBOOT #define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC "] [INF] " _fmt "\n\r", ##__VA_ARGS__) + ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) diff --git a/soc/riscv/esp32c3/mcuboot.ld b/soc/riscv/espressif_esp32/esp32c3/mcuboot.ld similarity index 100% rename from soc/riscv/esp32c3/mcuboot.ld rename to soc/riscv/espressif_esp32/esp32c3/mcuboot.ld diff --git a/soc/riscv/esp32c3/pinctrl_soc.h b/soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h similarity index 100% rename from soc/riscv/esp32c3/pinctrl_soc.h rename to soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h diff --git a/soc/riscv/esp32c3/power.c b/soc/riscv/espressif_esp32/esp32c3/power.c similarity index 100% rename from soc/riscv/esp32c3/power.c rename to soc/riscv/espressif_esp32/esp32c3/power.c diff --git a/soc/riscv/esp32c3/soc.c b/soc/riscv/espressif_esp32/esp32c3/soc.c similarity index 100% rename from soc/riscv/esp32c3/soc.c rename to soc/riscv/espressif_esp32/esp32c3/soc.c diff --git a/soc/riscv/esp32c3/soc.h b/soc/riscv/espressif_esp32/esp32c3/soc.h similarity index 100% rename from soc/riscv/esp32c3/soc.h rename to soc/riscv/espressif_esp32/esp32c3/soc.h diff --git a/soc/riscv/esp32c3/soc_irq.S b/soc/riscv/espressif_esp32/esp32c3/soc_irq.S similarity index 100% rename from soc/riscv/esp32c3/soc_irq.S rename to soc/riscv/espressif_esp32/esp32c3/soc_irq.S diff --git a/soc/riscv/esp32c3/soc_irq.c b/soc/riscv/espressif_esp32/esp32c3/soc_irq.c similarity index 100% rename from soc/riscv/esp32c3/soc_irq.c rename to soc/riscv/espressif_esp32/esp32c3/soc_irq.c diff --git a/soc/riscv/esp32c3/vectors.S b/soc/riscv/espressif_esp32/esp32c3/vectors.S similarity index 100% rename from soc/riscv/esp32c3/vectors.S rename to soc/riscv/espressif_esp32/esp32c3/vectors.S diff --git a/soc/xtensa/esp32/include/_soc_inthandlers.h b/soc/xtensa/esp32/include/_soc_inthandlers.h deleted file mode 100644 index 9d7e4b29b71407c..000000000000000 --- a/soc/xtensa/esp32/include/_soc_inthandlers.h +++ /dev/null @@ -1,365 +0,0 @@ -/* - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - * - * Functions here are designed to produce efficient code to - * search an Xtensa bitmask of interrupts, inspecting only those bits - * declared to be associated with a given interrupt level. Each - * dispatcher will handle exactly one flagged interrupt, in numerical - * order (low bits first) and will return a mask of that bit that can - * then be cleared by the calling code. Unrecognized bits for the - * level will invoke an error handler. - */ - -#include -#include -#include - -#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif - -static inline int _xtensa_handle_one_int1(unsigned int mask) -{ - int irq; - - if (mask & 0x7f) { - if (mask & 0x7) { - if (mask & BIT(0)) { - mask = BIT(0); - irq = 0; - goto handle_irq; - } - if (mask & BIT(1)) { - mask = BIT(1); - irq = 1; - goto handle_irq; - } - if (mask & BIT(2)) { - mask = BIT(2); - irq = 2; - goto handle_irq; - } - } else { - if (mask & 0x18) { - if (mask & BIT(3)) { - mask = BIT(3); - irq = 3; - goto handle_irq; - } - if (mask & BIT(4)) { - mask = BIT(4); - irq = 4; - goto handle_irq; - } - } else { - if (mask & BIT(5)) { - mask = BIT(5); - irq = 5; - goto handle_irq; - } - if (mask & BIT(6)) { - mask = BIT(6); - irq = 6; - goto handle_irq; - } - } - } - } else { - if (mask & 0x780) { - if (mask & 0x180) { - if (mask & BIT(7)) { - mask = BIT(7); - irq = 7; - goto handle_irq; - } - if (mask & BIT(8)) { - mask = BIT(8); - irq = 8; - goto handle_irq; - } - } else { - if (mask & BIT(9)) { - mask = BIT(9); - irq = 9; - goto handle_irq; - } - if (mask & BIT(10)) { - mask = BIT(10); - irq = 10; - goto handle_irq; - } - } - } else { - if (mask & 0x3000) { - if (mask & BIT(12)) { - mask = BIT(12); - irq = 12; - goto handle_irq; - } - if (mask & BIT(13)) { - mask = BIT(13); - irq = 13; - goto handle_irq; - } - } else { - if (mask & BIT(17)) { - mask = BIT(17); - irq = 17; - goto handle_irq; - } - if (mask & BIT(18)) { - mask = BIT(18); - irq = 18; - goto handle_irq; - } - } - } - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int3(unsigned int mask) -{ - int irq; - - if (mask & 0x408800) { - if (mask & BIT(11)) { - mask = BIT(11); - irq = 11; - goto handle_irq; - } - if (mask & BIT(15)) { - mask = BIT(15); - irq = 15; - goto handle_irq; - } - if (mask & BIT(22)) { - mask = BIT(22); - irq = 22; - goto handle_irq; - } - } else { - if (mask & BIT(23)) { - mask = BIT(23); - irq = 23; - goto handle_irq; - } - if (mask & BIT(27)) { - mask = BIT(27); - irq = 27; - goto handle_irq; - } - if (mask & BIT(29)) { - mask = BIT(29); - irq = 29; - goto handle_irq; - } - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int7(unsigned int mask) -{ - int irq; - - if (mask & BIT(14)) { - mask = BIT(14); - irq = 14; - goto handle_irq; - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int5(unsigned int mask) -{ - int irq; - - if (mask & BIT(16)) { - mask = BIT(16); - irq = 16; - goto handle_irq; - } - if (mask & BIT(26)) { - mask = BIT(26); - irq = 26; - goto handle_irq; - } - if (mask & BIT(31)) { - mask = BIT(31); - irq = 31; - goto handle_irq; - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int2(unsigned int mask) -{ - int irq; - - if (mask & BIT(19)) { - mask = BIT(19); - irq = 19; - goto handle_irq; - } - if (mask & BIT(20)) { - mask = BIT(20); - irq = 20; - goto handle_irq; - } - if (mask & BIT(21)) { - mask = BIT(21); - irq = 21; - goto handle_irq; - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int4(unsigned int mask) -{ - int irq; - - if (mask & 0x3000000) { - if (mask & BIT(24)) { - mask = BIT(24); - irq = 24; - goto handle_irq; - } - if (mask & BIT(25)) { - mask = BIT(25); - irq = 25; - goto handle_irq; - } - } else { - if (mask & BIT(28)) { - mask = BIT(28); - irq = 28; - goto handle_irq; - } - if (mask & BIT(30)) { - mask = BIT(30); - irq = 30; - goto handle_irq; - } - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int0(unsigned int mask) -{ - return 0; -} -static inline int _xtensa_handle_one_int6(unsigned int mask) -{ - return 0; -} diff --git a/soc/xtensa/esp32s2/Kconfig.defconfig b/soc/xtensa/esp32s2/Kconfig.defconfig deleted file mode 100644 index 24e829d5d43abfa..000000000000000 --- a/soc/xtensa/esp32s2/Kconfig.defconfig +++ /dev/null @@ -1,55 +0,0 @@ -# ESP32S2 board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ESP32S2 - -if BOOTLOADER_MCUBOOT - -config HAS_FLASH_LOAD_OFFSET - default y - -config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - -config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - -config ROM_START_OFFSET - default 0x20 - -endif - -config SOC - default "esp32s2" - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32s2" - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config ISR_STACK_SIZE - default 2048 - -config HEAP_MEM_POOL_SIZE - default 32768 - -config MP_MAX_NUM_CPUS - default 1 - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -endif diff --git a/soc/xtensa/esp32s2/include/_soc_inthandlers.h b/soc/xtensa/esp32s2/include/_soc_inthandlers.h deleted file mode 100644 index becafa7285a283e..000000000000000 --- a/soc/xtensa/esp32s2/include/_soc_inthandlers.h +++ /dev/null @@ -1,371 +0,0 @@ -/* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - * - * Functions here are designed to produce efficient code to - * search an Xtensa bitmask of interrupts, inspecting only those bits - * declared to be associated with a given interrupt level. Each - * dispatcher will handle exactly one flagged interrupt, in numerical - * order (low bits first) and will return a mask of that bit that can - * then be cleared by the calling code. Unrecognized bits for the - * level will invoke an error handler. - */ - -#include -#include -#include - -#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 1 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT22_LEVEL) || XCHAL_INT22_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT23_LEVEL) || XCHAL_INT23_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT27_LEVEL) || XCHAL_INT27_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT29_LEVEL) || XCHAL_INT29_LEVEL != 3 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 7 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT26_LEVEL) || XCHAL_INT26_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT31_LEVEL) || XCHAL_INT31_LEVEL != 5 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT21_LEVEL) || XCHAL_INT21_LEVEL != 2 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT24_LEVEL) || XCHAL_INT24_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT25_LEVEL) || XCHAL_INT25_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT28_LEVEL) || XCHAL_INT28_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif -#if !defined(XCHAL_INT30_LEVEL) || XCHAL_INT30_LEVEL != 4 -#error core-isa.h interrupt level does not match dispatcher! -#endif - -static inline int _xtensa_handle_one_int1(unsigned int mask) -{ - int irq; - - if (mask & 0x7f) { - if (mask & 0x7) { - if (mask & BIT(0)) { - mask = BIT(0); - irq = 0; - goto handle_irq; - } - if (mask & BIT(1)) { - mask = BIT(1); - irq = 1; - goto handle_irq; - } - if (mask & BIT(2)) { - mask = BIT(2); - irq = 2; - goto handle_irq; - } - } else { - if (mask & 0x18) { - if (mask & BIT(3)) { - mask = BIT(3); - irq = 3; - goto handle_irq; - } - if (mask & BIT(4)) { - mask = BIT(4); - irq = 4; - goto handle_irq; - } - } else { - if (mask & BIT(5)) { - mask = BIT(5); - irq = 5; - goto handle_irq; - } - if (mask & BIT(6)) { - mask = BIT(6); - irq = 6; - goto handle_irq; - } - } - } - } else { - if (mask & 0x780) { - if (mask & 0x180) { - if (mask & BIT(7)) { - mask = BIT(7); - irq = 7; - goto handle_irq; - } - if (mask & BIT(8)) { - mask = BIT(8); - irq = 8; - goto handle_irq; - } - } else { - if (mask & BIT(9)) { - mask = BIT(9); - irq = 9; - goto handle_irq; - } - if (mask & BIT(10)) { - mask = BIT(10); - irq = 10; - goto handle_irq; - } - } - } else { - if (mask & 0x3000) { - if (mask & BIT(12)) { - mask = BIT(12); - irq = 12; - goto handle_irq; - } - if (mask & BIT(13)) { - mask = BIT(13); - irq = 13; - goto handle_irq; - } - } else { - if (mask & BIT(17)) { - mask = BIT(17); - irq = 17; - goto handle_irq; - } - if (mask & BIT(18)) { - mask = BIT(18); - irq = 18; - goto handle_irq; - } - } - } - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int3(unsigned int mask) -{ - int irq; - - if (mask & 0x408800) { - if (mask & BIT(11)) { - mask = BIT(11); - irq = 11; - goto handle_irq; - } - if (mask & BIT(15)) { - mask = BIT(15); - irq = 15; - goto handle_irq; - } - if (mask & BIT(22)) { - mask = BIT(22); - irq = 22; - goto handle_irq; - } - } else { - if (mask & BIT(23)) { - mask = BIT(23); - irq = 23; - goto handle_irq; - } - if (mask & BIT(27)) { - mask = BIT(27); - irq = 27; - goto handle_irq; - } - if (mask & BIT(29)) { - mask = BIT(29); - irq = 29; - goto handle_irq; - } - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int7(unsigned int mask) -{ - int irq; - - if (mask & BIT(14)) { - mask = BIT(14); - irq = 14; - goto handle_irq; - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int5(unsigned int mask) -{ - int irq; - - if (mask & BIT(16)) { - mask = BIT(16); - irq = 16; - goto handle_irq; - } - if (mask & BIT(26)) { - mask = BIT(26); - irq = 26; - goto handle_irq; - } - if (mask & BIT(31)) { - mask = BIT(31); - irq = 31; - goto handle_irq; - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int2(unsigned int mask) -{ - int irq; - - if (mask & BIT(19)) { - mask = BIT(19); - irq = 19; - goto handle_irq; - } - if (mask & BIT(20)) { - mask = BIT(20); - irq = 20; - goto handle_irq; - } - if (mask & BIT(21)) { - mask = BIT(21); - irq = 21; - goto handle_irq; - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int4(unsigned int mask) -{ - int irq; - - if (mask & 0x3000000) { - if (mask & BIT(24)) { - mask = BIT(24); - irq = 24; - goto handle_irq; - } - if (mask & BIT(25)) { - mask = BIT(25); - irq = 25; - goto handle_irq; - } - } else { - if (mask & BIT(28)) { - mask = BIT(28); - irq = 28; - goto handle_irq; - } - if (mask & BIT(30)) { - mask = BIT(30); - irq = 30; - goto handle_irq; - } - } - return 0; -handle_irq: - _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); - return mask; -} - -static inline int _xtensa_handle_one_int0(unsigned int mask) -{ - return 0; -} -static inline int _xtensa_handle_one_int6(unsigned int mask) -{ - return 0; -} diff --git a/soc/xtensa/espressif_esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/CMakeLists.txt new file mode 100644 index 000000000000000..31ef76aadeef99d --- /dev/null +++ b/soc/xtensa/espressif_esp32/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/xtensa/espressif_esp32/Kconfig b/soc/xtensa/espressif_esp32/Kconfig new file mode 100644 index 000000000000000..31e176291ab8bca --- /dev/null +++ b/soc/xtensa/espressif_esp32/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ESP32 + bool + +if SOC_FAMILY_ESP32 + +config SOC_FAMILY + string + default "espressif_esp32" + +source "soc/xtensa/espressif_esp32/common/Kconfig.soc" +source "soc/xtensa/espressif_esp32/*/Kconfig.soc" + +endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/Kconfig.defconfig b/soc/xtensa/espressif_esp32/Kconfig.defconfig new file mode 100644 index 000000000000000..fedabb82b8c7491 --- /dev/null +++ b/soc/xtensa/espressif_esp32/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series" +source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/xtensa/espressif_esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/Kconfig.soc new file mode 100644 index 000000000000000..6b28e8008689524 --- /dev/null +++ b/soc/xtensa/espressif_esp32/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/xtensa/espressif_esp32/*/Kconfig.series" diff --git a/soc/xtensa/espressif_esp32/common/CMakeLists.txt b/soc/xtensa/espressif_esp32/common/CMakeLists.txt new file mode 100644 index 000000000000000..e097e8ce4eec43e --- /dev/null +++ b/soc/xtensa/espressif_esp32/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/esp32s3/Kconfig.defconfig b/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series similarity index 57% rename from soc/xtensa/esp32s3/Kconfig.defconfig rename to soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series index 864bc13515623a3..771976bc66d53c7 100644 --- a/soc/xtensa/esp32s3/Kconfig.defconfig +++ b/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series @@ -1,41 +1,44 @@ -# ESP32 board configuration - -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -if SOC_ESP32S3 +if SOC_FAMILY_ESP32 -if BOOTLOADER_MCUBOOT - config HAS_FLASH_LOAD_OFFSET - default y +# Xtensa default options for ESP32 family +config XTENSA_RESET_VECTOR + default n - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y +config XTENSA_USE_CORE_CRT1 + default n - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y +config GEN_ISR_TABLES + default y - config ROM_START_OFFSET - default 0x20 -endif +config GEN_IRQ_VECTOR_TABLE + default n -config SOC - default "esp32s3" +config CLOCK_CONTROL + default y -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32s3" +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) -config HEAP_MEM_POOL_SIZE - default 32768 +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE default n -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) +if BOOTLOADER_MCUBOOT -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC + config HAS_FLASH_LOAD_OFFSET + default y + config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + config ROM_START_OFFSET + default 0x20 + +endif # BOOTLOADER_MCUBOOT -endif +endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/common/Kconfig.soc b/soc/xtensa/espressif_esp32/common/Kconfig.soc new file mode 100644 index 000000000000000..4cf8bf9095f824d --- /dev/null +++ b/soc/xtensa/espressif_esp32/common/Kconfig.soc @@ -0,0 +1,194 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESP32 + +config ESPTOOLPY_FLASHFREQ_80M + bool + +config FLASH_SIZE + int + +config FLASH_BASE_ADDRESS + hex + +config ESP_SPIRAM + bool "Support for external, SPI-connected RAM" + help + This enables support for an external SPI RAM chip, connected in + parallel with the main SPI flash chip. + +config ESP_HEAP_MIN_EXTRAM_THRESHOLD + int "Minimum threshold for external RAM allocation" + default 8192 + range 1024 131072 + depends on ESP_SPIRAM + help + Threshold to decide if memory will be allocated from DRAM + or SPIRAM. If value of allocation size is less than this value, + memory will be allocated from internal RAM. + +config ESP_HEAP_SEARCH_ALL_REGIONS + bool "Search for all available heap regions" + depends on ESP_SPIRAM + default y + help + This configuration enables searching all available heap + regions. If the region of desired capability is exhausted, + memory will be allocated from other available region. + +menu "SPI RAM config" + depends on ESP_SPIRAM + +choice SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + depends on ESP_SPIRAM + default SPIRAM_TYPE_ESPPSRAM16 + +config SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" + +config SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" + +endchoice # SPIRAM_TYPE + +config ESP_SPIRAM_SIZE + int "Size of SPIRAM part" + default 2097152 if SPIRAM_TYPE_ESPPSRAM16 + default 4194304 if SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if SPIRAM_TYPE_ESPPSRAM64 + help + Specify size of SPIRAM part. + NOTE: If SPIRAM size is greater than 4MB, only + lower 4MB can be allocated using k_malloc(). + +choice SPIRAM_SPEED + prompt "Set RAM clock speed" + default SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: + + 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz + 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz + 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz + + Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host + will be occupied by the system. Which SPI host to use can be selected by the config item + SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The + option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. + (ESPTOOLPY_FLASHFREQ_79M is true) + +config SPIRAM_SPEED_26M + bool "26MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_20M + bool "20MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config SPIRAM_SPEED_80M + depends on ESPTOOLPY_FLASHFREQ_80M + bool "80MHz clock speed" + +endchoice # SPIRAM_SPEED + +menu "PSRAM clock and cs IO for ESP32-DOWD" + +config D0WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 17 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D0WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 16 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-DOWD + +menu "PSRAM clock and cs IO for ESP32-D2WD" + +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-D2WD + +menu "PSRAM clock and cs IO for ESP32-PICO" + +config PICO_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. + + For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock + IO. + For the reference hardware design, please refer to + https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endmenu # PSRAM clock and cs IO for ESP32-PICO + +config SPIRAM_CUSTOM_SPIWP_SD3_PIN + bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" + default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 + default n + help + This setting is only used if the SPI flash pins have been overridden by setting the eFuses + SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. + + When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka + ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI + mode, so a WP pin setting is necessary. + + If this config item is set to N (default), the correct WP pin will be automatically used for any + Espressif chip or module with integrated flash. If a custom setting is needed, set this config item + to Y and specify the GPIO number connected to the WP pin. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin + configured in the bootloader. + +config SPIRAM_SPIWP_SD3_PIN + int "Custom SPI PSRAM WP(SD3) Pin" + range 0 33 + default 7 + help + The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored + + If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this + value to the GPIO number of the SPIRAM WP pin. + +config SPIRAM + bool + default y + +endmenu # SPI RAM config + +endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/esp32s3/include/_soc_inthandlers.h b/soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h similarity index 99% rename from soc/xtensa/esp32s3/include/_soc_inthandlers.h rename to soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h index 6980643e71dd4a4..8e6b115bca3db89 100644 --- a/soc/xtensa/esp32s3/include/_soc_inthandlers.h +++ b/soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/soc/xtensa/esp32/include/gdbstub/soc.h b/soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h similarity index 100% rename from soc/xtensa/esp32/include/gdbstub/soc.h rename to soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h diff --git a/soc/xtensa/esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt similarity index 98% rename from soc/xtensa/esp32/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32/CMakeLists.txt index 0728e94e2535728..6c3039116cb476a 100644 --- a/soc/xtensa/esp32/CMakeLists.txt +++ b/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt @@ -40,7 +40,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF) ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} -S ${espidf_components_dir}/bootloader/subproject -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} -DPYTHON_DEPS_CHECKED=1 -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} diff --git a/soc/xtensa/esp32/Kconfig.defconfig b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series similarity index 56% rename from soc/xtensa/esp32/Kconfig.defconfig rename to soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series index 229f6fb02e7c8f1..50a7e9e8124f0a8 100644 --- a/soc/xtensa/esp32/Kconfig.defconfig +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series @@ -1,30 +1,28 @@ -# ESP32 board configuration - -# Copyright (c) 2017 Intel Corporation +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -if SOC_ESP32 +if SOC_SERIES_ESP32 -if BOOTLOADER_MCUBOOT - config HAS_FLASH_LOAD_OFFSET - default y +config SOC_SERIES + default "esp32" - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - config ROM_START_OFFSET - default 0x20 -endif +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC -config SOC - default "esp32" +config ESPTOOLPY_FLASHFREQ_80M + default y -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32" +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) if SMP @@ -37,16 +35,7 @@ config SCHED_CPU_MASK config MP_MAX_NUM_CPUS default 2 -endif - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC +endif # SMP config if GDBSTUB @@ -55,6 +44,6 @@ if GDBSTUB config GDBSTUB_BUF_SZ default 840 if GDBSTUB -endif +endif # GDBSTUB config -endif +endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.series b/soc/xtensa/espressif_esp32/esp32/Kconfig.series new file mode 100644 index 000000000000000..dce3176ed53c737 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.series @@ -0,0 +1,18 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32 + bool "ESP32 Series" + select XTENSA + select SOC_FAMILY_ESP32 + select CLOCK_CONTROL + select DYNAMIC_INTERRUPTS + select ARCH_HAS_GDBSTUB + select ARCH_SUPPORTS_COREDUMP + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + select HAS_PM + help + Enable support for Espressif ESP32 diff --git a/soc/xtensa/esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32/Kconfig.soc similarity index 56% rename from soc/xtensa/esp32/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32/Kconfig.soc index 9e4e0e6892f5ba7..7371c49ed9403f5 100644 --- a/soc/xtensa/esp32/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.soc @@ -1,40 +1,66 @@ -# Copyright (c) 2017 Intel Corporation +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config SOC_ESP32 - bool "ESP32" - select XTENSA - select CLOCK_CONTROL - select DYNAMIC_INTERRUPTS - select ARCH_HAS_GDBSTUB - select ARCH_SUPPORTS_COREDUMP - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - select HAS_PM - -if SOC_ESP32 - -config SOC_FAMILY_ESP32 - bool - default y +if SOC_SERIES_ESP32 config IDF_TARGET_ESP32 bool "ESP32 as target board" default y -config ESPTOOLPY_FLASHFREQ_80M - bool - default y +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32" + +choice SOC_PART_NUMBER + prompt "ESP32 SOC/SIP Selection" + depends on SOC_SERIES_ESP32 + + # SoC with/without embedded flash + config SOC_ESP32_D0WD_V3 + bool "ESP32_D0WD_V3" + config SOC_ESP32_D0WDR2_V3 + bool "ESP32_D0WDR2_V3" + config SOC_ESP32_U4WDH + bool "ESP32_U4WDH" + config SOC_ESP32_PICO_V3 + bool "ESP32_PICO_V3" + config SOC_ESP32_PICO_V3_02 + bool "ESP32_PICO_V3_02" + config SOC_ESP32_PICO_D4 + bool "ESP32_PICO_D4" + # SiP with external flash / psram + config SOC_ESP32_WROOM_DA_N4 + bool "ESP32_WROOM_DA_N4" + config SOC_ESP32_WROOM_DA_N8 + bool "ESP32_WROOM_DA_N8" + config SOC_ESP32_WROOM_DA_N16 + bool "ESP32_WROOM_DA_N16" + config SOC_ESP32_WROOM_32UE_N4 + bool "ESP32_WROOM_32UE_N4" + config SOC_ESP32_WROOM_32UE_N8 + bool "ESP32_WROOM_32UE_N8" + config SOC_ESP32_WROOM_32UE_N16 + bool "ESP32_WROOM_32UE_N16" + config SOC_ESP32_WROVER_E_N4R2 + bool "ESP32_WROVER_E_N4R2" + config SOC_ESP32_WROVER_E_N8R2 + bool "ESP32_WROVER_E_N8R2" + config SOC_ESP32_WROVER_E_N16R2 + bool "ESP32_WROVER_E_N16R2" + config SOC_ESP32_WROVER_E_N4R8 + bool "ESP32_WROVER_E_N4R8" + config SOC_ESP32_WROVER_E_N8R8 + bool "ESP32_WROVER_E_N8R8" + config SOC_ESP32_WROVER_E_N16R8 + bool "ESP32_WROVER_E_N16R8" + +endchoice # SOC_PART_NUMBER -config FLASH_SIZE - int - default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) +config ESP_SYSTEM_RTC_EXT_XTAL + bool -config FLASH_BASE_ADDRESS - hex - default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) +config ESP_SYSTEM_RTC_EXT_OSC + bool config ESP32_NETWORK_CORE bool "Uses the ESP32 APP_CPU as Network dedicated core" @@ -55,183 +81,6 @@ config ESP_HEAP_MEM_POOL_REGION_1_SIZE This configuration can be used to add memory from region 1 to heap and can be allocated using k_malloc. -config ESP_SPIRAM - bool "Support for external, SPI-connected RAM" - default n if MCUBOOT - help - This enables support for an external SPI RAM chip, connected in - parallel with the main SPI flash chip. - -config ESP_HEAP_MIN_EXTRAM_THRESHOLD - int "Minimum threshold for external RAM allocation" - default 8192 - range 1024 131072 - depends on ESP_SPIRAM - help - Threshold to decide if memory will be allocated from DRAM - or SPIRAM. If value of allocation size is less than this value, - memory will be allocated from internal RAM. - -config ESP_HEAP_SEARCH_ALL_REGIONS - bool "Search for all available heap regions" - depends on ESP_SPIRAM - default y - help - This configuration enables searching all available heap - regions. If the region of desired capability is exhausted, - memory will be allocated from other available region. - -menu "SPI RAM config" - depends on ESP_SPIRAM - -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE - -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz - 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz - 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz - - Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host - will be occupied by the system. Which SPI host to use can be selected by the config item - SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The - option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. - (ESPTOOLPY_FLASHFREQ_79M is true) - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_80M - depends on ESPTOOLPY_FLASHFREQ_80M - bool "80MHz clock speed" - -endchoice # SPIRAM_SPEED - -menu "PSRAM clock and cs IO for ESP32-DOWD" - -config D0WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 17 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D0WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 16 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-DOWD - -menu "PSRAM clock and cs IO for ESP32-D2WD" - -config D2WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 9 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D2WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-D2WD - -menu "PSRAM clock and cs IO for ESP32-PICO" - -config PICO_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - - For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock - IO. - For the reference hardware design, please refer to - https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf - -endmenu # PSRAM clock and cs IO for ESP32-PICO - -config SPIRAM_CUSTOM_SPIWP_SD3_PIN - bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" - default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 - default n - help - This setting is only used if the SPI flash pins have been overridden by setting the eFuses - SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. - - When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka - ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI - mode, so a WP pin setting is necessary. - - If this config item is set to N (default), the correct WP pin will be automatically used for any - Espressif chip or module with integrated flash. If a custom setting is needed, set this config item - to Y and specify the GPIO number connected to the WP pin. - - When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin - configured in the bootloader. - -config SPIRAM_SPIWP_SD3_PIN - int "Custom SPI PSRAM WP(SD3) Pin" - range 0 33 - default 7 - help - The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored - - If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this - value to the GPIO number of the SPIRAM WP pin. - -config SPIRAM - bool - default y - -endmenu # SPI RAM config - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - choice ESP32_RTC_CLK_SRC prompt "RTC clock source" default ESP32_RTC_CLK_SRC_INT_RC @@ -417,6 +266,6 @@ config ETH_DMA_TX_BUFFER_NUM Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. Larger number of buffers could increase throughput somehow. -endif # ESP32_EMAC +endif # ESP32_EMAC config -endif # SOC_ESP32 +endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/esp32/default.ld b/soc/xtensa/espressif_esp32/esp32/default.ld similarity index 100% rename from soc/xtensa/esp32/default.ld rename to soc/xtensa/espressif_esp32/esp32/default.ld diff --git a/soc/xtensa/esp32/esp32-mp.c b/soc/xtensa/espressif_esp32/esp32/esp32-mp.c similarity index 100% rename from soc/xtensa/esp32/esp32-mp.c rename to soc/xtensa/espressif_esp32/esp32/esp32-mp.c diff --git a/soc/xtensa/esp32/gdbstub.c b/soc/xtensa/espressif_esp32/esp32/gdbstub.c similarity index 100% rename from soc/xtensa/esp32/gdbstub.c rename to soc/xtensa/espressif_esp32/esp32/gdbstub.c diff --git a/soc/xtensa/esp32/linker.ld b/soc/xtensa/espressif_esp32/esp32/linker.ld similarity index 100% rename from soc/xtensa/esp32/linker.ld rename to soc/xtensa/espressif_esp32/esp32/linker.ld diff --git a/soc/xtensa/esp32/loader.c b/soc/xtensa/espressif_esp32/esp32/loader.c similarity index 97% rename from soc/xtensa/esp32/loader.c rename to soc/xtensa/espressif_esp32/esp32/loader.c index ed18aa8d02a386f..5b946bfba4156e4 100644 --- a/soc/xtensa/esp32/loader.c +++ b/soc/xtensa/espressif_esp32/esp32/loader.c @@ -16,7 +16,7 @@ #ifdef CONFIG_BOOTLOADER_MCUBOOT #define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC "] [INF] " _fmt "\n\r", ##__VA_ARGS__) + ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) diff --git a/soc/xtensa/esp32/mcuboot.ld b/soc/xtensa/espressif_esp32/esp32/mcuboot.ld similarity index 100% rename from soc/xtensa/esp32/mcuboot.ld rename to soc/xtensa/espressif_esp32/esp32/mcuboot.ld diff --git a/soc/xtensa/esp32/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32/newlib_fix.c diff --git a/soc/xtensa/esp32/pinctrl_soc.h b/soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h similarity index 100% rename from soc/xtensa/esp32/pinctrl_soc.h rename to soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h diff --git a/soc/xtensa/esp32/power.c b/soc/xtensa/espressif_esp32/esp32/power.c similarity index 100% rename from soc/xtensa/esp32/power.c rename to soc/xtensa/espressif_esp32/esp32/power.c diff --git a/soc/xtensa/esp32/soc.c b/soc/xtensa/espressif_esp32/esp32/soc.c similarity index 98% rename from soc/xtensa/esp32/soc.c rename to soc/xtensa/espressif_esp32/esp32/soc.c index cb1e3433fa8efc1..0f7537bacfc94d8 100644 --- a/soc/xtensa/esp32/soc.c +++ b/soc/xtensa/espressif_esp32/esp32/soc.c @@ -31,9 +31,9 @@ #include "esp_app_format.h" #include "hal/wdt_hal.h" -#ifndef CONFIG_SOC_ESP32_NET +#ifndef CONFIG_SOC_SERIES_ESP32_NET #include "esp_clk_internal.h" -#endif /* CONFIG_SOC_ESP32_NET */ +#endif /* CONFIG_SOC_SERIES_ESP32_NET */ #ifdef CONFIG_MCUBOOT #include "bootloader_init.h" @@ -135,7 +135,7 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); -#ifndef CONFIG_SOC_ESP32_NET +#ifndef CONFIG_SOC_SERIES_ESP32_NET /* Configures the CPU clock, RTC slow and fast clocks, and performs * RTC slow clock calibration. */ diff --git a/soc/xtensa/esp32/soc.h b/soc/xtensa/espressif_esp32/esp32/soc.h similarity index 100% rename from soc/xtensa/esp32/soc.h rename to soc/xtensa/espressif_esp32/esp32/soc.h diff --git a/soc/xtensa/esp32_net/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32_net/CMakeLists.txt similarity index 100% rename from soc/xtensa/esp32_net/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32_net/CMakeLists.txt diff --git a/soc/xtensa/esp32_net/Kconfig.defconfig b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.defconfig.series similarity index 56% rename from soc/xtensa/esp32_net/Kconfig.defconfig rename to soc/xtensa/espressif_esp32/esp32_net/Kconfig.defconfig.series index 7484769fb16051a..7c3c2ab7db14c40 100644 --- a/soc/xtensa/esp32_net/Kconfig.defconfig +++ b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.defconfig.series @@ -1,14 +1,13 @@ -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -if SOC_ESP32_NET +if SOC_SERIES_ESP32_NET -config SOC +config SOC_SERIES default "esp32_net" -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32" +config SOC_PART_NUMBER + default "esp32_net" config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE default n @@ -19,4 +18,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC config XTENSA_CCOUNT_HZ default SYS_CLOCK_HW_CYCLES_PER_SEC -endif +config ESPTOOLPY_FLASHFREQ_80M + default y + +endif # SOC_ESP32_NET diff --git a/soc/xtensa/espressif_esp32/esp32_net/Kconfig.series b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.series new file mode 100644 index 000000000000000..55f794f96e05677 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.series @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32_NET + bool "ESP32-NET Series" + select XTENSA + select SOC_FAMILY_ESP32 + select CLOCK_CONTROL + select DYNAMIC_INTERRUPTS + select HAS_ESPRESSIF_HAL + help + Enable support for Espressif ESP32_NET diff --git a/soc/xtensa/esp32_net/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.soc similarity index 88% rename from soc/xtensa/esp32_net/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32_net/Kconfig.soc index 3b735071700378e..975b777b7907689 100644 --- a/soc/xtensa/esp32_net/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.soc @@ -1,26 +1,25 @@ # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config SOC_ESP32_NET - bool "ESP32_NET" - select XTENSA - select CLOCK_CONTROL - select DYNAMIC_INTERRUPTS - select HAS_ESPRESSIF_HAL - -if SOC_ESP32_NET - -config SOC_FAMILY_ESP32 - bool - default y +if SOC_SERIES_ESP32_NET config IDF_TARGET_ESP32 bool "ESP32 as target board" default y -config ESPTOOLPY_FLASHFREQ_80M - bool - default y +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32" + +choice SOC_PART_NUMBER + prompt "ESP32-NET SOC Selection" + depends on SOC_SERIES_ESP32_NET + + # SoC with/without embedded flash + config SOC_ESP32_NET + bool "ESP32_NET" + +endchoice # SOC_PART_NUMBER config ESP32_BT_RESERVE_DRAM hex "Bluetooth controller reserved RAM region" @@ -76,4 +75,4 @@ config ESP32_UNIVERSAL_MAC_ADDRESSES default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR -endif # SOC_ESP32 +endif # SOC_ESP32_NET diff --git a/soc/xtensa/esp32_net/include/_soc_inthandlers.h b/soc/xtensa/espressif_esp32/esp32_net/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/esp32_net/include/_soc_inthandlers.h rename to soc/xtensa/espressif_esp32/esp32_net/include/_soc_inthandlers.h diff --git a/soc/xtensa/esp32_net/include/gdbstub/soc.h b/soc/xtensa/espressif_esp32/esp32_net/include/gdbstub/soc.h similarity index 100% rename from soc/xtensa/esp32_net/include/gdbstub/soc.h rename to soc/xtensa/espressif_esp32/esp32_net/include/gdbstub/soc.h diff --git a/soc/xtensa/esp32_net/linker.ld b/soc/xtensa/espressif_esp32/esp32_net/linker.ld similarity index 100% rename from soc/xtensa/esp32_net/linker.ld rename to soc/xtensa/espressif_esp32/esp32_net/linker.ld diff --git a/soc/xtensa/esp32_net/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32_net/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32_net/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32_net/newlib_fix.c diff --git a/soc/xtensa/esp32_net/soc.c b/soc/xtensa/espressif_esp32/esp32_net/soc.c similarity index 100% rename from soc/xtensa/esp32_net/soc.c rename to soc/xtensa/espressif_esp32/esp32_net/soc.c diff --git a/soc/xtensa/esp32_net/soc.h b/soc/xtensa/espressif_esp32/esp32_net/soc.h similarity index 100% rename from soc/xtensa/esp32_net/soc.h rename to soc/xtensa/espressif_esp32/esp32_net/soc.h diff --git a/soc/xtensa/esp32s2/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt similarity index 98% rename from soc/xtensa/esp32s2/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt index c520dabda273bd2..18cf77e3248fe19 100644 --- a/soc/xtensa/esp32s2/CMakeLists.txt +++ b/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt @@ -38,7 +38,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF) ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} -S ${espidf_components_dir}/bootloader/subproject -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} -DPYTHON_DEPS_CHECKED=1 -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series new file mode 100644 index 000000000000000..c1618783ae598cb --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series @@ -0,0 +1,33 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +config SOC_SERIES + default "esp32s2" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config MP_MAX_NUM_CPUS + default 1 + +config ISR_STACK_SIZE + default 2048 + +config HEAP_MEM_POOL_SIZE + default 32768 + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series new file mode 100644 index 000000000000000..88bdcf1a53aea37 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series @@ -0,0 +1,17 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S2 + bool "ESP32-S2 Series" + select XTENSA + select SOC_FAMILY_ESP32 + select ATOMIC_OPERATIONS_C + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select ARCH_SUPPORTS_COREDUMP + select HAS_PM + help + Enable support for Espressif ESP32-S2 diff --git a/soc/xtensa/esp32s2/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc similarity index 74% rename from soc/xtensa/esp32s2/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc index eef1a489ea2f5a3..85d190d6472b206 100644 --- a/soc/xtensa/esp32s2/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc @@ -1,39 +1,122 @@ -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config SOC_ESP32S2 - bool "ESP32S2" - select XTENSA - select ATOMIC_OPERATIONS_C - select DYNAMIC_INTERRUPTS - select CLOCK_CONTROL - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select ARCH_SUPPORTS_COREDUMP - select HAS_PM - -if SOC_ESP32S2 - -config SOC_FAMILY_ESP32 - bool - default y +if SOC_SERIES_ESP32S2 config IDF_TARGET_ESP32S2 - bool "ESP32S2 as target board" + bool "ESP32S2 as target SOC" default y -config ESPTOOLPY_FLASHFREQ_80M +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s2" + +choice SOC_PART_NUMBER + prompt "ESP32-S2 SOC Selection" + depends on SOC_SERIES_ESP32S2 + + # SoC with/without embedded flash + config SOC_ESP32S2 + bool "ESP32S2" + config SOC_ESP32S2_R2 + bool "ESP32S2_R2" + config SOC_ESP32S2_FH2 + bool "ESP32S2_FH2" + config SOC_ESP32S2_FH4 + bool "ESP32S2_FH4" + config SOC_ESP32S2_FN4R2 + bool "ESP32S2_FN4R2" + # SiP with external flash / psram + config SOC_ESP32S2_SOLO_N4 + bool "ESP32S2_SOLO_N4" + config SOC_ESP32S2_SOLO_N8 + bool "ESP32S2_SOLO_N8" + config SOC_ESP32S2_SOLO_N16 + bool "ESP32S2_SOLO_N16" + config SOC_ESP32S2_SOLO_N4R2 + bool "ESP32S2_SOLO_N4R2" + config SOC_ESP32S2_MINI_N4 + bool "ESP32S2_MINI_N4" + config SOC_ESP32S2_MINI_N4R2 + bool "ESP32S2_MINI_N4R2" + config SOC_ESP32S2_WROOM + bool "ESP32S2_WROOM" + config SOC_ESP32S2_WROVER_N4R2 + bool "ESP32S2_WROVER_N4R2" + config SOC_ESP32S2_WROVER_N8R2 + bool "ESP32S2_WROVER_N8R2" + config SOC_ESP32S2_WROVER_N16R2 + bool "ESP32S2_WROVER_N16R2" + +endchoice # SOC_PART_NUMBER + +config ESP_SYSTEM_RTC_EXT_XTAL bool - default y -config FLASH_SIZE - int - default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) +config ESP_SYSTEM_RTC_EXT_OSC + bool -config FLASH_BASE_ADDRESS - hex - default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) +choice ESP32S2_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S2_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 90kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 90kHz oscillator. It does not require external components. + +config ESP32S2_RTC_CLK_SRC_INT_RC + bool "Internal 90kHz RC oscillator" + +config ESP32S2_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32S2_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32S2_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice + +config ESP32S2_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 + default 576 if ESP32S2_RTC_CLK_SRC_INT_RC + range 0 125000 + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +menu "Cache config" choice prompt "Instruction cache line size" @@ -98,51 +181,9 @@ config ESP32S2_DATA_CACHE_SIZE default 0x4000 if ESP32S2_DATA_CACHE_16KB default 0x0000 -config ESP_SPIRAM - bool "Support for external, SPI-connected RAM" - help - This enables support for an external SPI RAM chip, connected in - parallel with the main SPI flash chip. - -config ESP_HEAP_MIN_EXTRAM_THRESHOLD - int "Minimum threshold for external RAM allocation" - default 8192 - range 1024 131072 - depends on ESP_SPIRAM - help - Threshold to decide if memory will be allocated from DRAM - or SPIRAM. If value of allocation size is less than this value, - memory will be allocated from internal RAM. - -menu "SPI RAM config" - depends on ESP_SPIRAM - -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE +endmenu # Cache config -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -menu "PSRAM clock and cs IO for ESP32S2" +menu "PSRAM clock and cs IO for ESP32-S2" depends on ESP_SPIRAM config DEFAULT_PSRAM_CLK_IO @@ -163,98 +204,6 @@ config DEFAULT_PSRAM_CS_IO endmenu # PSRAM clock and cs IO for ESP32S2 -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - -config SPIRAM_SPEED_80M - bool "80MHz clock speed" - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_26M - bool "26MHz clock speed" - -config SPIRAM_SPEED_20M - bool "20MHz clock speed" - -endchoice # SPIRAM_SPEED - -config SPIRAM - bool - default y - -endmenu # SPI RAM config - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32S2_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S2_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 90kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 90kHz oscillator. It does not require external components. - -config ESP32S2_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" - -config ESP32S2_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32S2_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32S2_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice - -config ESP32S2_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 - default 576 if ESP32S2_RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - choice ESP32S2_UNIVERSAL_MAC_ADDRESSES bool "Number of universally administered (by IEEE) MAC address" default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO @@ -274,7 +223,7 @@ choice ESP32S2_UNIVERSAL_MAC_ADDRESSES allocation of MAC addresses in this range (either 1 or 2 per device). config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - bool "Two" + bool "One" select ESP_MAC_ADDR_UNIVERSE_WIFI_STA config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO @@ -307,4 +256,4 @@ config ESP32_PHY_MAX_TX_POWER int default ESP32_PHY_MAX_WIFI_TX_POWER -endif # SOC_ESP32S2 +endif # SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/esp32s2/default.ld b/soc/xtensa/espressif_esp32/esp32s2/default.ld similarity index 100% rename from soc/xtensa/esp32s2/default.ld rename to soc/xtensa/espressif_esp32/esp32s2/default.ld diff --git a/soc/xtensa/esp32s2/linker.ld b/soc/xtensa/espressif_esp32/esp32s2/linker.ld similarity index 100% rename from soc/xtensa/esp32s2/linker.ld rename to soc/xtensa/espressif_esp32/esp32s2/linker.ld diff --git a/soc/xtensa/esp32s2/loader.c b/soc/xtensa/espressif_esp32/esp32s2/loader.c similarity index 100% rename from soc/xtensa/esp32s2/loader.c rename to soc/xtensa/espressif_esp32/esp32s2/loader.c diff --git a/soc/xtensa/esp32s2/mcuboot.ld b/soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld similarity index 100% rename from soc/xtensa/esp32s2/mcuboot.ld rename to soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld diff --git a/soc/xtensa/esp32s2/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32s2/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c diff --git a/soc/xtensa/esp32s2/pinctrl_soc.h b/soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h similarity index 100% rename from soc/xtensa/esp32s2/pinctrl_soc.h rename to soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h diff --git a/soc/xtensa/esp32s2/power.c b/soc/xtensa/espressif_esp32/esp32s2/power.c similarity index 100% rename from soc/xtensa/esp32s2/power.c rename to soc/xtensa/espressif_esp32/esp32s2/power.c diff --git a/soc/xtensa/esp32s2/soc.c b/soc/xtensa/espressif_esp32/esp32s2/soc.c similarity index 100% rename from soc/xtensa/esp32s2/soc.c rename to soc/xtensa/espressif_esp32/esp32s2/soc.c diff --git a/soc/xtensa/esp32s2/soc.h b/soc/xtensa/espressif_esp32/esp32s2/soc.h similarity index 100% rename from soc/xtensa/esp32s2/soc.h rename to soc/xtensa/espressif_esp32/esp32s2/soc.h diff --git a/soc/xtensa/esp32s2/soc_cache.c b/soc/xtensa/espressif_esp32/esp32s2/soc_cache.c similarity index 100% rename from soc/xtensa/esp32s2/soc_cache.c rename to soc/xtensa/espressif_esp32/esp32s2/soc_cache.c diff --git a/soc/xtensa/esp32s3/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt similarity index 98% rename from soc/xtensa/esp32s3/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt index 70cc633e7649509..87d717981592345 100644 --- a/soc/xtensa/esp32s3/CMakeLists.txt +++ b/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt @@ -36,7 +36,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF) ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} -S ${espidf_components_dir}/bootloader/subproject -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} -DPYTHON_DEPS_CHECKED=1 -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series new file mode 100644 index 000000000000000..31f7bdbff50cc94 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series @@ -0,0 +1,30 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +config SOC_SERIES + default "esp32s3" + +config HEAP_MEM_POOL_SIZE + default 32768 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series new file mode 100644 index 000000000000000..1265375c12a280a --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series @@ -0,0 +1,16 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S3 + bool "ESP32-S3 Series" + select XTENSA + select SOC_FAMILY_ESP32 + select DYNAMIC_INTERRUPTS + select ARCH_SUPPORTS_COREDUMP + select CLOCK_CONTROL + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + help + Enable support for Espressif ESP32-S3 diff --git a/soc/xtensa/esp32s3/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc similarity index 87% rename from soc/xtensa/esp32s3/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc index 3860bea328b4c68..7dd8fc4dddb83a6 100644 --- a/soc/xtensa/esp32s3/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc @@ -1,38 +1,54 @@ -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config SOC_ESP32S3 - bool "ESP32S3" - select XTENSA - select CLOCK_CONTROL - select DYNAMIC_INTERRUPTS - select ARCH_SUPPORTS_COREDUMP - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - -if SOC_ESP32S3 - -config SOC_FAMILY_ESP32 - bool - default y +if SOC_SERIES_ESP32S3 config IDF_TARGET_ESP32S3 - bool "ESP32S3 as target board" - default y - -config ESPTOOLPY_FLASHFREQ_80M - bool + bool "ESP32S3 as target SOC" default y -config FLASH_SIZE - int - default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) - -config FLASH_BASE_ADDRESS - hex - default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s3" + +choice SOC_PART_NUMBER + prompt "ESP32-S3 SOC Selection" + depends on SOC_SERIES_ESP32S3 + + # SoC with/without embedded flash + config SOC_ESP32S3 + bool "ESP32S3" + config SOC_ESP32S3_R2 + bool "ESP32S3_R2" + config SOC_ESP32S3_R8 + bool "ESP32S3_R8" + config SOC_ESP32S3_R8V + bool "ESP32S3_R8V" + config SOC_ESP32S3_FN8 + bool "ESP32S3_FN8" + config SOC_ESP32S3_PICO_N8R2 + bool "ESP32S3_PICO_N8R2" + config SOC_ESP32S3_PICO_N8R8 + bool "ESP32S3_PICO_N8R8" + # SiP with flash and/or psram + config SOC_ESP32S3_MINI_N8 + bool "ESP32S3_MINI_N8" + config SOC_ESP32S3_MINI_N4R2 + bool "ESP32S3_MINI_N4R2" + config SOC_ESP32S3_WROOM_N4 + bool "ESP32S3_WROOM_N4" + config SOC_ESP32S3_WROOM_N8 + bool "ESP32S3_WROOM_N8" + config SOC_ESP32S3_WROOM_N16 + bool "ESP32S3_WROOM_N16" + config SOC_ESP32S3_WROOM_N4R8 + bool "ESP32S3_WROOM_N4R8" + config SOC_ESP32S3_WROOM_N8R8 + bool "ESP32S3_WROOM_N8R8" + config SOC_ESP32S3_WROOM_N16R8 + bool "ESP32S3_WROOM_N16" + +endchoice # SOC_PART_NUMBER choice ESP32S3_RTC_CLK_SRC prompt "RTC clock source" @@ -268,7 +284,7 @@ config ESP32S3_DATA_CACHE_WRAP config MAC_BB_PD bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" - depends on SOC_ESP32S3 && TICKLESS_KERNEL + depends on SOC_SERIES_ESP32S3 && TICKLESS_KERNEL default n help If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered @@ -277,4 +293,4 @@ config MAC_BB_PD endmenu # Cache config -endif # SOC_ESP32S3 +endif # SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/esp32s3/default.ld b/soc/xtensa/espressif_esp32/esp32s3/default.ld similarity index 100% rename from soc/xtensa/esp32s3/default.ld rename to soc/xtensa/espressif_esp32/esp32s3/default.ld diff --git a/soc/xtensa/esp32s3/linker.ld b/soc/xtensa/espressif_esp32/esp32s3/linker.ld similarity index 100% rename from soc/xtensa/esp32s3/linker.ld rename to soc/xtensa/espressif_esp32/esp32s3/linker.ld diff --git a/soc/xtensa/esp32s3/loader.c b/soc/xtensa/espressif_esp32/esp32s3/loader.c similarity index 100% rename from soc/xtensa/esp32s3/loader.c rename to soc/xtensa/espressif_esp32/esp32s3/loader.c diff --git a/soc/xtensa/esp32s3/mcuboot.ld b/soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld similarity index 100% rename from soc/xtensa/esp32s3/mcuboot.ld rename to soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld diff --git a/soc/xtensa/esp32s3/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32s3/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c diff --git a/soc/xtensa/esp32s3/pinctrl_soc.h b/soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h similarity index 100% rename from soc/xtensa/esp32s3/pinctrl_soc.h rename to soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h diff --git a/soc/xtensa/esp32s3/soc.c b/soc/xtensa/espressif_esp32/esp32s3/soc.c similarity index 100% rename from soc/xtensa/esp32s3/soc.c rename to soc/xtensa/espressif_esp32/esp32s3/soc.c diff --git a/soc/xtensa/esp32s3/soc.h b/soc/xtensa/espressif_esp32/esp32s3/soc.h similarity index 100% rename from soc/xtensa/esp32s3/soc.h rename to soc/xtensa/espressif_esp32/esp32s3/soc.h diff --git a/soc/xtensa/esp32s3/soc_cache.c b/soc/xtensa/espressif_esp32/esp32s3/soc_cache.c similarity index 100% rename from soc/xtensa/esp32s3/soc_cache.c rename to soc/xtensa/espressif_esp32/esp32s3/soc_cache.c diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index 21f1b10960d7c0d..28b7ea541f2a0bd 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -55,8 +55,8 @@ #endif #if defined(CONFIG_BOARD_COLIBRI_IMX7D_M4) || defined(CONFIG_SOC_MK64F12) || \ - defined(CONFIG_SOC_MKW41Z4) || defined(CONFIG_SOC_ESP32S2) || \ - defined(CONFIG_SOC_ESP32S3) || defined(CONFIG_SOC_ESP32C3) + defined(CONFIG_SOC_MKW41Z4) || defined(CONFIG_SOC_SERIES_ESP32S2) || \ + defined(CONFIG_SOC_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3) #define DEFAULT_PERIOD_CYCLE 1024 #define DEFAULT_PULSE_CYCLE 512 #define DEFAULT_PERIOD_NSEC 2000000 diff --git a/tests/drivers/uart/uart_async_api/src/test_uart.h b/tests/drivers/uart/uart_async_api/src/test_uart.h index b6b5ee66f563556..cd9dd3162483096 100644 --- a/tests/drivers/uart/uart_async_api/src/test_uart.h +++ b/tests/drivers/uart/uart_async_api/src/test_uart.h @@ -21,6 +21,8 @@ #if DT_NODE_EXISTS(DT_NODELABEL(dut)) #define UART_NODE DT_NODELABEL(dut) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) +#define UART_NODE DT_NODELABEL(uart1) #else #define UART_NODE DT_CHOSEN(zephyr_console) #endif diff --git a/west.yml b/west.yml index ff83119fcc682f7..273acf78c383062 100644 --- a/west.yml +++ b/west.yml @@ -147,7 +147,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 322f6389e21d08845486b5ebe1a6e5cb077981b8 + revision: d5a8fc861136abe74f05f56fad5738477a9985d2 path: modules/hal/espressif west-commands: west/west-commands.yml groups: