diff --git a/boards/xtensa/esp32/esp32.dts b/boards/xtensa/esp32/esp32.dts index 2295d4ed43495e5..cf5c565f0d56094 100644 --- a/boards/xtensa/esp32/esp32.dts +++ b/boards/xtensa/esp32/esp32.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include "esp32-pinctrl.dtsi" / { diff --git a/dts/xtensa/espressif/esp32.dtsi b/dts/xtensa/espressif/esp32.dtsi index fafd33686899600..92654661506c89e 100644 --- a/dts/xtensa/espressif/esp32.dtsi +++ b/dts/xtensa/espressif/esp32.dtsi @@ -113,7 +113,7 @@ flash0: flash@0 { compatible = "soc-nv-flash"; - reg = <0 0x400000>; +/* reg = <0 0x400000>; */ erase-block-size = <4096>; write-block-size = <4>; }; diff --git a/dts/xtensa/espressif/esp32d0wd.dtsi b/dts/xtensa/espressif/esp32d0wd.dtsi new file mode 100644 index 000000000000000..0155d8b87ec36fd --- /dev/null +++ b/dts/xtensa/espressif/esp32d0wd.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +/* placeholder - this is part used in SiP modules + * and on some boards - flash/psram size needs to + * be specified on board level + */ diff --git a/dts/xtensa/espressif/esp32d0wdr2.dtsi b/dts/xtensa/espressif/esp32d0wdr2.dtsi new file mode 100644 index 000000000000000..1715406fc85cef7 --- /dev/null +++ b/dts/xtensa/espressif/esp32d0wdr2.dtsi @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" diff --git a/dts/xtensa/espressif/esp32d2wd.dtsi b/dts/xtensa/espressif/esp32d2wd.dtsi new file mode 100644 index 000000000000000..730dd8491cc5764 --- /dev/null +++ b/dts/xtensa/espressif/esp32d2wd.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x00000000 DT_SIZE_M(2)>; +}; diff --git a/dts/xtensa/espressif/esp32pico.dtsi b/dts/xtensa/espressif/esp32pico.dtsi new file mode 100644 index 000000000000000..3cb14be05c7e95f --- /dev/null +++ b/dts/xtensa/espressif/esp32pico.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x00000000 DT_SIZE_M(4)>; +}; diff --git a/dts/xtensa/espressif/esp32pico02.dtsi b/dts/xtensa/espressif/esp32pico02.dtsi new file mode 100644 index 000000000000000..6ec502ac7413548 --- /dev/null +++ b/dts/xtensa/espressif/esp32pico02.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x0 DT_SIZE_M(8)>; +}; diff --git a/dts/xtensa/espressif/esp32picod4.dtsi b/dts/xtensa/espressif/esp32picod4.dtsi new file mode 100644 index 000000000000000..be6688d104f14e2 --- /dev/null +++ b/dts/xtensa/espressif/esp32picod4.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; diff --git a/dts/xtensa/espressif/esp32u4wdh.dtsi b/dts/xtensa/espressif/esp32u4wdh.dtsi new file mode 100644 index 000000000000000..be6688d104f14e2 --- /dev/null +++ b/dts/xtensa/espressif/esp32u4wdh.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; diff --git a/dts/xtensa/espressif/esp32wroom.dtsi b/dts/xtensa/espressif/esp32wroom.dtsi new file mode 100644 index 000000000000000..be6688d104f14e2 --- /dev/null +++ b/dts/xtensa/espressif/esp32wroom.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; diff --git a/dts/xtensa/espressif/esp32wrover.dtsi b/dts/xtensa/espressif/esp32wrover.dtsi new file mode 100644 index 000000000000000..be6688d104f14e2 --- /dev/null +++ b/dts/xtensa/espressif/esp32wrover.dtsi @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp32.dtsi" + +&flash0 { + reg = <0x0 DT_SIZE_M(4)>; +}; diff --git a/soc/riscv/espressif_esp32/CMakeLists.txt b/soc/riscv/espressif_esp32/CMakeLists.txt new file mode 100644 index 000000000000000..d6608bf5f6d0e49 --- /dev/null +++ b/soc/riscv/espressif_esp32/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) +#add_subdirectory(common) +#zephyr_include_directories(common) diff --git a/soc/riscv/espressif_esp32/Kconfig b/soc/riscv/espressif_esp32/Kconfig new file mode 100644 index 000000000000000..150fa0cd8bacd60 --- /dev/null +++ b/soc/riscv/espressif_esp32/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2023 Espressif +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ESP32 + bool + +if SOC_FAMILY_ESP32 + +config SOC_FAMILY + string + default "espressif_esp32" + +source "soc/riscv/espressif_esp32/*/Kconfig.soc" + +endif # SOC_FAMILY_ESP32 + diff --git a/soc/riscv/espressif_esp32/Kconfig.defconfig b/soc/riscv/espressif_esp32/Kconfig.defconfig new file mode 100644 index 000000000000000..b5232ae4579b6e5 --- /dev/null +++ b/soc/riscv/espressif_esp32/Kconfig.defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +source "soc/arm/st_stm32/*/Kconfig.defconfig.series" diff --git a/soc/riscv/espressif_esp32/Kconfig.soc b/soc/riscv/espressif_esp32/Kconfig.soc new file mode 100644 index 000000000000000..b9ea04e5b1c8247 --- /dev/null +++ b/soc/riscv/espressif_esp32/Kconfig.soc @@ -0,0 +1,6 @@ +# ST Microelectronics STM32 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/arm/st_stm32/*/Kconfig.series" diff --git a/soc/riscv/esp32c3/CMakeLists.txt b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt similarity index 100% rename from soc/riscv/esp32c3/CMakeLists.txt rename to soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt diff --git a/soc/riscv/esp32c3/Kconfig.defconfig b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig similarity index 100% rename from soc/riscv/esp32c3/Kconfig.defconfig rename to soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series new file mode 100644 index 000000000000000..7431522e867ebd3 --- /dev/null +++ b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series @@ -0,0 +1,50 @@ +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NXP_IMX8 + +config SOC_SERIES + string + default "imx8" + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx_adsp" + +config SOC + string + default "nxp_imx8" + +config SMP + default n + +config XTENSA_TIMER + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 666000000 if XTENSA_TIMER + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +config DYNAMIC_INTERRUPTS + default y + +config LOG + default y + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_SERIES_NXP_IMX8 diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series new file mode 100644 index 000000000000000..396607a484709ca --- /dev/null +++ b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series @@ -0,0 +1,13 @@ +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NXP_IMX8 + bool "NXP i.MX8" + select SOC_FAMILY_NXP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + help + NXP i.MX8 diff --git a/soc/riscv/esp32c3/Kconfig.soc b/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc similarity index 100% rename from soc/riscv/esp32c3/Kconfig.soc rename to soc/riscv/espressif_esp32/esp32c3/Kconfig.soc diff --git a/soc/riscv/esp32c3/default.ld b/soc/riscv/espressif_esp32/esp32c3/default.ld similarity index 100% rename from soc/riscv/esp32c3/default.ld rename to soc/riscv/espressif_esp32/esp32c3/default.ld diff --git a/soc/riscv/esp32c3/idle.c b/soc/riscv/espressif_esp32/esp32c3/idle.c similarity index 100% rename from soc/riscv/esp32c3/idle.c rename to soc/riscv/espressif_esp32/esp32c3/idle.c diff --git a/soc/riscv/esp32c3/linker.ld b/soc/riscv/espressif_esp32/esp32c3/linker.ld similarity index 100% rename from soc/riscv/esp32c3/linker.ld rename to soc/riscv/espressif_esp32/esp32c3/linker.ld diff --git a/soc/riscv/esp32c3/loader.c b/soc/riscv/espressif_esp32/esp32c3/loader.c similarity index 100% rename from soc/riscv/esp32c3/loader.c rename to soc/riscv/espressif_esp32/esp32c3/loader.c diff --git a/soc/riscv/esp32c3/mcuboot.ld b/soc/riscv/espressif_esp32/esp32c3/mcuboot.ld similarity index 100% rename from soc/riscv/esp32c3/mcuboot.ld rename to soc/riscv/espressif_esp32/esp32c3/mcuboot.ld diff --git a/soc/riscv/esp32c3/pinctrl_soc.h b/soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h similarity index 100% rename from soc/riscv/esp32c3/pinctrl_soc.h rename to soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h diff --git a/soc/riscv/esp32c3/power.c b/soc/riscv/espressif_esp32/esp32c3/power.c similarity index 100% rename from soc/riscv/esp32c3/power.c rename to soc/riscv/espressif_esp32/esp32c3/power.c diff --git a/soc/riscv/esp32c3/soc.c b/soc/riscv/espressif_esp32/esp32c3/soc.c similarity index 100% rename from soc/riscv/esp32c3/soc.c rename to soc/riscv/espressif_esp32/esp32c3/soc.c diff --git a/soc/riscv/esp32c3/soc.h b/soc/riscv/espressif_esp32/esp32c3/soc.h similarity index 100% rename from soc/riscv/esp32c3/soc.h rename to soc/riscv/espressif_esp32/esp32c3/soc.h diff --git a/soc/riscv/esp32c3/soc_irq.S b/soc/riscv/espressif_esp32/esp32c3/soc_irq.S similarity index 100% rename from soc/riscv/esp32c3/soc_irq.S rename to soc/riscv/espressif_esp32/esp32c3/soc_irq.S diff --git a/soc/riscv/esp32c3/soc_irq.c b/soc/riscv/espressif_esp32/esp32c3/soc_irq.c similarity index 100% rename from soc/riscv/esp32c3/soc_irq.c rename to soc/riscv/espressif_esp32/esp32c3/soc_irq.c diff --git a/soc/riscv/esp32c3/vectors.S b/soc/riscv/espressif_esp32/esp32c3/vectors.S similarity index 100% rename from soc/riscv/esp32c3/vectors.S rename to soc/riscv/espressif_esp32/esp32c3/vectors.S diff --git a/soc/xtensa/esp32/Kconfig.defconfig b/soc/xtensa/esp32/Kconfig.defconfig deleted file mode 100644 index c6af5cb81c33a5a..000000000000000 --- a/soc/xtensa/esp32/Kconfig.defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# ESP32 board configuration - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ESP32 - -if BOOTLOADER_MCUBOOT - config HAS_FLASH_LOAD_OFFSET - default y - - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - - config ROM_START_OFFSET - default 0x20 - - config HAS_DYNAMIC_DEVICE_HANDLES - default y -endif - -config SOC - default "esp32" - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32" - -if SMP - -config SCHED_IPI_SUPPORTED - default y - -config SCHED_CPU_MASK - default y - -config MP_MAX_NUM_CPUS - default 2 - -endif - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -if GDBSTUB - -# ESP32 GDB expects 420 bytes G-packet. -# So double for hexadecimal digits. -config GDBSTUB_BUF_SZ - default 840 if GDBSTUB - -endif - -endif diff --git a/soc/xtensa/espressif_esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/CMakeLists.txt new file mode 100644 index 000000000000000..31ef76aadeef99d --- /dev/null +++ b/soc/xtensa/espressif_esp32/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/xtensa/espressif_esp32/Kconfig b/soc/xtensa/espressif_esp32/Kconfig new file mode 100644 index 000000000000000..514a934d48fc722 --- /dev/null +++ b/soc/xtensa/espressif_esp32/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ESP32 + bool + +if SOC_FAMILY_ESP32 + +config SOC_FAMILY + string + default "espressif_esp32" + +source "soc/xtensa/espressif_esp32/*/Kconfig.soc" + +endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/Kconfig.defconfig b/soc/xtensa/espressif_esp32/Kconfig.defconfig new file mode 100644 index 000000000000000..a146b8b65560165 --- /dev/null +++ b/soc/xtensa/espressif_esp32/Kconfig.defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/xtensa/espressif_esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/Kconfig.soc new file mode 100644 index 000000000000000..6b28e8008689524 --- /dev/null +++ b/soc/xtensa/espressif_esp32/Kconfig.soc @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +source "soc/xtensa/espressif_esp32/*/Kconfig.series" diff --git a/soc/xtensa/espressif_esp32/common/CMakeLists.txt b/soc/xtensa/espressif_esp32/common/CMakeLists.txt new file mode 100644 index 000000000000000..73509bb53689b96 --- /dev/null +++ b/soc/xtensa/espressif_esp32/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +#zephyr_sources(stm32cube_hal.c) +#zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) +#zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) +#zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) +#zephyr_sources(soc_config.c) diff --git a/soc/xtensa/esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt similarity index 98% rename from soc/xtensa/esp32/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32/CMakeLists.txt index 0728e94e2535728..6c3039116cb476a 100644 --- a/soc/xtensa/esp32/CMakeLists.txt +++ b/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt @@ -40,7 +40,7 @@ if(CONFIG_BOOTLOADER_ESP_IDF) ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} -S ${espidf_components_dir}/bootloader/subproject -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC} + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} -DPYTHON_DEPS_CHECKED=1 -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wd b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wd new file mode 100644 index 000000000000000..ec4baadd4411cce --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wd @@ -0,0 +1,16 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#ESP32-D0WD-V3 +#flash 0 +#psram 0 +#gpio 34 +#used_gpio 6,7,8,9,10,11 +#cert BT_SIG + +if SOC_ESP32D0WD + +config SOC + default "esp32d0wd" + +endif # SOC_ESP32D0WD config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wdr2 b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wdr2 new file mode 100644 index 000000000000000..5670e64912d9bc6 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d0wdr2 @@ -0,0 +1,37 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#ESP32-D0WDR2 +#flash 0 +#psram 2 +#gpio 34 +#used_gpio 6,7,8,9,10,11 + +if SOC_ESP32D0WDR2 + +config SOC + default "esp32d0wdr2" + +#config ESP_SPIRAM +# default y +# +#config SPIRAM_TYPE_ESPPSRAM16 +# default y +# +#config D0WD_PSRAM_CLK_IO +# int "PSRAM CLK IO number" +# range 0 33 +# default 17 +# help +# The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use +# 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. +# +#config D0WD_PSRAM_CS_IO +# int "PSRAM CS IO number" +# range 0 33 +# default 16 +# help +# The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use +# 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endif # SOC_ESP32D0WDR2 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d2wd b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d2wd new file mode 100644 index 000000000000000..28783e9be4cd429 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32d2wd @@ -0,0 +1,32 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#ESP32-D2WD +#flash 0 +#psram 0 +#gpio 34 +#used_gpio 6,7,8,9,10,11 +#cert BT_SIG + +if SOC_ESP32D2WD + +config SOC + default "esp32d2wd" + +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endif # SOC_ESP32D2WD config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32pico b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32pico new file mode 100644 index 000000000000000..a54629162b31a29 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32pico @@ -0,0 +1,13 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#flash 4 +#psram 0 +#gpio 31 +#used_gpio 6,7,8,9,10,11 +if SOC_ESP32PICO + +config SOC + default "esp32pico" + +endif # SOC_ESP32PICO config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32pico02 b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32pico02 new file mode 100644 index 000000000000000..a6876ea5e2e3e03 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32pico02 @@ -0,0 +1,33 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#ESP32-PICO-V3-02 +#flash 8 +#psram 2 +#gpio 29 +#used_gpio 6,7,8,9,10,11 + +if SOC_ESP32PICO02 + +config SOC + default "esp32pico02" + +#config ESP_SPIRAM +# default y +# +#config SPIRAM_TYPE_ESPPSRAM16 +# default y +# +#config PICO_PSRAM_CS_IO +# int "PSRAM CS IO number" +# range 0 33 +# default 10 +# help +# The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. +# +# For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock +# IO. +# For the reference hardware design, please refer to +# https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endif # SOC_ESP32PICO02 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32picod4 b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32picod4 new file mode 100644 index 000000000000000..2548a612d53b9b6 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32picod4 @@ -0,0 +1,33 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#ESP32-PICO-V3-02 +#flash 8 +#psram 2 +#gpio 29 +#used_gpio 6,7,8,9,10,11 + +if SOC_ESP32PICOD4 + +config SOC + default "esp32picod4" + +#config ESP_SPIRAM +# default y +# +#config SPIRAM_TYPE_ESPPSRAM16 +# default y +# +#config PICO_PSRAM_CS_IO +# int "PSRAM CS IO number" +# range 0 33 +# default 10 +# help +# The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. +# +# For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock +# IO. +# For the reference hardware design, please refer to +# https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endif # SOC_ESP32PICOD4 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32u4wdh b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32u4wdh new file mode 100644 index 000000000000000..70e4184eeef95ba --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32u4wdh @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#flash 4 +#psram 0 +#gpio 34 +#used_gpio 6,7,8,11,16,17 + +if SOC_ESP32U4WDH + +config SOC + default "esp32u4wdh" + +endif # SOC_ESP32U4WDH config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32wroom b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32wroom new file mode 100644 index 000000000000000..b0bfba3be9043b6 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32wroom @@ -0,0 +1,18 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#flash 4 +#psram 0 +#gpio 26 +#used_gpio 6,7,8,9,10,11 + +#if SOC_ESP32WROOM + +config SOC + default "esp32wroom" + depends on SOC_ESP32WROOM + +#config SPIRAM_TYPE_NONE +# default y + +#endif # SOC_ESP32WROOM config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32wrover b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32wrover new file mode 100644 index 000000000000000..79ea3130ab7e855 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32wrover @@ -0,0 +1,20 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +#flash 4 +#psram 8 +#gpio 24 +#used_gpio 6,7,8,9,10,11 / 16,17 + +if SOC_ESP32WROVER + +config SOC + default "esp32wrover" + +#config ESP_SPIRAM +# default y +# +#config SPIRAM_TYPE_ESPPSRAM64 +# default y + +endif # SOC_ESP32WROVER config diff --git a/soc/xtensa/esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series similarity index 74% rename from soc/xtensa/esp32/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series index 56949f965992f43..d4f1f6f9715d9eb 100644 --- a/soc/xtensa/esp32/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series @@ -1,23 +1,29 @@ -# Copyright (c) 2017 Intel Corporation +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 -config SOC_ESP32 - bool "ESP32" - select XTENSA - select CLOCK_CONTROL - select DYNAMIC_INTERRUPTS - select ARCH_HAS_GDBSTUB - select ARCH_SUPPORTS_COREDUMP - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - -if SOC_ESP32 - -config SOC_FAMILY_ESP32 - bool - default y +if SOC_SERIES_ESP32 + +source "soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.esp32*" + +config SOC_SERIES + default "esp32" + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32" + +# for compatibility purposes ? +#config SOC +# default "esp32" + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC config IDF_TARGET_ESP32 bool "ESP32 as target board" @@ -35,6 +41,47 @@ config FLASH_BASE_ADDRESS hex default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) +if SMP + +config SCHED_IPI_SUPPORTED + default y + +config SCHED_CPU_MASK + default y + +config MP_MAX_NUM_CPUS + default 2 + +endif # SMP config + +if BOOTLOADER_MCUBOOT + + config HAS_FLASH_LOAD_OFFSET + default y + + config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + + config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + + config ROM_START_OFFSET + default 0x20 + + config HAS_DYNAMIC_DEVICE_HANDLES + default y + +endif # BOOTLOADER_MCUBOOT config + +if GDBSTUB + +# ESP32 GDB expects 420 bytes G-packet. +# So double for hexadecimal digits. +config GDBSTUB_BUF_SZ + default 840 if GDBSTUB + +endif # GDBSTUB config + config ESP32_NETWORK_CORE bool "Uses the ESP32 APP_CPU as Network dedicated core" @@ -82,112 +129,72 @@ config ESP_HEAP_SEARCH_ALL_REGIONS menu "SPI RAM config" depends on ESP_SPIRAM -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE - -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz - 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz - 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz - - Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host - will be occupied by the system. Which SPI host to use can be selected by the config item - SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The - option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. - (ESPTOOLPY_FLASHFREQ_79M is true) - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_80M - depends on ESPTOOLPY_FLASHFREQ_80M - bool "80MHz clock speed" - -endchoice # SPIRAM_SPEED - -menu "PSRAM clock and cs IO for ESP32-DOWD" - -config D0WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 17 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D0WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 16 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-DOWD - -menu "PSRAM clock and cs IO for ESP32-D2WD" - -config D2WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 9 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D2WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-D2WD - -menu "PSRAM clock and cs IO for ESP32-PICO" - -config PICO_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - - For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock - IO. - For the reference hardware design, please refer to - https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf - -endmenu # PSRAM clock and cs IO for ESP32-PICO +#choice SPIRAM_TYPE +# prompt "Type of SPI RAM chip in use" +# default SPIRAM_TYPE_NONE +# #default SPIRAM_TYPE_ESPPSRAM16 +# +#config SPIRAM_TYPE_NONE +# bool "SPIRAM None" +# +#config SPIRAM_TYPE_ESPPSRAM16 +# bool "ESP-PSRAM16 or APS1604" +# +#config SPIRAM_TYPE_ESPPSRAM32 +# bool "ESP-PSRAM32 or IS25WP032" +# +#config SPIRAM_TYPE_ESPPSRAM64 +# bool "ESP-PSRAM64 or LY68L6400" +# +#endchoice # SPIRAM_TYPE +# +#config ESP_SPIRAM_SIZE +# int "Size of SPIRAM part" +# default 2097152 if SPIRAM_TYPE_ESPPSRAM16 +# default 4194304 if SPIRAM_TYPE_ESPPSRAM32 +# default 8388608 if SPIRAM_TYPE_ESPPSRAM64 +# help +# Specify size of SPIRAM part. +# NOTE: If SPIRAM size is greater than 4MB, only +# lower 4MB can be allocated using k_malloc(). +# +#choice SPIRAM_SPEED +# prompt "Set RAM clock speed" +# default SPIRAM_SPEED_40M +# help +# Select the speed for the SPI RAM chip. +# If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: +# +# 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz +# 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz +# 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz +# +# Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host +# will be occupied by the system. Which SPI host to use can be selected by the config item +# SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The +# option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. +# (ESPTOOLPY_FLASHFREQ_79M is true) +# +#config SPIRAM_SPEED_40M +# bool "40MHz clock speed" +# +#config SPIRAM_SPEED_80M +# depends on ESPTOOLPY_FLASHFREQ_80M +# bool "80MHz clock speed" +# +#endchoice # SPIRAM_SPEED + +#menu "PSRAM clock and cs IO for ESP32-DOWD" +# +#endmenu # PSRAM clock and cs IO for ESP32-DOWD +# +#menu "PSRAM clock and cs IO for ESP32-D2WD" +# +#endmenu # PSRAM clock and cs IO for ESP32-D2WD +# +#menu "PSRAM clock and cs IO for ESP32-PICO" +# +#endmenu # PSRAM clock and cs IO for ESP32-PICO config SPIRAM_CUSTOM_SPIWP_SD3_PIN bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" @@ -415,6 +422,6 @@ config ETH_DMA_TX_BUFFER_NUM Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. Larger number of buffers could increase throughput somehow. -endif # ESP32_EMAC +endif # ESP32_EMAC config -endif # SOC_ESP32 +endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.series b/soc/xtensa/espressif_esp32/esp32/Kconfig.series new file mode 100644 index 000000000000000..8e140acd5a603fa --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.series @@ -0,0 +1,17 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32 + bool "ESP32 Series" + select XTENSA + select SOC_FAMILY_ESP32 + select CLOCK_CONTROL + select DYNAMIC_INTERRUPTS + select ARCH_HAS_GDBSTUB + select ARCH_SUPPORTS_COREDUMP + select PINCTRL + select XIP + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + help + Enable support for Espressif ESP32 diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32/Kconfig.soc new file mode 100644 index 000000000000000..6e46a489cee91d7 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32/Kconfig.soc @@ -0,0 +1,38 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice +prompt "ESP32 SOC Selection" +depends on SOC_SERIES_ESP32 + +# SoC with/without embedded flash +config SOC_ESP32D0WD + bool "ESP32D0WD" + +config SOC_ESP32D0WDR2 + bool "ESP32D0WDR2" + +config SOC_ESP32D2WD + bool "ESP32U4WDH" + +config SOC_ESP32U4WDH + bool "ESP32U4WDH" + +# SiP with external flash / psram +config SOC_ESP32WROOM + bool "ESP32WROOM" + +config SOC_ESP32WROVER + bool "ESP32WROVER" + +config SOC_ESP32PICO + bool "ESP32PICO" + +config SOC_ESP32PICO02 + bool "ESP32PICO02" + +config SOC_ESP32PICOD4 + bool "ESP32PICOD4" + +endchoice + diff --git a/soc/xtensa/esp32/default.ld b/soc/xtensa/espressif_esp32/esp32/default.ld similarity index 100% rename from soc/xtensa/esp32/default.ld rename to soc/xtensa/espressif_esp32/esp32/default.ld diff --git a/soc/xtensa/esp32/esp32-mp.c b/soc/xtensa/espressif_esp32/esp32/esp32-mp.c similarity index 100% rename from soc/xtensa/esp32/esp32-mp.c rename to soc/xtensa/espressif_esp32/esp32/esp32-mp.c diff --git a/soc/xtensa/esp32/gdbstub.c b/soc/xtensa/espressif_esp32/esp32/gdbstub.c similarity index 100% rename from soc/xtensa/esp32/gdbstub.c rename to soc/xtensa/espressif_esp32/esp32/gdbstub.c diff --git a/soc/xtensa/esp32/include/_soc_inthandlers.h b/soc/xtensa/espressif_esp32/esp32/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/esp32/include/_soc_inthandlers.h rename to soc/xtensa/espressif_esp32/esp32/include/_soc_inthandlers.h diff --git a/soc/xtensa/esp32/include/gdbstub/soc.h b/soc/xtensa/espressif_esp32/esp32/include/gdbstub/soc.h similarity index 100% rename from soc/xtensa/esp32/include/gdbstub/soc.h rename to soc/xtensa/espressif_esp32/esp32/include/gdbstub/soc.h diff --git a/soc/xtensa/esp32/linker.ld b/soc/xtensa/espressif_esp32/esp32/linker.ld similarity index 100% rename from soc/xtensa/esp32/linker.ld rename to soc/xtensa/espressif_esp32/esp32/linker.ld diff --git a/soc/xtensa/esp32/loader.c b/soc/xtensa/espressif_esp32/esp32/loader.c similarity index 100% rename from soc/xtensa/esp32/loader.c rename to soc/xtensa/espressif_esp32/esp32/loader.c diff --git a/soc/xtensa/esp32/mcuboot.ld b/soc/xtensa/espressif_esp32/esp32/mcuboot.ld similarity index 100% rename from soc/xtensa/esp32/mcuboot.ld rename to soc/xtensa/espressif_esp32/esp32/mcuboot.ld diff --git a/soc/xtensa/esp32/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32/newlib_fix.c diff --git a/soc/xtensa/esp32/pinctrl_soc.h b/soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h similarity index 100% rename from soc/xtensa/esp32/pinctrl_soc.h rename to soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h diff --git a/soc/xtensa/esp32/power.c b/soc/xtensa/espressif_esp32/esp32/power.c similarity index 100% rename from soc/xtensa/esp32/power.c rename to soc/xtensa/espressif_esp32/esp32/power.c diff --git a/soc/xtensa/esp32/soc.c b/soc/xtensa/espressif_esp32/esp32/soc.c similarity index 100% rename from soc/xtensa/esp32/soc.c rename to soc/xtensa/espressif_esp32/esp32/soc.c diff --git a/soc/xtensa/esp32/soc.h b/soc/xtensa/espressif_esp32/esp32/soc.h similarity index 100% rename from soc/xtensa/esp32/soc.h rename to soc/xtensa/espressif_esp32/esp32/soc.h diff --git a/soc/xtensa/esp32_net/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32_net/CMakeLists.txt similarity index 100% rename from soc/xtensa/esp32_net/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32_net/CMakeLists.txt diff --git a/soc/xtensa/esp32_net/Kconfig.defconfig b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.defconfig similarity index 100% rename from soc/xtensa/esp32_net/Kconfig.defconfig rename to soc/xtensa/espressif_esp32/esp32_net/Kconfig.defconfig diff --git a/soc/xtensa/esp32_net/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32_net/Kconfig.soc similarity index 100% rename from soc/xtensa/esp32_net/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32_net/Kconfig.soc diff --git a/soc/xtensa/esp32_net/include/_soc_inthandlers.h b/soc/xtensa/espressif_esp32/esp32_net/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/esp32_net/include/_soc_inthandlers.h rename to soc/xtensa/espressif_esp32/esp32_net/include/_soc_inthandlers.h diff --git a/soc/xtensa/esp32_net/include/gdbstub/soc.h b/soc/xtensa/espressif_esp32/esp32_net/include/gdbstub/soc.h similarity index 100% rename from soc/xtensa/esp32_net/include/gdbstub/soc.h rename to soc/xtensa/espressif_esp32/esp32_net/include/gdbstub/soc.h diff --git a/soc/xtensa/esp32_net/linker.ld b/soc/xtensa/espressif_esp32/esp32_net/linker.ld similarity index 100% rename from soc/xtensa/esp32_net/linker.ld rename to soc/xtensa/espressif_esp32/esp32_net/linker.ld diff --git a/soc/xtensa/esp32_net/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32_net/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32_net/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32_net/newlib_fix.c diff --git a/soc/xtensa/esp32_net/soc.c b/soc/xtensa/espressif_esp32/esp32_net/soc.c similarity index 100% rename from soc/xtensa/esp32_net/soc.c rename to soc/xtensa/espressif_esp32/esp32_net/soc.c diff --git a/soc/xtensa/esp32_net/soc.h b/soc/xtensa/espressif_esp32/esp32_net/soc.h similarity index 100% rename from soc/xtensa/esp32_net/soc.h rename to soc/xtensa/espressif_esp32/esp32_net/soc.h diff --git a/soc/xtensa/esp32s2/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt similarity index 100% rename from soc/xtensa/esp32s2/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt diff --git a/soc/xtensa/esp32s2/Kconfig.defconfig b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig similarity index 100% rename from soc/xtensa/esp32s2/Kconfig.defconfig rename to soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig diff --git a/soc/xtensa/esp32s2/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc similarity index 99% rename from soc/xtensa/esp32s2/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc index f9d77cc1f5d56d5..3b7690868eecb49 100644 --- a/soc/xtensa/esp32s2/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc @@ -13,10 +13,6 @@ config SOC_ESP32S2 if SOC_ESP32S2 -config SOC_FAMILY_ESP32 - bool - default y - config IDF_TARGET_ESP32S2 bool "ESP32S2 as target board" default y diff --git a/soc/xtensa/esp32s2/default.ld b/soc/xtensa/espressif_esp32/esp32s2/default.ld similarity index 100% rename from soc/xtensa/esp32s2/default.ld rename to soc/xtensa/espressif_esp32/esp32s2/default.ld diff --git a/soc/xtensa/esp32s2/include/_soc_inthandlers.h b/soc/xtensa/espressif_esp32/esp32s2/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/esp32s2/include/_soc_inthandlers.h rename to soc/xtensa/espressif_esp32/esp32s2/include/_soc_inthandlers.h diff --git a/soc/xtensa/esp32s2/linker.ld b/soc/xtensa/espressif_esp32/esp32s2/linker.ld similarity index 100% rename from soc/xtensa/esp32s2/linker.ld rename to soc/xtensa/espressif_esp32/esp32s2/linker.ld diff --git a/soc/xtensa/esp32s2/loader.c b/soc/xtensa/espressif_esp32/esp32s2/loader.c similarity index 100% rename from soc/xtensa/esp32s2/loader.c rename to soc/xtensa/espressif_esp32/esp32s2/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/mcuboot-esp32.ld b/soc/xtensa/espressif_esp32/esp32s2/mcuboot-esp32.ld new file mode 100644 index 000000000000000..f2bb4201ebc09a6 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s2/mcuboot-esp32.ld @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2016 Cadence Design Systems, Inc. + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the MCUboot on Xtensa platform. + */ + +#include +#include +#include +#include + +#ifdef CONFIG_XIP +#error "Bootloader cannot use XIP" +#endif /* CONFIG_XIP */ + +/* Disable all romable LMA */ +#undef GROUP_DATA_LINK_IN +#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion + +#define RAMABLE_REGION dram_seg +#define RAMABLE_REGION_1 dram_seg + +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg + +#define IRAM_REGION iram_seg +#define FLASH_CODE_REGION iram_loader_seg + +#define IROM_SEG_ALIGN 16 + +MEMORY +{ + iram_loader_seg (RWX) : org = 0x40078000, len = 0x8000 + iram_seg (RWX) : org = 0x4009C000, len = 0x4000 + dram_seg (RW) : org = 0x3FFEA000, len = 0x16000 + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +PROVIDE ( _ResetVector = 0x40000400 ); + +ENTRY(CONFIG_KERNEL_ENTRY) + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = 0x40000450); +PROVIDE(_memmap_reset_vector = 0x40000400); + +SECTIONS +{ + /* NOTE: .rodata section should be the first section in the linker script and no + * other section should appear before .rodata section. This is the requirement + * to align ROM section to 64K page offset. + * Adding .rodata as first section helps to reduce size of generated binary by + * few kBs. + */ + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + __rodata_region_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + + . = ALIGN(4); + *(.rodata) + *(.rodata.*) +/* + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) +*/ + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + *(.rodata_wlog) + *(.rodata_wlog*) + _thread_local_end = ABSOLUTE(.); + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include +/* #include + #include + #include */ + #include + #include + + #include + + .dram0.data : + { + __data_start = ABSOLUTE(.); + + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ +/* + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) +#*/ + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ +// #pragma push_macro("GROUP_ROM_LINK_IN") +// #undef GROUP_ROM_LINK_IN +// #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include +// #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + #include + . = ALIGN(4); + _end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + /* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + + /* This goes here, not at top of linker script, so addr2line finds it last, + and uses it in preference to the first symbol in IRAM */ + _iram_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *libgcov.a:(.literal .text .literal.* .text.*) + + _iram_text_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + /* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + /* Buffer for system heap should be placed in dram_seg */ + *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + _end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(RAMABLE_REGION)) <= LENGTH(RAMABLE_REGION)), + "DRAM segment data does not fit.") + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN (8); + *(.noinit) + *(.noinit.*) + . = ALIGN (8); + } GROUP_LINK_IN(RAMABLE_REGION_1) + + .flash.text : ALIGN(IROM_SEG_ALIGN) + { + _stext = .; + _text_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + resolved by addr2line in preference to the first symbol in + the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /* TODO: ?? */ + _heap_sentry = 0x3ffe3f20; + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +} + +ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)), + "IRAM0 segment data does not fit.") diff --git a/soc/xtensa/esp32s2/mcuboot.ld b/soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld similarity index 100% rename from soc/xtensa/esp32s2/mcuboot.ld rename to soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld diff --git a/soc/xtensa/esp32s2/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32s2/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c diff --git a/soc/xtensa/esp32s2/pinctrl_soc.h b/soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h similarity index 100% rename from soc/xtensa/esp32s2/pinctrl_soc.h rename to soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h diff --git a/soc/xtensa/esp32s2/power.c b/soc/xtensa/espressif_esp32/esp32s2/power.c similarity index 100% rename from soc/xtensa/esp32s2/power.c rename to soc/xtensa/espressif_esp32/esp32s2/power.c diff --git a/soc/xtensa/esp32s2/soc.c b/soc/xtensa/espressif_esp32/esp32s2/soc.c similarity index 100% rename from soc/xtensa/esp32s2/soc.c rename to soc/xtensa/espressif_esp32/esp32s2/soc.c diff --git a/soc/xtensa/esp32s2/soc.h b/soc/xtensa/espressif_esp32/esp32s2/soc.h similarity index 100% rename from soc/xtensa/esp32s2/soc.h rename to soc/xtensa/espressif_esp32/esp32s2/soc.h diff --git a/soc/xtensa/esp32s2/soc_cache.c b/soc/xtensa/espressif_esp32/esp32s2/soc_cache.c similarity index 100% rename from soc/xtensa/esp32s2/soc_cache.c rename to soc/xtensa/espressif_esp32/esp32s2/soc_cache.c diff --git a/soc/xtensa/esp32s3/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt similarity index 100% rename from soc/xtensa/esp32s3/CMakeLists.txt rename to soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt diff --git a/soc/xtensa/esp32s3/Kconfig.defconfig b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig similarity index 100% rename from soc/xtensa/esp32s3/Kconfig.defconfig rename to soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig diff --git a/soc/xtensa/esp32s3/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc similarity index 98% rename from soc/xtensa/esp32s3/Kconfig.soc rename to soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc index 3860bea328b4c68..04c4037387c8647 100644 --- a/soc/xtensa/esp32s3/Kconfig.soc +++ b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc @@ -1,4 +1,4 @@ -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. # SPDX-License-Identifier: Apache-2.0 config SOC_ESP32S3 @@ -14,10 +14,6 @@ config SOC_ESP32S3 if SOC_ESP32S3 -config SOC_FAMILY_ESP32 - bool - default y - config IDF_TARGET_ESP32S3 bool "ESP32S3 as target board" default y diff --git a/soc/xtensa/espressif_esp32/esp32s3/bootloader.ld b/soc/xtensa/espressif_esp32/esp32s3/bootloader.ld new file mode 100644 index 000000000000000..9217642d6cfb312 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s3/bootloader.ld @@ -0,0 +1,175 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Simplified memory map for the bootloader. + * + * The main purpose is to make sure the bootloader can load into main memory + * without overwriting itself. + */ + +MEMORY +{ + iram_seg (RWX) : org = 0x403B2500, len = 0x7B00 + iram_loader_seg (RWX) : org = 0x403BA000, len = 0x6000 + dram_seg (RW) : org = 0x3FCD8000, len = 0x9A00 +} + +/* Default entry point: */ +ENTRY(main); + +SECTIONS +{ + .iram_loader.text : + { + . = ALIGN (16); + _loader_text_start = ABSOLUTE(.); + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */ + *libhal.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_flash_config_esp32s3.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_init_common.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_flash.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libhal.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libhal.a:bootloader_efuse_esp32s3.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_utility.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_sha.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_console.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_console_loader.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_panic.*(.literal .text .literal.* .text.*) + *libhal.a:bootloader_soc.*(.literal .text .literal.* .text.*) + *libhal.a:esp_image_format.*(.literal .text .literal.* .text.*) + *libhal.a:flash_encrypt.*(.literal .text .literal.* .text.*) + *libhal.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*) + *libhal.a:flash_partitions.*(.literal .text .literal.* .text.*) + *libhal.a:secure_boot.*(.literal .text .literal.* .text.*) + *libhal.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*) + *libhal.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*) + *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*) + *libhal.a:esp_efuse_table.*(.literal .text .literal.* .text.*) + *libhal.a:esp_efuse_fields.*(.literal .text .literal.* .text.*) + *libhal.a:esp_efuse_api.*(.literal .text .literal.* .text.*) + *libhal.a:esp_efuse_utility.*(.literal .text .literal.* .text.*) + *libhal.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) + *libhal.a:app_cpu_start.*(.literal .text .literal.* .text.*) + *esp_mcuboot.*(.literal .text .literal.* .text.*) + *esp_loader.*(.literal .text .literal.* .text.*) + *(.fini.literal) + *(.fini) + *(.gnu.version) + _loader_text_end = ABSOLUTE(.); + } > iram_loader_seg + + .iram.text : + { + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + } > iram_seg + + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _dram_start = ABSOLUTE(.); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >dram_seg + + .dram0.data : + { + _data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + _data_end = ABSOLUTE(.); + } >dram_seg + + .dram0.rodata : + { + _rodata_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + . = (. + 3) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.*(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _dram_end = ABSOLUTE(.); + } >dram_seg + + .iram.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.iram .iram.*) /* catch stray IRAM_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + } > iram_seg + +} diff --git a/soc/xtensa/esp32s3/default.ld b/soc/xtensa/espressif_esp32/esp32s3/default.ld similarity index 100% rename from soc/xtensa/esp32s3/default.ld rename to soc/xtensa/espressif_esp32/esp32s3/default.ld diff --git a/soc/xtensa/esp32s3/include/_soc_inthandlers.h b/soc/xtensa/espressif_esp32/esp32s3/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/esp32s3/include/_soc_inthandlers.h rename to soc/xtensa/espressif_esp32/esp32s3/include/_soc_inthandlers.h diff --git a/soc/xtensa/esp32s3/linker.ld b/soc/xtensa/espressif_esp32/esp32s3/linker.ld similarity index 100% rename from soc/xtensa/esp32s3/linker.ld rename to soc/xtensa/espressif_esp32/esp32s3/linker.ld diff --git a/soc/xtensa/esp32s3/loader.c b/soc/xtensa/espressif_esp32/esp32s3/loader.c similarity index 100% rename from soc/xtensa/esp32s3/loader.c rename to soc/xtensa/espressif_esp32/esp32s3/loader.c diff --git a/soc/xtensa/esp32s3/mcuboot.ld b/soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld similarity index 100% rename from soc/xtensa/esp32s3/mcuboot.ld rename to soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32s3/mcubootesp32.ld b/soc/xtensa/espressif_esp32/esp32s3/mcubootesp32.ld new file mode 100644 index 000000000000000..0f2c4fee4ed6277 --- /dev/null +++ b/soc/xtensa/espressif_esp32/esp32s3/mcubootesp32.ld @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2016 Cadence Design Systems, Inc. + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the MCUboot on Xtensa platform. + */ + +#include +#include +#include +#include + +#ifdef CONFIG_XIP +#error "Bootloader cannot use XIP" +#endif /* CONFIG_XIP */ + +/* Disable all romable LMA */ +#undef GROUP_DATA_LINK_IN +#define GROUP_DATA_LINK_IN(vregion, lregion) > vregion + +#define RAMABLE_REGION dram_seg +#define RAMABLE_REGION_1 dram_seg + +#define RODATA_REGION dram_seg +#define ROMABLE_REGION dram_seg + +#define IRAM_REGION iram_seg +#define FLASH_CODE_REGION iram_loader_seg + +#define IROM_SEG_ALIGN 16 + +MEMORY +{ + /* + iram_loader_seg (RWX) : org = 0x40078000, len = 0x8000 + iram_seg (RWX) : org = 0x4009C000, len = 0x4000 + dram_seg (RW) : org = 0x3FFEA000, len = 0x16000 + */ + iram_seg(RX) : org = 0x403B1000, len = 0x4000 + iram_loader_seg(WX) : org = 0x403BA000, len = 0x8000 + dram_seg(RW) : org = 0x3FCF0000, len = 0x10000 + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +/*PROVIDE ( _ResetVector = 0x40000400 );*/ + +ENTRY(CONFIG_KERNEL_ENTRY) + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = 0x40000450); +PROVIDE(_memmap_reset_vector = 0x40000400); + +SECTIONS +{ + /* NOTE: .rodata section should be the first section in the linker script and no + * other section should appear before .rodata section. This is the requirement + * to align ROM section to 64K page offset. + * Adding .rodata as first section helps to reduce size of generated binary by + * few kBs. + */ + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + __rodata_region_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + + . = ALIGN(4); + *(.rodata) + *(.rodata.*) +/* + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) +*/ + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + *(.rodata_wlog) + *(.rodata_wlog*) + _thread_local_end = ABSOLUTE(.); + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include +/* #include + #include + #include */ + #include + #include + + #include + + .dram0.data : + { + __data_start = ABSOLUTE(.); + + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ +/* + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) +#*/ + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ +// #pragma push_macro("GROUP_ROM_LINK_IN") +// #undef GROUP_ROM_LINK_IN +// #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include +// #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + #include + . = ALIGN(4); + _end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + /* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + + /* This goes here, not at top of linker script, so addr2line finds it last, + and uses it in preference to the first symbol in IRAM */ + _iram_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *libgcov.a:(.literal .text .literal.* .text.*) + + _iram_text_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + /* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + /* Buffer for system heap should be placed in dram_seg */ + *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + _end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(RAMABLE_REGION)) <= LENGTH(RAMABLE_REGION)), + "DRAM segment data does not fit.") + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN (8); + *(.noinit) + *(.noinit.*) + . = ALIGN (8); + } GROUP_LINK_IN(RAMABLE_REGION_1) + + .flash.text : ALIGN(IROM_SEG_ALIGN) + { + _stext = .; + _text_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + resolved by addr2line in preference to the first symbol in + the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /* TODO: ?? */ + _heap_sentry = 0x3ffe3f20; + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +} + +ASSERT(((_iram_end - ORIGIN(IRAM_REGION)) <= LENGTH(IRAM_REGION)), + "IRAM0 segment data does not fit.") diff --git a/soc/xtensa/esp32s3/newlib_fix.c b/soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c similarity index 100% rename from soc/xtensa/esp32s3/newlib_fix.c rename to soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c diff --git a/soc/xtensa/esp32s3/pinctrl_soc.h b/soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h similarity index 100% rename from soc/xtensa/esp32s3/pinctrl_soc.h rename to soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h diff --git a/soc/xtensa/esp32s3/soc.c b/soc/xtensa/espressif_esp32/esp32s3/soc.c similarity index 100% rename from soc/xtensa/esp32s3/soc.c rename to soc/xtensa/espressif_esp32/esp32s3/soc.c diff --git a/soc/xtensa/esp32s3/soc.h b/soc/xtensa/espressif_esp32/esp32s3/soc.h similarity index 100% rename from soc/xtensa/esp32s3/soc.h rename to soc/xtensa/espressif_esp32/esp32s3/soc.h diff --git a/soc/xtensa/esp32s3/soc_cache.c b/soc/xtensa/espressif_esp32/esp32s3/soc_cache.c similarity index 100% rename from soc/xtensa/esp32s3/soc_cache.c rename to soc/xtensa/espressif_esp32/esp32s3/soc_cache.c