From 3c5a22fa67d7973a5f4e69b0a129db866de8ee20 Mon Sep 17 00:00:00 2001 From: Marek Matej Date: Tue, 30 May 2023 23:18:04 +0200 Subject: [PATCH] drivers: Update SOC_ESP32 -> SOC_SERIES_ESP32 Signed-off-by: Marek Matej --- drivers/adc/adc_esp32.c | 14 ++++----- drivers/bluetooth/hci/hci_esp32.c | 2 +- drivers/can/can_esp32_twai.c | 30 +++++++++--------- drivers/clock_control/clock_control_esp32.c | 34 ++++++++++----------- drivers/counter/counter_esp32_rtc.c | 6 ++-- drivers/flash/flash_esp32.c | 8 ++--- drivers/hwinfo/hwinfo_esp32.c | 2 +- drivers/i2c/i2c_esp32.c | 2 +- drivers/interrupt_controller/Kconfig.esp32 | 2 +- drivers/sensor/esp32_temp/esp32_temp.c | 2 +- drivers/sensor/pcnt_esp32/pcnt_esp32.c | 8 ++--- drivers/serial/uart_esp32.c | 12 ++++---- drivers/spi/spi_esp32_spim.c | 12 ++++---- 13 files changed, 67 insertions(+), 67 deletions(-) diff --git a/drivers/adc/adc_esp32.c b/drivers/adc/adc_esp32.c index 01bd54c32b5aa78..cbf64ea4c458ada 100644 --- a/drivers/adc/adc_esp32.c +++ b/drivers/adc/adc_esp32.c @@ -20,7 +20,7 @@ #include LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL); -#if CONFIG_SOC_ESP32 +#if CONFIG_SOC_SERIES_ESP32 #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_VREF #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH @@ -31,12 +31,12 @@ LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL); */ #define ADC_CLIP_MVOLT_11DB 2550 -#elif CONFIG_SOC_ESP32S2 +#elif CONFIG_SOC_SERIES_ESP32S2 #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_MAX_BITWIDTH -#elif CONFIG_SOC_ESP32C3 +#elif CONFIG_SOC_SERIES_ESP32C3 #define ADC_CALI_SCHEME ESP_ADC_CAL_VAL_EFUSE_TP #define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MAX_BITWIDTH #define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH @@ -165,14 +165,14 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s data->resolution[channel_id] = seq->resolution; -#if CONFIG_SOC_ESP32C3 +#if CONFIG_SOC_SERIES_ESP32C3 /* NOTE: nothing to set on ESP32C3 SoC */ if (conf->unit == ADC_UNIT_1) { adc1_config_width(ADC_WIDTH_BIT_DEFAULT); } #else adc_set_data_width(conf->unit, WIDTH_MASK(data->resolution[channel_id])); -#endif /* CONFIG_SOC_ESP32C3 */ +#endif /* CONFIG_SOC_SERIES_ESP32C3 */ /* Read raw value */ if (conf->unit == ADC_UNIT_1) { @@ -191,13 +191,13 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s /* Get corrected voltage output */ cal = cal_mv = esp_adc_cal_raw_to_voltage(reading, &data->chars[channel_id]); -#if CONFIG_SOC_ESP32 +#if CONFIG_SOC_SERIES_ESP32 if (data->attenuation[channel_id] == ADC_ATTEN_DB_11) { if (cal > ADC_CLIP_MVOLT_11DB) { cal = ADC_CLIP_MVOLT_11DB; } } -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ /* Fit according to selected attenuation */ atten_to_gain(data->attenuation[channel_id], &cal); diff --git a/drivers/bluetooth/hci/hci_esp32.c b/drivers/bluetooth/hci/hci_esp32.c index bdcdb7db99aa012..8dae220dd944d94 100644 --- a/drivers/bluetooth/hci/hci_esp32.c +++ b/drivers/bluetooth/hci/hci_esp32.c @@ -280,7 +280,7 @@ static int bt_esp32_ble_init(void) int ret; esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); -#if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_BT_BREDR) && defined(CONFIG_SOC_SERIES_ESP32) esp_bt_mode_t mode = ESP_BT_MODE_BTDM; #else esp_bt_mode_t mode = ESP_BT_MODE_BLE; diff --git a/drivers/can/can_esp32_twai.c b/drivers/can/can_esp32_twai.c index cd0d6bad6ec3c6c..0d745dccdbefe24 100644 --- a/drivers/can/can_esp32_twai.c +++ b/drivers/can/can_esp32_twai.c @@ -26,7 +26,7 @@ LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL); * The names with TWAI_ prefixes from Espressif reference manuals are used for these incompatible * registers. */ -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* TWAI_BUS_TIMING_0_REG is incompatible with CAN_SJA1000_BTR0 */ #define TWAI_BUS_TIMING_0_REG (6U) @@ -63,7 +63,7 @@ LOG_MODULE_REGISTER(can_esp32_twai, CONFIG_CAN_LOG_LEVEL); #define TWAI_CD_MASK GENMASK(2, 0) #define TWAI_CLOCK_OFF BIT(3) -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ struct can_esp32_twai_config { mm_reg_t base; @@ -71,10 +71,10 @@ struct can_esp32_twai_config { const struct device *clock_dev; const clock_control_subsys_t clock_subsys; int irq_source; -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* 32-bit variant of output clock divider register required for non-ESP32 MCUs */ uint32_t cdr32; -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ }; static uint8_t can_esp32_twai_read_reg(const struct device *dev, uint8_t reg) @@ -95,7 +95,7 @@ static void can_esp32_twai_write_reg(const struct device *dev, uint8_t reg, uint sys_write32(val & 0xFF, addr); } -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* * Required for newer ESP32-series MCUs which violate the original SJA1000 8-bit register size. @@ -157,7 +157,7 @@ static int can_esp32_twai_set_timing(const struct device *dev, const struct can_ return 0; } -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ static int can_esp32_twai_get_core_clock(const struct device *dev, uint32_t *rate) { @@ -205,7 +205,7 @@ static int can_esp32_twai_init(const struct device *dev) return err; } -#ifndef CONFIG_SOC_ESP32 +#ifndef CONFIG_SOC_SERIES_ESP32 /* * TWAI_CLOCK_DIVIDER_REG is incompatible with CAN_SJA1000_CDR for non-ESP32 MCUs * - TWAI_CD has length of 8 bits instead of 3 bits @@ -215,7 +215,7 @@ static int can_esp32_twai_init(const struct device *dev) * Overwrite with 32-bit register variant configured via devicetree. */ can_esp32_twai_write_reg32(dev, TWAI_CLOCK_DIVIDER_REG, twai_config->cdr32); -#endif /* !CONFIG_SOC_ESP32 */ +#endif /* !CONFIG_SOC_SERIES_ESP32 */ esp_intr_alloc(twai_config->irq_source, 0, can_esp32_twai_isr, (void *)dev, NULL); @@ -227,11 +227,11 @@ const struct can_driver_api can_esp32_twai_driver_api = { .start = can_sja1000_start, .stop = can_sja1000_stop, .set_mode = can_sja1000_set_mode, -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 .set_timing = can_sja1000_set_timing, #else .set_timing = can_esp32_twai_set_timing, -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ .send = can_sja1000_send, .add_rx_filter = can_sja1000_add_rx_filter, .remove_rx_filter = can_sja1000_remove_rx_filter, @@ -244,7 +244,7 @@ const struct can_driver_api can_esp32_twai_driver_api = { .recover = can_sja1000_recover, #endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */ .timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER, -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 .timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER, #else /* larger prescaler allowed for newer ESP32-series MCUs */ @@ -255,16 +255,16 @@ const struct can_driver_api can_esp32_twai_driver_api = { .phase_seg2 = 0x8, .prescaler = 0x2000, } -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ }; -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #define TWAI_CLKOUT_DIVIDER_MAX (14) #define TWAI_CDR32_INIT(inst) #else #define TWAI_CLKOUT_DIVIDER_MAX (490) #define TWAI_CDR32_INIT(inst) .cdr32 = CAN_ESP32_TWAI_DT_CDR_INST_GET(inst) -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ #define CAN_ESP32_TWAI_ASSERT_CLKOUT_DIVIDER(inst) \ BUILD_ASSERT(COND_CODE_0(DT_INST_NODE_HAS_PROP(inst, clkout_divider), (1), \ @@ -295,7 +295,7 @@ const struct can_driver_api can_esp32_twai_driver_api = { CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_esp32_twai_config_##inst, \ can_esp32_twai_read_reg, can_esp32_twai_write_reg, \ CAN_SJA1000_OCR_OCMODE_BIPHASE, \ - COND_CODE_0(IS_ENABLED(CONFIG_SOC_ESP32), (0), \ + COND_CODE_0(IS_ENABLED(CONFIG_SOC_SERIES_ESP32), (0), \ (CAN_ESP32_TWAI_DT_CDR_INST_GET(inst)))); \ \ static struct can_sja1000_data can_sja1000_data_##inst = \ diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c index d7bda543bb2b466..4e2136b2683e14c 100644 --- a/drivers/clock_control/clock_control_esp32.c +++ b/drivers/clock_control/clock_control_esp32.c @@ -9,32 +9,32 @@ #define CPU_RESET_REASON RTC_SW_CPU_RESET -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6 #undef CPU_RESET_REASON #define CPU_RESET_REASON SW_CPU_RESET #include #include "esp32/rom/rtc.h" #include "soc/dport_reg.h" -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #include #include "esp32s2/rom/rtc.h" #include "soc/dport_reg.h" -#elif defined(CONFIG_SOC_ESP32S3) +#elif defined(CONFIG_SOC_SERIES_ESP32S3) #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7 #include #include "esp32s3/rom/rtc.h" #include "soc/dport_reg.h" #include "esp32s3/clk.h" -#elif CONFIG_IDF_TARGET_ESP32C3 +#elif CONFIG_SOC_SERIES_ESP32C3 #define DT_CPU_COMPAT espressif_riscv #include #include "esp32c3/rom/rtc.h" #include #include #include -#endif +#endif /* CONFIG_SOC_SERIES_ESP32xx */ #include "esp_rom_sys.h" #include @@ -55,14 +55,14 @@ struct esp32_clock_config { }; static uint8_t const xtal_freq[] = { -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) || defined(CONFIG_SOC_ESP32S3) +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET) || defined(CONFIG_SOC_SERIES_ESP32S3) [ESP32_CLK_XTAL_24M] = 24, [ESP32_CLK_XTAL_26M] = 26, [ESP32_CLK_XTAL_40M] = 40, [ESP32_CLK_XTAL_AUTO] = 0 -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) [ESP32_CLK_XTAL_40M] = 40, -#elif defined(CONFIG_SOC_ESP32C3) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) [ESP32_CLK_XTAL_32M] = 32, [ESP32_CLK_XTAL_40M] = 40, #endif @@ -124,7 +124,7 @@ static int clock_control_esp32_get_rate(const struct device *dev, return 0; } -#if defined(CONFIG_SOC_ESP32) || defined(CONFIG_SOC_ESP32_NET) +#if defined(CONFIG_SOC_SERIES_ESP32) || defined(CONFIG_SOC_SERIES_ESP32_NET) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk; @@ -217,9 +217,9 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32 */ -#if defined(CONFIG_SOC_ESP32S2) +#if defined(CONFIG_SOC_SERIES_ESP32S2) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk; @@ -321,9 +321,9 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32S2 */ -#if defined(CONFIG_SOC_ESP32S3) +#if defined(CONFIG_SOC_SERIES_ESP32S3) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; @@ -421,9 +421,9 @@ static void esp32_clock_perip_init(void) esp_rom_uart_tx_wait_idle(0); esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32S3 */ -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) static void esp32_clock_perip_init(void) { uint32_t common_perip_clk; @@ -510,7 +510,7 @@ static void esp32_clock_perip_init(void) /* Enable RNG clock. */ periph_module_enable(PERIPH_RNG_MODULE); } -#endif +#endif /* CONFIG_SOC_SERIES_ESP32C3 */ static int clock_control_esp32_init(const struct device *dev) { @@ -596,7 +596,7 @@ DEVICE_DT_DEFINE(DT_NODELABEL(rtc), CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_esp32_api); -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) == DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency), "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq"); diff --git a/drivers/counter/counter_esp32_rtc.c b/drivers/counter/counter_esp32_rtc.c index 7b157414b57db3d..0b7e8bbbb27cc12 100644 --- a/drivers/counter/counter_esp32_rtc.c +++ b/drivers/counter/counter_esp32_rtc.c @@ -18,7 +18,7 @@ #include #include -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) #include #else #include @@ -27,7 +27,7 @@ #include LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL); -#if defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32C3) #define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t #else #define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t @@ -88,7 +88,7 @@ static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks) ARG_UNUSED(dev); SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE); -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) { /* might take 1 RTC slowclk period, don't flood RTC bus */ k_sleep(K_USEC(1)); diff --git a/drivers/flash/flash_esp32.c b/drivers/flash/flash_esp32.c index e2919258294ca69..6366401a43b199a 100644 --- a/drivers/flash/flash_esp32.c +++ b/drivers/flash/flash_esp32.c @@ -30,20 +30,20 @@ #include #include -#if defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32) #include "soc/dport_reg.h" #include "esp32/rom/cache.h" #include "esp32/rom/spi_flash.h" #include "esp32/spiram.h" -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) #include "soc/spi_mem_reg.h" #include "esp32s2/rom/cache.h" #include "esp32s2/rom/spi_flash.h" -#elif defined(CONFIG_SOC_ESP32S3) +#elif defined(CONFIG_SOC_SERIES_ESP32S3) #include "soc/spi_mem_reg.h" #include "esp32s3/rom/cache.h" #include "esp32s3/rom/spi_flash.h" -#elif defined(CONFIG_SOC_ESP32C3) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) #include "soc/spi_periph.h" #include "soc/spi_mem_reg.h" #include "soc/dport_access.h" diff --git a/drivers/hwinfo/hwinfo_esp32.c b/drivers/hwinfo/hwinfo_esp32.c index fd466c32704a501..df4d67321120d8e 100644 --- a/drivers/hwinfo/hwinfo_esp32.c +++ b/drivers/hwinfo/hwinfo_esp32.c @@ -15,7 +15,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { -#if !defined(CONFIG_SOC_ESP32) && !defined(CONFIG_SOC_ESP32_NET) +#if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32_NET) uint32_t rdata1 = sys_read32(EFUSE_RD_MAC_SPI_SYS_0_REG); uint32_t rdata2 = sys_read32(EFUSE_RD_MAC_SPI_SYS_1_REG); #else diff --git a/drivers/i2c/i2c_esp32.c b/drivers/i2c/i2c_esp32.c index 267c49793e4a447..0730fd1a6d6323b 100644 --- a/drivers/i2c/i2c_esp32.c +++ b/drivers/i2c/i2c_esp32.c @@ -255,7 +255,7 @@ static void IRAM_ATTR i2c_esp32_configure_timeout(const struct device *dev) * at least for ESP32-C3 (tested with communication to bq76952 chip). So we set the * timeout to maximum supported value instead. */ -#if defined(CONFIG_SOC_ESP32C3) || defined(CONFIG_SOC_ESP32) +#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32) i2c_hal_set_tout(&data->hal, I2C_LL_MAX_TIMEOUT); #else i2c_hal_set_tout_en(&data->hal, 0); diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32 index 6080dcbc318e986..90227cf79a4a796 100644 --- a/drivers/interrupt_controller/Kconfig.esp32 +++ b/drivers/interrupt_controller/Kconfig.esp32 @@ -5,7 +5,7 @@ config INTC_ESP32 bool "Interrupt allocator for Xtensa-based Espressif SoCs" - default y if SOC_ESP32 || SOC_ESP32S2 || SOC_ESP32_NET || SOC_ESP32S3 + default y if SOC_FAMILY_ESP32 help Enable custom interrupt allocator for Espressif SoCs based on Xtensa architecture. diff --git a/drivers/sensor/esp32_temp/esp32_temp.c b/drivers/sensor/esp32_temp/esp32_temp.c index 1ceb13bde088329..5deaecc3430fabe 100644 --- a/drivers/sensor/esp32_temp/esp32_temp.c +++ b/drivers/sensor/esp32_temp/esp32_temp.c @@ -16,7 +16,7 @@ #include LOG_MODULE_REGISTER(esp32_temp, CONFIG_SENSOR_LOG_LEVEL); -#if CONFIG_SOC_ESP32 +#if CONFIG_SOC_SERIES_ESP32 #error "Temperature sensor not supported on ESP32" #endif /* CONFIG_IDF_TARGET_ESP32 */ diff --git a/drivers/sensor/pcnt_esp32/pcnt_esp32.c b/drivers/sensor/pcnt_esp32/pcnt_esp32.c index 21da92897356cc3..487e1352156a83c 100644 --- a/drivers/sensor/pcnt_esp32/pcnt_esp32.c +++ b/drivers/sensor/pcnt_esp32/pcnt_esp32.c @@ -29,12 +29,12 @@ LOG_MODULE_REGISTER(pcnt_esp32, CONFIG_SENSOR_LOG_LEVEL); #define PCNT_INTR_UNIT_1 BIT(1) #define PCNT_INTR_UNIT_2 BIT(2) #define PCNT_INTR_UNIT_3 BIT(3) -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #define PCNT_INTR_UNIT_4 BIT(4) #define PCNT_INTR_UNIT_5 BIT(5) #define PCNT_INTR_UNIT_6 BIT(6) #define PCNT_INTR_UNIT_7 BIT(7) -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ #ifdef CONFIG_PCNT_ESP32_TRIGGER #define PCNT_INTR_THRES_1 BIT(2) @@ -293,7 +293,7 @@ static void IRAM_ATTR pcnt_esp32_isr(const struct device *dev) pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 2); } else if (pcnt_intr_status & PCNT_INTR_UNIT_3) { pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 3); -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 } else if (pcnt_intr_status & PCNT_INTR_UNIT_4) { pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 4); } else if (pcnt_intr_status & PCNT_INTR_UNIT_5) { @@ -302,7 +302,7 @@ static void IRAM_ATTR pcnt_esp32_isr(const struct device *dev) pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 6); } else if (pcnt_intr_status & PCNT_INTR_UNIT_7) { pcnt_unit_status = pcnt_ll_get_unit_status(data->hal.dev, 7); -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ } else { return; } diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c index 4b9fba97c8623e0..964224473b20451 100644 --- a/drivers/serial/uart_esp32.c +++ b/drivers/serial/uart_esp32.c @@ -8,18 +8,18 @@ /* Include esp-idf headers first to avoid redefining BIT() macro */ /* TODO: include w/o prefix */ -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #include #include #include -#elif defined(CONFIG_SOC_ESP32S2) +#elif defined(CONFIG_SOC_SERIES_ESP32S2) #include #include #include -#elif defined(CONFIG_SOC_ESP32S3) +#elif defined(CONFIG_SOC_SERIES_ESP32S3) #include #include -#elif defined(CONFIG_SOC_ESP32C3) +#elif defined(CONFIG_SOC_SERIES_ESP32C3) #include #include #ifdef CONFIG_UART_ASYNC_API @@ -41,7 +41,7 @@ #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -53,7 +53,7 @@ #include LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL); -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t diff --git a/drivers/spi/spi_esp32_spim.c b/drivers/spi/spi_esp32_spim.c index 74b5d7c82b9b40e..3a1a5dc244a75b2 100644 --- a/drivers/spi/spi_esp32_spim.c +++ b/drivers/spi/spi_esp32_spim.c @@ -16,7 +16,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL); #include #include #include -#ifndef CONFIG_SOC_ESP32C3 +#ifndef CONFIG_SOC_SERIES_ESP32C3 #include #else #include @@ -29,7 +29,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL); #include "spi_context.h" #include "spi_esp32_spim.h" -#ifdef CONFIG_SOC_ESP32C3 +#ifdef CONFIG_SOC_SERIES_ESP32C3 #define ISR_HANDLER isr_handler_t #else #define ISR_HANDLER intr_handler_t @@ -180,11 +180,11 @@ static int spi_esp32_init_dma(const struct device *dev) #else channel_offset = 1; #endif /* SOC_GDMA_SUPPORTED */ -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 /*Connect SPI and DMA*/ DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, cfg->dma_host + 1, ((cfg->dma_host + 1) * 2)); -#endif /* CONFIG_SOC_ESP32 */ +#endif /* CONFIG_SOC_SERIES_ESP32 */ data->hal_config.dma_in = (spi_dma_dev_t *)cfg->spi; data->hal_config.dma_out = (spi_dma_dev_t *)cfg->spi; @@ -351,7 +351,7 @@ static int IRAM_ATTR spi_esp32_configure(const struct device *dev, * Workaround for ESP32S3 and ESP32C3 SoC. This dummy transaction is needed to sync CLK and * software controlled CS when SPI is in mode 3 */ -#if defined(CONFIG_SOC_ESP32S3) || defined(CONFIG_SOC_ESP32C3) +#if defined(CONFIG_SOC_SERIES_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3) if (ctx->num_cs_gpios && (hal_dev->mode & (SPI_MODE_CPOL | SPI_MODE_CPHA))) { spi_esp32_transfer(dev); } @@ -463,7 +463,7 @@ static const struct spi_driver_api spi_api = { .release = spi_esp32_release }; -#ifdef CONFIG_SOC_ESP32 +#ifdef CONFIG_SOC_SERIES_ESP32 #define GET_AS_CS(idx) .as_cs = DT_INST_PROP(idx, clk_as_cs), #else #define GET_AS_CS(idx)