From 70211f4d10ce0a15b50477bebb2f4500de63a3ee Mon Sep 17 00:00:00 2001 From: Eric Ackermann Date: Fri, 30 Aug 2024 10:47:29 +0200 Subject: [PATCH] boards: openhwgroup: add CV64A6 on GenesysII board Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Signed-off-by: Eric Ackermann --- .../cv64a6_genesysII/CMakeLists.txt | 1 + .../cv64a6_genesysII/Kconfig.cv64a6_genesysII | 5 ++ .../openhwgroup/cv64a6_genesysII/board.cmake | 8 ++ boards/openhwgroup/cv64a6_genesysII/board.yml | 7 ++ .../cv64a6_genesysII/cv64a6_genesysII.dts | 74 +++++++++++++++++++ .../cv64a6_genesysII_defconfig | 46 ++++++++++++ .../cv64a6_genesysII/support/ariane.cfg | 49 ++++++++++++ 7 files changed, 190 insertions(+) create mode 100644 boards/openhwgroup/cv64a6_genesysII/CMakeLists.txt create mode 100644 boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII create mode 100644 boards/openhwgroup/cv64a6_genesysII/board.cmake create mode 100644 boards/openhwgroup/cv64a6_genesysII/board.yml create mode 100644 boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts create mode 100644 boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig create mode 100644 boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg diff --git a/boards/openhwgroup/cv64a6_genesysII/CMakeLists.txt b/boards/openhwgroup/cv64a6_genesysII/CMakeLists.txt new file mode 100644 index 000000000000000..9881313609aae2c --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/CMakeLists.txt @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII b/boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII new file mode 100644 index 000000000000000..af8bfea7f102725 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/Kconfig.cv64a6_genesysII @@ -0,0 +1,5 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +config BOARD_CV64A6_GENESYSII + select SOC_CV64A6 + select SOC_SERIES_CV64A6_PROVIDE_FPGA_POWEROFF \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/board.cmake b/boards/openhwgroup/cv64a6_genesysII/board.cmake new file mode 100644 index 000000000000000..fffa2bed09562b3 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/board.cmake @@ -0,0 +1,8 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg") +board_runner_args(openocd "--use-elf") +board_runner_args(openocd "--verify") +board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/board.yml b/boards/openhwgroup/cv64a6_genesysII/board.yml new file mode 100644 index 000000000000000..1c48d2b4f7de3e4 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/board.yml @@ -0,0 +1,7 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +board: + name: cv64a6_genesysII + vendor: openhwgroup + socs: + - name: cv64a6 \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts new file mode 100644 index 000000000000000..b9463391bec3185 --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Openhardwaregroup CV64A6 on Genesys II"; + compatible = "ariane,cv64a6_genesysII"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &memory0; + }; + + // these devices are missing in the Northcape board + eth: lowrisc-eth@30000000 { + compatible = "lowrisc-eth"; + device_type = "network"; + interrupt-parent = <&PLIC0>; + interrupts = <3 0>; + local-mac-address = [00 18 3e 02 e3 7f]; + reg = <0x0 0x30000000 0x0 0x8000>; + }; + xlnx_gpio: gpio@40000000 { + #gpio-cells = <2>; + compatible = "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x40000000 0x0 0x10000 >; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,dout-default = <0x0>; + xlnx,dout-default-2 = <0x0>; + xlnx,gpio-width = <0x8>; + xlnx,gpio2-width = <0x8>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xffffffff>; + xlnx,tri-default-2 = <0xffffffff>; + }; +}; + +&uart0 { + status = "okay"; + // different interrupt than the CISPA version of the SoC + interrupts = <1>; +}; + +&spi0 { + status = "okay"; + // different interrupt than the CISPA version of the SoC + interrupts = <2 2>; +}; + +&clint{ + status = "okay"; +}; + +&dma0 { + status = "disabled"; +}; + + +&mdio0{ + status = "disabled"; +}; + +ð0 { + status = "disabled"; +}; diff --git a/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig new file mode 100644 index 000000000000000..3d036e5baa74e9f --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/cv64a6_genesysII_defconfig @@ -0,0 +1,46 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 +CONFIG_BASE64=y +CONFIG_INCLUDE_RESET_VECTOR=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_NS16550=y +CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y +CONFIG_CONSOLE_HANDLER=y +CONFIG_XIP=n +CONFIG_INIT_STACKS=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=25000000 +CONFIG_FPU=y +CONFIG_POWEROFF=y + +# RNG +CONFIG_TIMER_RANDOM_GENERATOR=y +CONFIG_TEST_RANDOM_GENERATOR=y + +# IRQs +CONFIG_MULTI_LEVEL_INTERRUPTS=y +CONFIG_2ND_LEVEL_INTERRUPTS=y +# 1 PLIC +CONFIG_NUM_2ND_LEVEL_AGGREGATORS=1 +CONFIG_1ST_LEVEL_INTERRUPT_BITS=7 +CONFIG_2ND_LEVEL_INTERRUPT_BITS=23 +CONFIG_PLIC=y +CONFIG_3RD_LEVEL_INTERRUPTS=n +CONFIG_3RD_LEVEL_INTERRUPT_BITS=0 + +# debug +CONFIG_DEBUG=y +CONFIG_DEBUG_OPTIMIZATIONS=y +CONFIG_STACK_SENTINEL=y +CONFIG_LOG=y +CONFIG_LOG_MODE_IMMEDIATE=y +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_THREAD_NAME=y + +CONFIG_ISR_STACK_SIZE=524288 +CONFIG_MAIN_STACK_SIZE=524288 +CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=524288 +CONFIG_IDLE_STACK_SIZE=524288 + +CONFIG_DMA_LOG_LEVEL_INF=y \ No newline at end of file diff --git a/boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg b/boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg new file mode 100644 index 000000000000000..9bece8fca9c555e --- /dev/null +++ b/boards/openhwgroup/cv64a6_genesysII/support/ariane.cfg @@ -0,0 +1,49 @@ +# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH +# SPDX-License-Identifier: Apache-2.0 + +# Based on the ariane.cfg from the cva6 project: +# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg +adapter_khz 1000 + +interface ftdi +ftdi_vid_pid 0x0403 0x6010 + +# Channel 1 is taken by Xilinx JTAG +ftdi_channel 0 + +# links: +# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html +# +# Bit MPSSE FT2232 JTAG Type Description +# Bit0 TCK ADBUS0 TCK Out Clock Signal Output +# Bit1 TDI ADBUS1 TDI Out Serial Data Out +# Bit2 TDO ADBUS2 TDO In Serial Data In +# Bit3 TMS ADBUS3 TMS Out Select Signal Out +# Bit4 GPIOL0 ADBUS4 nTRST In/Out General Purpose I/O +# this corresponds to the following in/out layout, with TMS initially set to 1 +ftdi_layout_init 0x0018 0x001b +# we only have to specify nTRST, the others are assigned correctly by default +ftdi_layout_signal nTRST -ndata 0x0010 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0 + +gdb_report_data_abort enable +gdb_report_register_access_error enable + +riscv set_reset_timeout_sec 120 +riscv set_command_timeout_sec 120 + +# prefer to use sba for system bus access +riscv set_prefer_sba off + +# Try enabling address translation (only works for newer versions) +if { [catch {riscv set_enable_virtual on} ] } { + echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." } + +init +halt +echo "Ready for Remote Connections"