From 7ffb95347a761384ce927e5f407c726a94792075 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Wed, 5 Jul 2023 16:10:31 +0200 Subject: [PATCH] dts: Move to 'zephyr,memory-attr' Move to 'zephyr,memory-attr' and use the newly introduced helpers. Signed-off-by: Carlo Caione --- .../arduino_giga_r1/arduino_giga_r1_m7.dts | 2 +- .../arm/stm32f746g_disco/stm32f746g_disco.dts | 2 +- boards/arm/stm32f7508_dk/stm32f7508_dk.dts | 2 +- .../arm/stm32f769i_disco/stm32f769i_disco.dts | 2 +- .../stm32h747i_disco/stm32h747i_disco_m7.dts | 2 +- boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts | 2 +- .../fvp_baser_aemv8r/fvp_baser_aemv8r.dts | 2 +- doc/hardware/arch/arm_cortex_m.rst | 8 +- drivers/adc/adc_stm32.c | 6 +- drivers/dma/dma_stm32_bdma.c | 6 +- dts/arm/nxp/nxp_lpc55S1x_common.dtsi | 2 +- dts/arm/nxp/nxp_lpc55S2x_common.dtsi | 2 +- dts/arm/nxp/nxp_lpc55S6x_common.dtsi | 2 +- dts/arm/nxp/nxp_rt5xx_common.dtsi | 2 +- dts/arm/nxp/nxp_rt6xx_common.dtsi | 2 +- dts/arm/st/f7/stm32f7.dtsi | 2 +- dts/arm/st/h7/stm32h7.dtsi | 2 +- dts/bindings/base/zephyr,memory-region.yaml | 16 +-- include/zephyr/linker/devicetree_regions.h | 114 ------------------ .../openamp/boards/mimxrt1160_evk_cm7.overlay | 2 +- .../openamp/boards/mimxrt1170_evk_cm7.overlay | 2 +- .../boards/mimxrt1170_evkb_cm7.overlay | 2 +- .../remote/boards/mimxrt1160_evk_cm4.overlay | 2 +- .../remote/boards/mimxrt1170_evk_cm4.overlay | 2 +- .../remote/boards/mimxrt1170_evkb_cm4.overlay | 2 +- soc/arm/common/cortex_m/arm_mpu_regions.c | 4 +- soc/arm/st_stm32/stm32h7/mpu_regions.c | 3 +- soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c | 4 +- .../arm_mpu_regions/boards/mps2_an385.overlay | 6 +- .../adc/adc_dma/boards/nucleo_h743zi.overlay | 2 +- .../boards/nucleo_h743zi.overlay | 2 +- .../boards/nucleo_h743zi.overlay | 2 +- .../boards/mps2_an521.overlay | 6 +- .../boards/qemu_cortex_a53.overlay | 6 +- .../mem_heap/shared_multi_heap/src/main.c | 4 +- 35 files changed, 50 insertions(+), 179 deletions(-) diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts index ed693b6e337d95d..f456227f96f513e 100644 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts +++ b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts @@ -29,7 +29,7 @@ device_type = "memory"; reg = <0xc0000000 DT_SIZE_M(8)>; zephyr,memory-region = "SDRAM1"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; aliases { diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts index 93054659df2f0b2..6981ed726e9e106 100644 --- a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts +++ b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts @@ -45,7 +45,7 @@ device_type = "memory"; reg = <0xc0000000 DT_SIZE_M(16)>; zephyr,memory-region = "SDRAM1"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; aliases { diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk.dts b/boards/arm/stm32f7508_dk/stm32f7508_dk.dts index c91bc664d7e0253..4cc8b7754a72ebe 100644 --- a/boards/arm/stm32f7508_dk/stm32f7508_dk.dts +++ b/boards/arm/stm32f7508_dk/stm32f7508_dk.dts @@ -46,7 +46,7 @@ device_type = "memory"; reg = <0xc0000000 DT_SIZE_M(16)>; zephyr,memory-region = "SDRAM1"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; aliases { diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco.dts b/boards/arm/stm32f769i_disco/stm32f769i_disco.dts index 26dfa4c6c31bc35..f857d8e48f500f5 100644 --- a/boards/arm/stm32f769i_disco/stm32f769i_disco.dts +++ b/boards/arm/stm32f769i_disco/stm32f769i_disco.dts @@ -28,7 +28,7 @@ device_type = "memory"; reg = <0xc0000000 DT_SIZE_M(16)>; zephyr,memory-region = "SDRAM1"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; leds { diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts index 6104a7c17659268..918c61b9978466b 100644 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts +++ b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts @@ -27,7 +27,7 @@ device_type = "memory"; reg = <0xd0000000 DT_SIZE_M(32)>; zephyr,memory-region = "SDRAM2"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; leds { diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts index c5102e8a0806c91..c6c61180281bf78 100644 --- a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts +++ b/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts @@ -48,7 +48,7 @@ device_type = "memory"; reg = <0xd0000000 DT_SIZE_M(16)>; zephyr,memory-region = "SDRAM2"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; transceiver0: can-phy0 { diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts index 86b95839506b650..80d45f513510582 100644 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts +++ b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts @@ -41,7 +41,7 @@ compatible = "zephyr,memory-region", "mmio-dram"; reg = <0x80000000 DT_SIZE_M(2048)>; zephyr,memory-region = "DEVICE_REGION"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; }; diff --git a/doc/hardware/arch/arm_cortex_m.rst b/doc/hardware/arch/arm_cortex_m.rst index 15369212cf26d01..05c37e272a2d051 100644 --- a/doc/hardware/arch/arm_cortex_m.rst +++ b/doc/hardware/arch/arm_cortex_m.rst @@ -442,7 +442,7 @@ are programmed during system boot. Arm memory map policies, allowing for privileged-only RWX permissions on SRAM). * All the memory regions defined in the devicetree with the compatible :dtcompatible:`zephyr,memory-region` and at least the property - ``zephyr,memory-region-mpu`` defining the MPU permissions for the memory region. + ``zephyr,memory-attr`` defining the MPU permissions for the memory region. See the next section for more details. The above MPU regions are defined in :file:`soc/arm/common/cortex_m/arm_mpu_regions.c`. @@ -455,11 +455,11 @@ Fixed MPU regions defined in devicetree The user can define memory regions to be allocated and created in the linker script using nodes with the :dtcompatible:`zephyr,memory-region` devicetree -compatible. When the property ``zephyr,memory-region-mpu`` is present in such +compatible. When the property ``zephyr,memory-attr`` is present in such a node, a new MPU region will be allocated and programmed during system boot. -The property ``zephyr,memory-region-mpu`` is a string carrying the attributes +The property ``zephyr,memory-attr`` is a string carrying the attributes for the MPU region. It is converted to a C token for use defining the attributes of the MPU region. @@ -471,7 +471,7 @@ For example, to define a new non-cacheable memory region in devicetree: compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20300000 0x100000>; zephyr,memory-region = "SRAM_NO_CACHE"; - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; This will automatically create a new MPU entry in diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c index dd617bf5d2cdbaf..14c491ea946f9ce 100644 --- a/drivers/adc/adc_stm32.c +++ b/drivers/adc/adc_stm32.c @@ -250,7 +250,7 @@ static int adc_stm32_dma_start(const struct device *dev, * The entire buffer must be in a single region. * An example of how the SRAM region can be defined in the DTS: * &sram4 { - * zephyr,memory-region-mpu = "RAM_NOCACHE"; + * zephyr,memory-attr = "RAM_NOCACHE"; * }; */ static bool address_in_non_cacheable_sram(const uint16_t *buffer, const uint16_t size) @@ -258,12 +258,12 @@ static bool address_in_non_cacheable_sram(const uint16_t *buffer, const uint16_t /* Default if no valid SRAM region found or buffer+size not located in a single region */ bool cachable = false; #define IS_NON_CACHEABLE_REGION_FN(node_id) \ - COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_region_mpu), ({ \ + COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), ({ \ const uint32_t region_start = DT_REG_ADDR(node_id); \ const uint32_t region_end = region_start + DT_REG_SIZE(node_id); \ if (((uint32_t)buffer >= region_start) && \ (((uint32_t)buffer + size) < region_end)) { \ - cachable = strcmp(DT_PROP(node_id, zephyr_memory_region_mpu), \ + cachable = strcmp(DT_PROP(node_id, zephyr_memory_attr), \ "RAM_NOCACHE") == 0; \ } \ }), \ diff --git a/drivers/dma/dma_stm32_bdma.c b/drivers/dma/dma_stm32_bdma.c index 8312f73dd642d36..797ed9ed794c43c 100644 --- a/drivers/dma/dma_stm32_bdma.c +++ b/drivers/dma/dma_stm32_bdma.c @@ -809,11 +809,11 @@ static int bdma_stm32_init(const struct device *dev) * This check verifies that the non-cachable flag is set in the DTS. * For example: * &sram4 { - * zephyr,memory-region-mpu = "RAM_NOCACHE"; + * zephyr,memory-attr = "RAM_NOCACHE"; * }; */ -#if DT_NODE_HAS_PROP(DT_NODELABEL(sram4), zephyr_memory_region_mpu) - if (strcmp(DT_PROP(DT_NODELABEL(sram4), zephyr_memory_region_mpu), "RAM_NOCACHE") != 0) { +#if DT_NODE_HAS_PROP(DT_NODELABEL(sram4), zephyr_memory_attr) + if (strcmp(DT_PROP(DT_NODELABEL(sram4), zephyr_memory_attr), "RAM_NOCACHE") != 0) { LOG_ERR("SRAM4 is not set as non-cachable."); return -EIO; } diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi index 26cdbd50c99d058..bbd71e2afa1f25b 100644 --- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi @@ -61,7 +61,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20010000 DT_SIZE_K(16)>; zephyr,memory-region = "USB_SRAM"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; }; diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi index 3aca92e41dcd8bf..5059d5d87f08356 100644 --- a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi @@ -75,7 +75,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x40100000 DT_SIZE_K(16)>; zephyr,memory-region = "USB_SRAM"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; }; diff --git a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi index 6f1abfac048ff29..ca14f43d6313833 100644 --- a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi @@ -95,7 +95,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x100000 DT_SIZE_K(16)>; zephyr,memory-region = "USB_SRAM"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; syscon: syscon@0 { diff --git a/dts/arm/nxp/nxp_rt5xx_common.dtsi b/dts/arm/nxp/nxp_rt5xx_common.dtsi index b9a3de432c42fc4..3cde4d50906585b 100644 --- a/dts/arm/nxp/nxp_rt5xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt5xx_common.dtsi @@ -49,7 +49,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x40140000 DT_SIZE_K(16)>; zephyr,memory-region = "SRAM1"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; }; diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi index fe77c0d121a9251..2fc4998e82d5b9d 100644 --- a/dts/arm/nxp/nxp_rt6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi @@ -48,7 +48,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x40140000 DT_SIZE_K(16)>; zephyr,memory-region = "SRAM1"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; }; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index ea585fadbd1d824..4519c6d65a90a62 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -47,7 +47,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x90000000 DT_SIZE_M(256)>; zephyr,memory-region = "QSPI"; - zephyr,memory-region-mpu = "EXTMEM"; + zephyr,memory-attr = "EXTMEM"; }; clocks { diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 012460b885a6f4e..a1de4f8cb54102d 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -48,7 +48,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x90000000 DT_SIZE_M(256)>; zephyr,memory-region = "QSPI"; - zephyr,memory-region-mpu = "EXTMEM"; + zephyr,memory-attr = "EXTMEM"; }; clocks { diff --git a/dts/bindings/base/zephyr,memory-region.yaml b/dts/bindings/base/zephyr,memory-region.yaml index f9db04e2d31ee6a..60308af7173a4e9 100644 --- a/dts/bindings/base/zephyr,memory-region.yaml +++ b/dts/bindings/base/zephyr,memory-region.yaml @@ -5,7 +5,7 @@ description: Compatible for devices resulting in linker memory regions compatible: "zephyr,memory-region" -include: base.yaml +include: [base.yaml, "zephyr,memory-attr.yaml"] properties: zephyr,memory-region: @@ -16,17 +16,3 @@ properties: memory region in the final executable. The region address and size is taken from the property, while the name is the value of this property. - - zephyr,memory-region-mpu: - type: string - enum: - - "RAM" - - "RAM_NOCACHE" - - "FLASH" - - "PPB" - - "IO" - - "EXTMEM" - description: | - Signify that this node should result in a dedicated MPU region. The - region address and size are taken from the property, while the MPU - attribute is the value of this property. diff --git a/include/zephyr/linker/devicetree_regions.h b/include/zephyr/linker/devicetree_regions.h index 1e37a3f22c28929..d60d3f9d7b176fc 100644 --- a/include/zephyr/linker/devicetree_regions.h +++ b/include/zephyr/linker/devicetree_regions.h @@ -92,8 +92,6 @@ #define _DT_SECTION_SIZE(node_id) UTIL_CAT(_DT_SECTION_PREFIX(node_id), _size) #define _DT_SECTION_LOAD(node_id) UTIL_CAT(_DT_SECTION_PREFIX(node_id), _load_start) -#define _DT_ATTR(token) UTIL_CAT(UTIL_CAT(REGION_, token), _ATTR) - /** * @brief Declare a memory region * @@ -162,35 +160,6 @@ _DT_SECTION_SIZE(node_id) = _DT_SECTION_END(node_id) - _DT_SECTION_START(node_id); \ _DT_SECTION_LOAD(node_id) = LOADADDR(LINKER_DT_NODE_REGION_NAME_TOKEN(node_id)); -/** - * Call the user-provided MPU_FN() macro passing the expected arguments - */ -#define _EXPAND_MPU_FN(node_id, MPU_FN, ...) \ - MPU_FN(LINKER_DT_NODE_REGION_NAME(node_id), \ - DT_REG_ADDR(node_id), \ - DT_REG_SIZE(node_id), \ - _DT_ATTR(DT_STRING_TOKEN(node_id, zephyr_memory_region_mpu))), - -/** - * Check that the node_id has both properties: - * - zephyr,memory-region-mpu - * - zephyr,memory-region - * - * and call the EXPAND_MPU_FN() macro - */ -#define _CHECK_ATTR_FN(node_id, EXPAND_MPU_FN, ...) \ - COND_CODE_1(UTIL_AND(DT_NODE_HAS_PROP(node_id, zephyr_memory_region_mpu), \ - DT_NODE_HAS_PROP(node_id, zephyr_memory_region)), \ - (EXPAND_MPU_FN(node_id, __VA_ARGS__)), \ - ()) - -/** - * Call _CHECK_ATTR_FN() for each enabled node passing EXPAND_MPU_FN() as - * explicit argument and the user-provided MPU_FN() macro in __VA_ARGS__ - */ -#define _CHECK_APPLY_FN(compat, EXPAND_MPU_FN, ...) \ - DT_FOREACH_STATUS_OKAY_VARGS(compat, _CHECK_ATTR_FN, EXPAND_MPU_FN, __VA_ARGS__) - /** @endcond */ /** @@ -211,87 +180,4 @@ #define LINKER_DT_SECTIONS() \ DT_FOREACH_STATUS_OKAY(_DT_COMPATIBLE, _SECTION_DECLARE) -/** - * @brief Generate MPU regions from the device tree nodes with compatible - * 'zephyr,memory-region' and 'zephyr,memory-region-mpu' attribute. - * - * Helper macro to apply an MPU_FN macro to all the memory regions declared - * using the 'zephyr,memory-region-mpu' property and the 'zephyr,memory-region' - * compatible. - * - * @p MPU_FN must take the form: - * - * @code{.c} - * #define MPU_FN(name, base, size, attr) ... - * @endcode - * - * The 'name', 'base' and 'size' parameters are taken from the DT node. - * - * The 'zephyr,memory-region-mpu' enum property is passed as an extended token - * to the MPU_FN macro using the 'attr' parameter, in the form - * REGION_{attr}_ATTR. - * - * The following enums are supported for the 'zephyr,memory-region-mpu' - * property: - * - * - RAM - * - RAM_NOCACHE - * - FLASH - * - PPB - * - IO - * - * This means that usually the arch code would provide some macros or defines - * with the same name of the extended property, that is: - * - * - REGION_RAM_ATTR - * - REGION_RAM_NOCACHE_ATTR - * - REGION_FLASH_ATTR - * - REGION_PPB_ATTR - * - REGION_IO_ATTR - * - * Example devicetree fragment: - * - * / { - * soc { - * sram1: memory@2000000 { - * zephyr,memory-region = "MY_NAME"; - * zephyr,memory-region-mpu = "RAM_NOCACHE"; - * }; - * }; - * }; - * - * For detailed information about MPU region attribute define configuration refer - * to the specific architecture MPU header. - * For example: include/zephyr/arch/arm/aarch32/mpu/arm_mpu_v7m.h. - * - * The 'attr' parameter of the MPU_FN function will be the extended - * 'REGION_RAM_NOCACHE_ATTR' token and the arch code will be usually - * implementing a macro with the same name. - * - * Example: - * - * @code{.c} - * - * #define REGION_RAM_NOCACHE_ATTR 0xAAAA - * #define REGION_RAM_ATTR 0xBBBB - * #define REGION_FLASH_ATTR 0xCCCC - * - * #define MPU_FN(p_name, p_base, p_size, p_attr) \ - * { \ - * .name = p_name, \ - * .base = p_base, \ - * .size = p_size, \ - * .attr = p_attr, \ - * } - * - * static const struct arm_mpu_region mpu_regions[] = { - * ... - * LINKER_DT_REGION_MPU(MPU_FN) - * ... - * }; - * @endcode - * - */ -#define LINKER_DT_REGION_MPU(mpu_fn) _CHECK_APPLY_FN(_DT_COMPATIBLE, _EXPAND_MPU_FN, mpu_fn) - #endif /* ZEPHYR_INCLUDE_LINKER_DEVICETREE_REGIONS_H_ */ diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay index 467595f18e0bd6e..52c68fd5339adda 100644 --- a/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay +++ b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_cm7.overlay @@ -17,6 +17,6 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay index 467595f18e0bd6e..52c68fd5339adda 100644 --- a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay @@ -17,6 +17,6 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay index 39e6c6896e7f724..a5d921810bbe405 100644 --- a/samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay @@ -17,6 +17,6 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay index ae2b4c56250ef17..fa4d29c3cd1d4cc 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_cm4.overlay @@ -33,7 +33,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_cm4.overlay index ae2b4c56250ef17..fa4d29c3cd1d4cc 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_cm4.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_cm4.overlay @@ -33,7 +33,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evkb_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evkb_cm4.overlay index 9cdfe651f05556f..f4ee15de7edd5a7 100644 --- a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evkb_cm4.overlay +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evkb_cm4.overlay @@ -33,7 +33,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x202c0000 DT_SIZE_K(16)>; zephyr,memory-region="OCRAM2_OVERLAY"; - zephyr,memory-region-mpu = "IO"; + zephyr,memory-attr = "IO"; }; }; diff --git a/soc/arm/common/cortex_m/arm_mpu_regions.c b/soc/arm/common/cortex_m/arm_mpu_regions.c index 477dc30566c7dc4..512cd4441cd32b0 100644 --- a/soc/arm/common/cortex_m/arm_mpu_regions.c +++ b/soc/arm/common/cortex_m/arm_mpu_regions.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include "arm_mpu_mem_cfg.h" @@ -31,7 +31,7 @@ static const struct arm_mpu_region mpu_regions[] = { #endif /* DT-defined regions */ - LINKER_DT_REGION_MPU(ARM_MPU_REGION_INIT) + DT_MEMORY_ATTR_APPLY(ARM_MPU_REGION_INIT) }; const struct arm_mpu_config mpu_config = { diff --git a/soc/arm/st_stm32/stm32h7/mpu_regions.c b/soc/arm/st_stm32/stm32h7/mpu_regions.c index 03a43a20d24180d..e253d70c7aef34f 100644 --- a/soc/arm/st_stm32/stm32h7/mpu_regions.c +++ b/soc/arm/st_stm32/stm32h7/mpu_regions.c @@ -5,7 +5,6 @@ */ #include -#include #include "../../common/cortex_m/arm_mpu_mem_cfg.h" static const struct arm_mpu_region mpu_regions[] = { @@ -32,7 +31,7 @@ static const struct arm_mpu_region mpu_regions[] = { #endif /* DT-defined regions */ - LINKER_DT_REGION_MPU(ARM_MPU_REGION_INIT) + DT_MEMORY_ATTR_APPLY(ARM_MPU_REGION_INIT) }; const struct arm_mpu_config mpu_config = { diff --git a/soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c b/soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c index ab261e2e45dba26..65400c672692cf0 100644 --- a/soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c +++ b/soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c @@ -7,7 +7,7 @@ #include #include -#include +#include #include static const struct arm_mpu_region mpu_regions[] = { @@ -41,7 +41,7 @@ static const struct arm_mpu_region mpu_regions[] = { REGION_RAM_ATTR), /* Extra regions defined in device tree */ - LINKER_DT_REGION_MPU(MPU_REGION_ENTRY_FROM_DTS) + DT_MEMORY_ATTR_APPLY(MPU_REGION_ENTRY_FROM_DTS) }; const struct arm_mpu_config mpu_config = { diff --git a/tests/arch/arm/arm_mpu_regions/boards/mps2_an385.overlay b/tests/arch/arm/arm_mpu_regions/boards/mps2_an385.overlay index e882e13075d1bef..4c9f1a5d5a8daa9 100644 --- a/tests/arch/arm/arm_mpu_regions/boards/mps2_an385.overlay +++ b/tests/arch/arm/arm_mpu_regions/boards/mps2_an385.overlay @@ -16,21 +16,21 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20200000 0x100000>; zephyr,memory-region = "SRAM_CACHE"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; sram_no_cache: memory@20300000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20300000 0x100000>; zephyr,memory-region = "SRAM_NO_CACHE"; - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; sram_dtcm_fake: memory@abcdabcd { compatible = "zephyr,memory-region", "arm,dtcm"; reg = <0xabcdabcd 0x100000>; zephyr,memory-region = "SRAM_DTCM_FAKE"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; sram_no_mpu: memory@deaddead { diff --git a/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay b/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay index af004e793710c5d..22590af7af4b706 100644 --- a/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay +++ b/tests/drivers/adc/adc_dma/boards/nucleo_h743zi.overlay @@ -22,7 +22,7 @@ /* ADC driver expects a buffer in a non-cachable memory region */ &sram4 { - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; &dma1 { diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay index 2114d8959bd3c08..20c8062f325e08c 100644 --- a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay +++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_h743zi.overlay @@ -18,7 +18,7 @@ test_dma0: &dmamux1 { * to be non-cachable. */ &sram4 { - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; &bdma1 { diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay index 2114d8959bd3c08..20c8062f325e08c 100644 --- a/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay +++ b/tests/drivers/dma/loop_transfer/boards/nucleo_h743zi.overlay @@ -18,7 +18,7 @@ test_dma0: &dmamux1 { * to be non-cachable. */ &sram4 { - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; &bdma1 { diff --git a/tests/kernel/mem_heap/shared_multi_heap/boards/mps2_an521.overlay b/tests/kernel/mem_heap/shared_multi_heap/boards/mps2_an521.overlay index 81e572475e232bf..c52183dfe81b5f5 100644 --- a/tests/kernel/mem_heap/shared_multi_heap/boards/mps2_an521.overlay +++ b/tests/kernel/mem_heap/shared_multi_heap/boards/mps2_an521.overlay @@ -17,20 +17,20 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x38100000 0x1000>; zephyr,memory-region = "RES0"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; res1: memory@38200000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x38200000 0x2000>; zephyr,memory-region = "RES1"; - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; res2: memory@38300000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x38300000 0x3000>; zephyr,memory-region = "RES2"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; }; diff --git a/tests/kernel/mem_heap/shared_multi_heap/boards/qemu_cortex_a53.overlay b/tests/kernel/mem_heap/shared_multi_heap/boards/qemu_cortex_a53.overlay index 90b0aeca8ac0e6d..a4ec256ad171092 100644 --- a/tests/kernel/mem_heap/shared_multi_heap/boards/qemu_cortex_a53.overlay +++ b/tests/kernel/mem_heap/shared_multi_heap/boards/qemu_cortex_a53.overlay @@ -10,14 +10,14 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 0x42000000 0x0 0x1000>; zephyr,memory-region = "RES0"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; res1: memory@43000000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 0x43000000 0x0 0x2000>; zephyr,memory-region = "RES1"; - zephyr,memory-region-mpu = "RAM_NOCACHE"; + zephyr,memory-attr = "RAM_NOCACHE"; }; res_no_mpu: memory@45000000 { @@ -30,7 +30,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 0x44000000 0x0 0x3000>; zephyr,memory-region = "RES2"; - zephyr,memory-region-mpu = "RAM"; + zephyr,memory-attr = "RAM"; }; }; }; diff --git a/tests/kernel/mem_heap/shared_multi_heap/src/main.c b/tests/kernel/mem_heap/shared_multi_heap/src/main.c index 17dc081f06e036d..c99264430bc3f38 100644 --- a/tests/kernel/mem_heap/shared_multi_heap/src/main.c +++ b/tests/kernel/mem_heap/shared_multi_heap/src/main.c @@ -27,7 +27,7 @@ struct region_map { .region = { \ .addr = (uintptr_t) DT_INST_REG_ADDR(n), \ .size = DT_INST_REG_SIZE(n), \ - .attr = DT_INST_ENUM_IDX_OR(n, zephyr_memory_region_mpu, \ + .attr = DT_INST_ENUM_IDX_OR(n, zephyr_memory_attr, \ SMH_REG_ATTR_NUM), \ }, \ }, @@ -103,7 +103,7 @@ static void fill_multi_heap(void) for (size_t idx = 0; idx < DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT); idx++) { reg_map = &map[idx]; - /* zephyr,memory-region-mpu property not found. Skip it. */ + /* zephyr,memory-attr property not found. Skip it. */ if (reg_map->region.attr == SMH_REG_ATTR_NUM) { continue; }