From 9c0f92db475f0e27673ac366276026eddf1a150c Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Thu, 19 Sep 2024 17:22:54 -0500 Subject: [PATCH] boards: shields: rk055hdmipi4ma0: raise MIPI DSI bit clock for RT1170 The RT1170 MIPI DPHY requires a faster clock frequency setting for the MIPI DPHY, or the pixel packet counts for the HFP, HBP, and HSA will be incorrect, and the DSI transfers will stall. Raise the target DPHY clock frequency to resolve this. Fixes #78299 Signed-off-by: Daniel DeGrasse --- .../boards/mimxrt1170_evk_mimxrt1176_cm7.overlay | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay new file mode 100644 index 00000000000000..7578cac75c2662 --- /dev/null +++ b/boards/shields/rk055hdmipi4ma0/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay @@ -0,0 +1,10 @@ +/* + * Copyright 2024, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&zephyr_mipi_dsi { + /* Raise the DSI clock frequency */ + phy-clock = <792000000>; +};