communication between Imx8mp and Nor Flash

[mbahmani90]

Hi,

Hope you are all well.

I want to communicate with nor flash through QSPI in Imx8mp_evk. Is there any library for this purpose?

I also read the datasheet and try to access and change some configuration registers with IP command. but the result is meaningless.

According to "IMX8MPRM.pdf"
In this code I try to

1. enable/disable write (page 2431)
2. read status register (page 2433)

according to nor flash datasheet the bit(7) should change but the problem is that in "write enable" mode the status register is 1 and in "write disable" mode the status register is 0:

Can anyone tell me where I am making mistake?

#define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (8)

#include <stdio.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include "../../modules/hal/nxp/mcux/mcux-sdk/drivers/flexspi/fsl_flexspi.h"

#define FLEXSPI_INSTANCE      FLEXSPI1
#define FLEXSPI_PORT          kFLEXSPI_PortA1
#define LUT_INDEX_WRITE       0

#define DISABLE_WRITE_CMD     0x04
#define ENABLE_WRITE_CMD      0x06
#define READ_STATUS_REG_CMD   0x05
#define WRITE_STATUS_REG_CMD  0x01
#define WRITE_NONVOLATILE_CONFIGURATION_REGISTER_CMD  0xB1
#define READ_NONVOLATILE_CONFIGURATION_REGISTER_CMD   0xB5

#define FLEXSPI_BASE_ADDR     0x30BB0000
#define FLEXSPI_CCM_CCGR      0x303842F0

#define MCR0_ADDR             (FLEXSPI_BASE_ADDR + 0x00)  
#define IPCR0_ADDR            (FLEXSPI_BASE_ADDR + 0xA0)  // Serial Flash Address for IP command.
#define IPCR1_ADDR            (FLEXSPI_BASE_ADDR + 0xA4)  // Data Size, Seq Index, Seq number, Parallel/Individual
#define IPCMD_ADDR            (FLEXSPI_BASE_ADDR + 0xB0)  // Trigger IP command
#define IPRXFCR_ADDR          (FLEXSPI_BASE_ADDR + 0xB8)  // IP RX FIFO Control Register
#define INTEN_ADDR            (FLEXSPI_BASE_ADDR + 0x10)  // Interrupt Enable Register
#define INTR_ADDR             (FLEXSPI_BASE_ADDR + 0x14)  // Interrupt Status Register
#define IP_RX_FIFO_ADDR       (FLEXSPI_BASE_ADDR + 0x100) // IP RX data register RFDR0 - RFDR31
#define IP_TX_FIFO_ADDR       (FLEXSPI_BASE_ADDR + 0x180) // IP TX data register TFDR0 - TFDR31
#define LUT_BASE_ADDR         (FLEXSPI_BASE_ADDR + 0x200) // Look Up Table

#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x303300F8
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x303300FC
// #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x30330100
#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x30330104
#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE    0x303300E0
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B  0x303300E4 
#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B  0x303300E8 

#define CCM_TARGET_ROOT87_ADDR  0x3038AB80 // QSPI_CLK_ROOT

#define ALT1_FLEXSPI_A_DATA  0x00000001
#define ALT1_FLEXSPI_A_SCLK  0x00000001
#define ALT1_FLEXSPI_A_SS0_B 0x00000001
#define ALT1_FLEXSPI_A_SS1_B 0x00000001

#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1)	   \
	(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | \
	 FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) |   \
	 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))


int x = 0;

void flexspi_init_pinmux(){

    uint32_t *nand_data00 = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00);
    uint32_t *nand_data01 = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01);
    // uint32_t *nand_data02 = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02);
    uint32_t *nand_data03 = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03);
    uint32_t *nand_ale    = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_ALE);
    uint32_t *nand_ce0_b  = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B);
    uint32_t *nand_ce1_b  = ((uint32_t *) IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B);

    *nand_data00 = ALT1_FLEXSPI_A_DATA;
    *nand_data01 = ALT1_FLEXSPI_A_DATA;
    // *nand_data02 = ALT1_FLEXSPI_A_DATA;
    *nand_data03 = ALT1_FLEXSPI_A_DATA;
    *nand_ale    = ALT1_FLEXSPI_A_SCLK;
    *nand_ce0_b  = ALT1_FLEXSPI_A_SS0_B;
    *nand_ce1_b  = ALT1_FLEXSPI_A_SS1_B;
    
}

// Function to perform a write transfer using the specified port
status_t flexspi_write_data()//(FLEXSPI_Type *base, uint32_t address, uint32_t *data, size_t dataSize)
{
    // flexspi_transfer_t flashXfer;
    status_t status = 0;
    
    uint32_t *flexspi_ccm = ((uint32_t *) CCM_TARGET_ROOT87_ADDR);
    uint32_t *flexspi_mcr0 = ((uint32_t *) MCR0_ADDR);
    uint32_t *flexspi_ipcr0 = ((uint32_t *) IPCR0_ADDR);
    uint32_t *lut_base0 = ((uint32_t *) (LUT_BASE_ADDR + 0x0));
    uint32_t *lut_base1 = ((uint32_t *) (LUT_BASE_ADDR + 0x4));
    uint32_t *lut_base2 = ((uint32_t *) (LUT_BASE_ADDR + 0x8));
    uint32_t *lut_base3 = ((uint32_t *) (LUT_BASE_ADDR + 0xC));
    uint32_t *ipcr1 = ((uint32_t *) IPCR1_ADDR);
    uint32_t *ipcmd = ((uint32_t *) IPCMD_ADDR);
    uint32_t *iprxfcr = ((uint32_t *) IPRXFCR_ADDR);
    uint32_t *inten = ((uint32_t *) INTEN_ADDR);
    uint32_t *intr = ((uint32_t *) INTR_ADDR);
    uint32_t *flexspi_ccm_ccgr = ((uint32_t *) FLEXSPI_CCM_CCGR);
    uint32_t *flexspi_ip_rx = ((uint32_t *) IP_RX_FIFO_ADDR);
    uint32_t *flexspi_ip_rx2 = ((uint32_t *) (IP_RX_FIFO_ADDR + 4));
    uint32_t *flexspi_ip_tx1 = ((uint32_t *) IP_TX_FIFO_ADDR);
    uint32_t *flexspi_ip_tx2 = ((uint32_t *) (IP_TX_FIFO_ADDR + 4));
    uint32_t *flexspi_ip_tx3 = ((uint32_t *) (IP_TX_FIFO_ADDR + 8));
    
    flexspi_init_pinmux();

    *flexspi_ccm = 0x1100001;
    printf("CCM: 0x%x\r\n" , *flexspi_ccm);
    *flexspi_ccm_ccgr = 0x00000030;
    printf("CCRG: 0x%x\r\n" , *flexspi_ccm_ccgr);
    *flexspi_mcr0 = 0xFFFF0000;
    printf("MCR0: 0x%x\r\n" , *flexspi_mcr0);
    *inten = 0xFFF;
    printf("INTEN: 0x%x\r\n" , *inten);
    
    *flexspi_ip_tx1 = 0x00000000;
    *flexspi_ip_tx2 = 0;//0x35363738;
    *flexspi_ip_tx3 = 0;//0x494A4B4C;
    printf("IP_TX: 0x%x , 0x%x , 0x%x\r\n" , *(flexspi_ip_tx1 + 0) , *(flexspi_ip_tx2 + 0) , *(flexspi_ip_tx3 + 0));

    *flexspi_ipcr0 = 0x00000008;
    printf("IPCR0: 0x%x\r\n" , *flexspi_ipcr0);

    uint32_t idatasz = 2;
    uint32_t seq_index = 0;
    uint32_t seq_num = 1;

    if(x == 0){
        
        idatasz = 0;
        seq_index = 0;
        seq_num = 1;
        
        printf("Enable write\r\n");  
        uint32_t lut_enable_write_opt = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, ENABLE_WRITE_CMD, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0);

        *lut_base0 = lut_enable_write_opt;
        *lut_base1 = 0;
        *lut_base2 = 0;
        *lut_base3 = 0;
        x++;    


    }

    else if(x == 1){

        idatasz = 1;
        seq_index = 0;
        seq_num = 1;

        printf("Read status\r\n");
        uint32_t lut_read_status_opt = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, READ_STATUS_REG_CMD,
                                                       kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x4);
                                                        
        uint32_t lut_stop_opt = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0,
                                                kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0);
                                                        
        *lut_base0 = lut_read_status_opt;
        *lut_base1 = 0;
        *lut_base2 = 0;
        *lut_base3 = 0;  
        x = 0;
        
    }

    printf("LUT: 0x%x , 0x%x , 0x%x , 0x%x\r\n" , *lut_base0 , *lut_base1 , *lut_base2 , *lut_base3);
    
    *flexspi_ccm = 0x111000F;
    *ipcr1 = ((seq_num - 1) << 24) | (seq_index << 16) | (idatasz);
    *ipcmd |= 1;
    
    while( !(*intr & 1) ){
        printf("COM and STATUS: %x %x %x\r\n", *ipcmd, *ipcr1, *intr);
        k_msleep(1000);
    }
    k_msleep(1000);

    printf("IP RX CMD: x: %d , %x , %x\r\n" , x , *flexspi_ip_rx , *flexspi_ip_rx2);
    printf("\r\n------------------------------------\r\n");

    *iprxfcr |= 0x1;
    *intr = 0xFFF;


    return status;
}

int main(void)
{
	// flexspi_transfer_t flashXfer;
    // long unsigned int *gpio_setdataout  = ((long unsigned int *) 0x30240000);
	// *gpio_direction = 0x000FC320;
    printf("%s %s %s\r\n" , __FILE__ , __DATE__ , __TIME__);

    long unsigned int *gpio_setdataout_addr  = ((long unsigned int *) 0x30220000);
    long unsigned int *gpio_direction_addr   = ((long unsigned int *) 0x30220004);

	*gpio_direction_addr |= (1 << 8);
	*gpio_setdataout_addr |= (1 << 8);

	while (1) {
        
        flexspi_write_data();	
		k_msleep(1000);

	}
	
	return 0;
}