From 8e10b428880d1cfff5841251b64390e2ac03ebc9 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 6 Jul 2023 12:17:46 +0200 Subject: [PATCH 1/4] drivers: pinctrl: add driver for EOS S3 This adds a new pinctrl driver for Quicklogic EOS S3 SoC Signed-off-by: Wojciech Sipak --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.eos_s3 | 9 ++ drivers/pinctrl/pinctrl_eos_s3.c | 128 ++++++++++++++++++ drivers/serial/Kconfig.pl011 | 1 + drivers/serial/Kconfig.ql_usbserialport_s3b | 1 + dts/arm/quicklogic/quicklogic_eos_s3.dtsi | 5 + .../pinctrl/quicklogic,eos-s3-pinctrl.yaml | 75 ++++++++++ .../pinctrl/quicklogic-eos-s3-pinctrl.h | 25 ++++ soc/arm/quicklogic_eos_s3/pinctrl_soc.h | 55 ++++++++ 10 files changed, 301 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.eos_s3 create mode 100644 drivers/pinctrl/pinctrl_eos_s3.c create mode 100644 dts/bindings/pinctrl/quicklogic,eos-s3-pinctrl.yaml create mode 100644 include/zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h create mode 100644 soc/arm/quicklogic_eos_s3/pinctrl_soc.h diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 521f1e61c19988..a14ee14286eac1 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -33,3 +33,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NUMAKER pinctrl_numaker.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 80551869d59503..cdecc3ae554b3f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -62,5 +62,6 @@ source "drivers/pinctrl/Kconfig.ti_k3" source "drivers/pinctrl/Kconfig.emsdp" source "drivers/pinctrl/Kconfig.ti_cc32xx" source "drivers/pinctrl/Kconfig.numaker" +source "drivers/pinctrl/Kconfig.eos_s3" endif # PINCTRL diff --git a/drivers/pinctrl/Kconfig.eos_s3 b/drivers/pinctrl/Kconfig.eos_s3 new file mode 100644 index 00000000000000..04d8cd1cbe172e --- /dev/null +++ b/drivers/pinctrl/Kconfig.eos_s3 @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_QUICKLOGIC_EOS_S3 + bool "QuickLogic EOS S3 SoC pinctrl driver" + default y + depends on DT_HAS_QUICKLOGIC_EOS_S3_PINCTRL_ENABLED + help + Enable driver for the QuickLogic EOS S3 SoC pinctrl driver diff --git a/drivers/pinctrl/pinctrl_eos_s3.c b/drivers/pinctrl/pinctrl_eos_s3.c new file mode 100644 index 00000000000000..5fcd62711da8dd --- /dev/null +++ b/drivers/pinctrl/pinctrl_eos_s3.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT quicklogic_eos_s3_pinctrl + +#include +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(pinctrl_eos_s3, CONFIG_PINCTRL_LOG_LEVEL); + +#define FUNCTION_REGISTER(func) (func >> 13) +#define PAD_FUNC_SEL_MASK GENMASK(2, 0) +#define PAD_CTRL_SEL_BIT0 3 +#define PAD_CTRL_SEL_BIT1 4 +#define PAD_OUTPUT_EN_BIT 5 +#define PAD_PULL_UP_BIT 6 +#define PAD_PULL_DOWN_BIT 7 +#define PAD_DRIVE_STRENGTH_BIT0 8 +#define PAD_DRIVE_STRENGTH_BIT1 9 +#define PAD_SLEW_RATE_BIT 10 +#define PAD_INPUT_EN_BIT 11 +#define PAD_SCHMITT_EN_BIT 12 + +/* + * Program IOMUX_func_SEL register. + */ +static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) +{ + volatile uint32_t *reg = (uint32_t *)IO_MUX_BASE; + + if (sel_reg <= IO_MUX_MAX_PAD_NR || sel_reg > IO_MUX_REG_MAX_OFFSET) { + return -EINVAL; + } + reg += sel_reg; + *reg = pin; + + return 0; +} + +/* + * Program IOMUX_PAD_x_CTRL register. + */ +static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) +{ + volatile uint32_t *reg = (uint32_t *)IO_MUX_BASE; + + if (pin > IO_MUX_REG_MAX_OFFSET) { + return -EINVAL; + } + reg += pin; + *reg = func; + + return 0; +} + +static int pinctrl_eos_s3_configure_pin(const pinctrl_soc_pin_t *pin) +{ + uint32_t reg_value = 0; + + /* Set function. */ + reg_value |= (pin->iof & PAD_FUNC_SEL_MASK); + + /* Output enable is active low. */ + WRITE_BIT(reg_value, PAD_OUTPUT_EN_BIT, pin->output_enable ? 0 : 1); + + /* These are active high. */ + WRITE_BIT(reg_value, PAD_INPUT_EN_BIT, pin->input_enable); + WRITE_BIT(reg_value, PAD_SLEW_RATE_BIT, pin->slew_rate); + WRITE_BIT(reg_value, PAD_SCHMITT_EN_BIT, pin->schmitt_enable); + WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT0, pin->control_selection & BIT(0)); + WRITE_BIT(reg_value, PAD_CTRL_SEL_BIT1, pin->control_selection & BIT(1)); + + switch (pin->drive_strength) { + case 2: + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0); + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0); + break; + case 4: + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1); + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 0); + break; + case 8: + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 0); + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1); + break; + case 12: + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT0, 1); + WRITE_BIT(reg_value, PAD_DRIVE_STRENGTH_BIT1, 1); + break; + default: + LOG_ERR("Selected drive-strength is not supported: %d\n", pin->drive_strength); + } + + /* Enable pull-up by default; overwrite if any setting was chosen. */ + WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 1); + WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, 0); + if (pin->high_impedance) { + WRITE_BIT(reg_value, PAD_PULL_UP_BIT, 0); + } else if (pin->pull_up | pin->pull_down) { + WRITE_BIT(reg_value, PAD_PULL_UP_BIT, pin->pull_up); + WRITE_BIT(reg_value, PAD_PULL_DOWN_BIT, pin->pull_down); + } + + /* Program registers. */ + pinctrl_eos_s3_set(pin->pin, reg_value); + if (pin->input_enable && FUNCTION_REGISTER(pin->iof)) { + pinctrl_eos_s3_input_selection(pin->pin, FUNCTION_REGISTER(pin->iof)); + } + return 0; +} + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + ARG_UNUSED(reg); + + for (int i = 0; i < pin_cnt; i++) { + pinctrl_eos_s3_configure_pin(&pins[i]); + } + + return 0; +} diff --git a/drivers/serial/Kconfig.pl011 b/drivers/serial/Kconfig.pl011 index 9c48001835a284..95dd947b9dccdc 100644 --- a/drivers/serial/Kconfig.pl011 +++ b/drivers/serial/Kconfig.pl011 @@ -7,6 +7,7 @@ menuconfig UART_PL011 depends on DT_HAS_ARM_PL011_ENABLED || DT_HAS_ARM_SBSA_UART_ENABLED select SERIAL_HAS_DRIVER select SERIAL_SUPPORT_INTERRUPT + select PINCTRL if SOC_EOS_S3 help This option enables the UART driver for the PL011 diff --git a/drivers/serial/Kconfig.ql_usbserialport_s3b b/drivers/serial/Kconfig.ql_usbserialport_s3b index 197d26f5faf496..b989c91516e521 100644 --- a/drivers/serial/Kconfig.ql_usbserialport_s3b +++ b/drivers/serial/Kconfig.ql_usbserialport_s3b @@ -8,5 +8,6 @@ config UART_QUICKLOGIC_USBSERIALPORT_S3B default y depends on DT_HAS_QUICKLOGIC_USBSERIALPORT_S3B_ENABLED select SERIAL_HAS_DRIVER + select PINCTRL help This option enables the QuickLogic USBserialport_S3B serial driver. diff --git a/dts/arm/quicklogic/quicklogic_eos_s3.dtsi b/dts/arm/quicklogic/quicklogic_eos_s3.dtsi index 8d3f3998e3091a..f29b1c482ffdc3 100644 --- a/dts/arm/quicklogic/quicklogic_eos_s3.dtsi +++ b/dts/arm/quicklogic/quicklogic_eos_s3.dtsi @@ -64,6 +64,11 @@ pin-secondary-config = <0x00>; gpio-controller; }; + + pinctrl: pinctrl@40004c00 { + compatible = "quicklogic,eos-s3-pinctrl"; + reg = <0x40004c00 0x1b0>; + }; }; }; diff --git a/dts/bindings/pinctrl/quicklogic,eos-s3-pinctrl.yaml b/dts/bindings/pinctrl/quicklogic,eos-s3-pinctrl.yaml new file mode 100644 index 00000000000000..cd9cd5ac532403 --- /dev/null +++ b/dts/bindings/pinctrl/quicklogic,eos-s3-pinctrl.yaml @@ -0,0 +1,75 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +description: | + Quicklogic EOS S3 IO MUX binding covers the 46 IOMUX_PAD_x_CTRL registers + that can be used to set the direction and the function of a pad. + + Device pin configuration should be placed in the child nodes of this node. + Populate the 'pinmux' field with IO function and pin number. + + For example, setting pins 44 and 45 for use as UART would look like this: + + #include + + &pinctrl { + uart0_rx_default: uart0_rx_default { + pinmux = ; + input-enable; + }; + uart0_tx_default: uart0_tx_default { + pinmux = ; + output-enable; + }; + }; + +compatible: "quicklogic,eos-s3-pinctrl" + +include: base.yaml + +properties: + reg: + required: true + +child-binding: + description: | + This binding gives a base representation of the SiFive FE310 pins + configuration. + + include: + - name: pincfg-node.yaml + property-allowlist: + - input-enable + - output-enable + - bias-pull-up + - bias-pull-down + - bias-high-impedance + - input-schmitt-enable + - drive-strength + properties: + pinmux: + required: true + type: array + description: | + Quicklogic EOS S3 pin's configuration (pin, IO function). + slew-rate: + description: | + The default value "slow" matches the power-on reset value. + default: "slow" + type: string + enum: + - "slow" + - "fast" + quicklogic,control-selection: + description: | + Control selection for IO output. + It's either controlled from registers of the A0 always-on domain, + fabric-controlled for signaling with FPGA, + or other-controller for bidirectional signals. + The default value "a0registers" matches the power-on reset value. + default: "a0registers" + type: string + enum: + - "a0registers" + - "others" + - "fabric" diff --git a/include/zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h new file mode 100644 index 00000000000000..b49e2141444ab2 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_QUICKLOGIC_EOS_S3_PINCTRL_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_QUICKLOGIC_EOS_S3_PINCTRL_H_ + +#include + +#define IO_MUX_REG_MAX_OFFSET 107 +#define IO_MUX_MAX_PAD_NR 45 + +#define FUNC_SEL_UART_RX (77 << 13) + +#define QUICKLOGIC_EOS_S3_PINMUX(pin, fun) (pin) (fun) + +#define UART_TX_PAD44 QUICKLOGIC_EOS_S3_PINMUX(44, 0x3) +#define UART_RX_PAD45 QUICKLOGIC_EOS_S3_PINMUX(45, FUNC_SEL_UART_RX | BIT(2)) +#define USB_PU_CTRL_PAD23 QUICKLOGIC_EOS_S3_PINMUX(23, 0x0) +#define USB_DN_PAD28 QUICKLOGIC_EOS_S3_PINMUX(28, 0x0) +#define USB_DP_PAD31 QUICKLOGIC_EOS_S3_PINMUX(31, 0x0) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_QUICKLOGIC_EOS_S3_PINCTRL_H_ */ diff --git a/soc/arm/quicklogic_eos_s3/pinctrl_soc.h b/soc/arm/quicklogic_eos_s3/pinctrl_soc.h new file mode 100644 index 00000000000000..957129a3d0e3a8 --- /dev/null +++ b/soc/arm/quicklogic_eos_s3/pinctrl_soc.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2023 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_QUICKLOGIC_EOS_S3_PINCTRL_H_ +#define ZEPHYR_SOC_ARM_QUICKLOGIC_EOS_S3_PINCTRL_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct pinctrl_soc_pin_t { + uint32_t pin; + uint32_t iof; + uint32_t input_enable: 1; + uint32_t output_enable: 1; + uint32_t pull_up: 1; + uint32_t pull_down: 1; + uint32_t high_impedance: 1; + uint32_t slew_rate: 2; + uint8_t drive_strength; + uint32_t schmitt_enable: 1; + uint32_t control_selection: 2; +} pinctrl_soc_pin_t; + +#define QUICKLOGIC_EOS_S3_DT_PIN(node_id) \ + { \ + .pin = DT_PROP_BY_IDX(node_id, pinmux, 0), \ + .iof = DT_PROP_BY_IDX(node_id, pinmux, 1), \ + .input_enable = DT_PROP(node_id, input_enable), \ + .output_enable = DT_PROP(node_id, output_enable), \ + .pull_up = DT_PROP(node_id, bias_pull_up), \ + .pull_down = DT_PROP(node_id, bias_pull_down), \ + .high_impedance = DT_PROP(node_id, bias_high_impedance), \ + .slew_rate = DT_ENUM_IDX(node_id, slew_rate), \ + .drive_strength = DT_PROP_OR(node_id, drive_strength, 4), \ + .schmitt_enable = DT_PROP(node_id, input_schmitt_enable), \ + .control_selection = DT_ENUM_IDX(node_id, quicklogic_control_selection), \ + }, + +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ + QUICKLOGIC_EOS_S3_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_QUICKLOGIC_EOS_S3_PINCTRL_H_ */ From 8f67d14c334473798a32fe85c3efb649de21d84e Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 6 Jul 2023 12:18:50 +0200 Subject: [PATCH 2/4] boards: quick_feather: use pinctrl driver Pinmuxing was previously done in the board.c file. Now it is done by the pinctrl driver. Signed-off-by: Wojciech Sipak --- boards/arm/quick_feather/CMakeLists.txt | 5 ----- boards/arm/quick_feather/board.c | 23 ---------------------- boards/arm/quick_feather/board.h | 19 ------------------ boards/arm/quick_feather/quick_feather.dts | 14 +++++++++++++ 4 files changed, 14 insertions(+), 47 deletions(-) delete mode 100644 boards/arm/quick_feather/CMakeLists.txt delete mode 100644 boards/arm/quick_feather/board.c delete mode 100644 boards/arm/quick_feather/board.h diff --git a/boards/arm/quick_feather/CMakeLists.txt b/boards/arm/quick_feather/CMakeLists.txt deleted file mode 100644 index 77aee051c0c72c..00000000000000 --- a/boards/arm/quick_feather/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(board.c) -zephyr_include_directories(.) diff --git a/boards/arm/quick_feather/board.c b/boards/arm/quick_feather/board.c deleted file mode 100644 index cf89c208ced0dd..00000000000000 --- a/boards/arm/quick_feather/board.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2020 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -static int eos_s3_board_init(void) -{ - - /* IO MUX setup for UART */ - eos_s3_io_mux(UART_TX_PAD, UART_TX_PAD_CFG); - eos_s3_io_mux(UART_RX_PAD, UART_RX_PAD_CFG); - - IO_MUX->UART_rxd_SEL = UART_RX_SEL; - - return 0; -} - -SYS_INIT(eos_s3_board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/arm/quick_feather/board.h b/boards/arm/quick_feather/board.h deleted file mode 100644 index 857a6edd037270..00000000000000 --- a/boards/arm/quick_feather/board.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2020 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __INC_BOARD_H -#define __INC_BOARD_H - -#include - -#define UART_TX_PAD 44 -#define UART_TX_PAD_CFG UART_TXD_PAD44 -#define UART_RX_PAD 45 -#define UART_RX_PAD_CFG UART_RXD_PAD45 - -#define UART_RX_SEL UART_RXD_SEL_PAD45 - -#endif /* __INC_BOARD_H */ diff --git a/boards/arm/quick_feather/quick_feather.dts b/boards/arm/quick_feather/quick_feather.dts index 9bde6c938c3490..2dc8053255a04a 100644 --- a/boards/arm/quick_feather/quick_feather.dts +++ b/boards/arm/quick_feather/quick_feather.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "QuickLogic Quick Feather board"; @@ -56,6 +57,17 @@ }; }; +&pinctrl { + uart_rx_default: uart_rx_default { + pinmux = ; + input-enable; + }; + uart_tx_default: uart_tx_default { + pinmux = ; + output-enable; + }; +}; + &cpu0 { clock-frequency = <61440000>; }; @@ -67,4 +79,6 @@ &uart0 { status = "okay"; current-speed = <115200>; + pinctrl-0 = <&uart_rx_default &uart_tx_default>; + pinctrl-names = "default"; }; From aeaf851c5bc1992b3264f068eb70373b76629706 Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 6 Jul 2023 12:19:36 +0200 Subject: [PATCH 3/4] boards: qomu: use pinctrl driver Pinmuxing was previously done in the board.c file. Now it is done by the pinctrl driver. Signed-off-by: Wojciech Sipak --- boards/arm/qomu/CMakeLists.txt | 4 ---- boards/arm/qomu/board.c | 28 ---------------------------- boards/arm/qomu/board.h | 25 ------------------------- boards/arm/qomu/qomu.dts | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 33 insertions(+), 57 deletions(-) delete mode 100644 boards/arm/qomu/CMakeLists.txt delete mode 100644 boards/arm/qomu/board.c delete mode 100644 boards/arm/qomu/board.h diff --git a/boards/arm/qomu/CMakeLists.txt b/boards/arm/qomu/CMakeLists.txt deleted file mode 100644 index a17def9a23147a..00000000000000 --- a/boards/arm/qomu/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2022 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(board.c) diff --git a/boards/arm/qomu/board.c b/boards/arm/qomu/board.c deleted file mode 100644 index d6752dff91338c..00000000000000 --- a/boards/arm/qomu/board.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2022 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "board.h" - -static int qomu_board_init(void) -{ - - /* IO MUX setup for UART */ - eos_s3_io_mux(UART_TX_PAD, UART_TX_PAD_CFG); - eos_s3_io_mux(UART_RX_PAD, UART_RX_PAD_CFG); - - IO_MUX->UART_rxd_SEL = UART_RX_SEL; - - /* IO MUX setup for USB */ - eos_s3_io_mux(USB_PU_CTRL_PAD, USB_PAD_CFG); - eos_s3_io_mux(USB_DN_PAD, USB_PAD_CFG); - eos_s3_io_mux(USB_DP_PAD, USB_PAD_CFG); - - return 0; -} - -SYS_INIT(qomu_board_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/arm/qomu/board.h b/boards/arm/qomu/board.h deleted file mode 100644 index 9bcd5820b10f23..00000000000000 --- a/boards/arm/qomu/board.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2022 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __INC_BOARD_H -#define __INC_BOARD_H - -#include - -#define USB_PU_CTRL_PAD 23 -#define USB_DN_PAD 28 -#define USB_DP_PAD 31 -#define USB_PAD_CFG (PAD_E_4MA | PAD_P_Z | PAD_OEN_NORMAL | PAD_SMT_DISABLE \ - | PAD_REN_DISABLE | PAD_SR_SLOW | PAD_CTRL_SEL_FPGA) - -#define UART_TX_PAD 44 -#define UART_TX_PAD_CFG UART_TXD_PAD44 -#define UART_RX_PAD 45 -#define UART_RX_PAD_CFG UART_RXD_PAD45 - -#define UART_RX_SEL UART_RXD_SEL_PAD45 - -#endif /* __INC_BOARD_H */ diff --git a/boards/arm/qomu/qomu.dts b/boards/arm/qomu/qomu.dts index c58825a5f4f660..dfdb9a14c18c6c 100644 --- a/boards/arm/qomu/qomu.dts +++ b/boards/arm/qomu/qomu.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include / { model = "QuickLogic Qomu board"; @@ -56,6 +57,35 @@ }; }; +&pinctrl { + uart1_rx_default: uart1_rx_default { + pinmux = ; + input-enable; + }; + uart1_tx_default: uart1_tx_default { + pinmux = ; + output-enable; + }; + usb_pu_default: usb_pu_default { + pinmux = ; + bias-high-impedance; + quicklogic,control-selection = "fabric"; + output-enable; + }; + usb_dn_default: usb_dn_default { + pinmux = ; + bias-high-impedance; + quicklogic,control-selection = "fabric"; + output-enable; + }; + usb_dp_default: usb_dp_default { + pinmux = ; + bias-high-impedance; + quicklogic,control-selection = "fabric"; + output-enable; + }; +}; + &cpu0 { clock-frequency = <61440000>; }; @@ -71,4 +101,7 @@ &uart1 { status = "okay"; current-speed = <115200>; + pinctrl-0 = <&uart1_rx_default &uart1_tx_default + &usb_pu_default &usb_dn_default &usb_dp_default>; + pinctrl-names = "default"; }; From 6f775f6d8df6e075e0db3d5984b91a8685d2132f Mon Sep 17 00:00:00 2001 From: Wojciech Sipak Date: Thu, 6 Jul 2023 12:20:21 +0200 Subject: [PATCH 4/4] soc: quicklogic_eos_s3: remove unneeded code Pinmuxing is now done by a pinctrl driver, not by board.c, so the code used previously for pinmuxing can be removed. Fixes #59186. Signed-off-by: Wojciech Sipak --- soc/arm/quicklogic_eos_s3/soc.c | 14 -------------- soc/arm/quicklogic_eos_s3/soc.h | 4 ---- soc/arm/quicklogic_eos_s3/soc_pinmap.h | 10 ---------- 3 files changed, 28 deletions(-) diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/arm/quicklogic_eos_s3/soc.c index 81d070df427cb5..ed2cdb70ef9643 100644 --- a/soc/arm/quicklogic_eos_s3/soc.c +++ b/soc/arm/quicklogic_eos_s3/soc.c @@ -20,20 +20,6 @@ void eos_s3_lock_disable(void) MISC_CTRL->LOCK_KEY_CTRL = 1; } -int eos_s3_io_mux(uint32_t pad_nr, uint32_t pad_cfg) -{ - volatile uint32_t *p = (uint32_t *)IO_MUX_BASE; - - if (pad_nr > EOS_S3_MAX_PAD_NR) { - return -EINVAL; - } - - p += pad_nr; - *p = pad_cfg; - - return 0; -} - static void eos_s3_cru_init(void) { /* Set desired frequency */ diff --git a/soc/arm/quicklogic_eos_s3/soc.h b/soc/arm/quicklogic_eos_s3/soc.h index b294be96e9bbab..a82e5399248c88 100644 --- a/soc/arm/quicklogic_eos_s3/soc.h +++ b/soc/arm/quicklogic_eos_s3/soc.h @@ -46,11 +46,7 @@ #define OSC_SET_FREQ_INC(FREQ) (AIP->OSC_CTRL_1 = ((FREQ / 32768) - 3) & 0xFFF) #define OSC_GET_FREQ_INC() (((AIP->OSC_CTRL_1 & 0xFFF) + 3) * 32768) -#define EOS_S3_MAX_PAD_NR 45 - void eos_s3_lock_enable(void); void eos_s3_lock_disable(void); -int eos_s3_io_mux(uint32_t pad_nr, uint32_t pad_cfg); - #endif /* _SOC__H_ */ diff --git a/soc/arm/quicklogic_eos_s3/soc_pinmap.h b/soc/arm/quicklogic_eos_s3/soc_pinmap.h index 65715300c61177..1acee444364977 100644 --- a/soc/arm/quicklogic_eos_s3/soc_pinmap.h +++ b/soc/arm/quicklogic_eos_s3/soc_pinmap.h @@ -9,14 +9,4 @@ #include -/* Set UART TX to PAD44 */ -#define UART_TXD_PAD44 (UART_TXD_SEL_PAD44 | PAD_CTRL_SEL_AO_REG \ - | PAD_OEN_NORMAL | PAD_P_Z | PAD_SR_SLOW \ - | PAD_E_4MA | PAD_REN_DISABLE | PAD_SMT_DISABLE) - -/* Set UART RX to PAD45 */ -#define UART_RXD_PAD45 (UART_RXD_SEL_PAD45 | PAD_CTRL_SEL_AO_REG \ - | PAD_OEN_DISABLE | PAD_P_Z | PAD_SR_SLOW \ - | PAD_E_4MA | PAD_REN_ENABLE | PAD_SMT_DISABLE) - #endif /* _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_ */