diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index 1c72bfe707b0b2..c14e56b0347de4 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -5283,6 +5283,8 @@ Testing with Renode: - fkokosinski files: - cmake/emu/renode.cmake + - soc/renode/ + - boards/renode/ - boards/**/*/support/*.repl - boards/**/*/support/*.resc labels: diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig index 4095a277c61388..2ee3c945644d06 100644 --- a/arch/arm/core/cortex_a_r/Kconfig +++ b/arch/arm/core/cortex_a_r/Kconfig @@ -93,6 +93,14 @@ config CPU_CORTEX_R7 help This option signifies the use of a Cortex-R7 CPU +config CPU_CORTEX_R8 + bool + select CPU_AARCH32_CORTEX_R + select ARMV7_R + select ARMV7_R_FP if CPU_HAS_FPU + help + This option signifies the use of a Cortex-R8 CPU + config CPU_CORTEX_R52 bool select CPU_AARCH32_CORTEX_R diff --git a/boards/renode/cortex_r8_virtual/Kconfig.cortex_r8_virtual b/boards/renode/cortex_r8_virtual/Kconfig.cortex_r8_virtual new file mode 100644 index 00000000000000..e9830df9f05478 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/Kconfig.cortex_r8_virtual @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CORTEX_R8_VIRTUAL + select SOC_CORTEX_R8_VIRTUAL diff --git a/boards/renode/cortex_r8_virtual/board.cmake b/boards/renode/cortex_r8_virtual/board.cmake new file mode 100644 index 00000000000000..272149871d0903 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS renode) +set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/cortex_r8_virtual.resc) +set(RENODE_UART sysbus.uart0) diff --git a/boards/renode/cortex_r8_virtual/board.yml b/boards/renode/cortex_r8_virtual/board.yml new file mode 100644 index 00000000000000..799b2a9ba12d08 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/board.yml @@ -0,0 +1,5 @@ +board: + name: cortex_r8_virtual + vendor: renode + socs: + - name: cortex_r8_virtual diff --git a/boards/renode/cortex_r8_virtual/cortex_r8_virtual.dts b/boards/renode/cortex_r8_virtual/cortex_r8_virtual.dts new file mode 100644 index 00000000000000..9e8bd04f7df2b5 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/cortex_r8_virtual.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "Cortex-R8 Virtual target"; + compatible = "renode,cortex-r8-virtual"; + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + clock-frequency = <99999901>; +}; diff --git a/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml b/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml new file mode 100644 index 00000000000000..8d888e8806cf9c --- /dev/null +++ b/boards/renode/cortex_r8_virtual/cortex_r8_virtual.yaml @@ -0,0 +1,18 @@ +identifier: cortex_r8_virtual +name: Cortex R8 Virtual Board +type: mcu +arch: arm +toolchain: + - zephyr +ram: 131072 +simulation: renode +simulation_exec: renode +testing: + ignore_tags: + - net + - bluetooth + renode: + uart: sysbus.uart0 + resc: boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.resc +supported: + - uart diff --git a/boards/renode/cortex_r8_virtual/cortex_r8_virtual_defconfig b/boards/renode/cortex_r8_virtual/cortex_r8_virtual_defconfig new file mode 100644 index 00000000000000..1c358355b1e5a2 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/cortex_r8_virtual_defconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n + +CONFIG_ISR_STACK_SIZE=512 +CONFIG_THREAD_STACK_INFO=y + +CONFIG_MAX_DOMAIN_PARTITIONS=24 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_XLNX_PS=y + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_ARM_MPU=y diff --git a/boards/renode/cortex_r8_virtual/doc/index.rst b/boards/renode/cortex_r8_virtual/doc/index.rst new file mode 100644 index 00000000000000..07a18a7765074d --- /dev/null +++ b/boards/renode/cortex_r8_virtual/doc/index.rst @@ -0,0 +1,62 @@ +.. _cortex_r8_virtual: + +Cortex-R8 Virtual +################# + +Overview +******** + +The Cortex-R8 Virtual board is a virtual platform that can be emulated with Renode. +Edit the :zephyr_file:`boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.repl` file to adapt the platform layout to your needs. + +Refer to the `Renode documentation `_ +to learn how to obtain Renode for your host. + +Programming and debugging +************************* + +Building +======== + +Applications for the ``cortex_r8_virtual`` board target can be built +using the standard build flow (see :ref:`build_an_application`): + +.. zephyr-app-commands:: + :board: cortex_r8_virtual + :goals: build + +Flashing +======== + +Your software will run in simulation and you don't need to "flash" the board in a traditional way, +but you can use this configuration to run Zephyr applications +and kernel tests directly in Renode with the use of the ``run`` command. + +For example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: cortex_r8_virtual + :goals: run + +This will build an image with the synchronization sample app, boot it using +Renode, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v3.6.0-5689-g2a5c606abfa7 *** + thread_a: Hello World from cpu 0 on cortex_r8_virtual! + thread_b: Hello World from cpu 0 on cortex_r8_virtual! + thread_a: Hello World from cpu 0 on cortex_r8_virtual! + thread_b: Hello World from cpu 0 on cortex_r8_virtual! + +Exit Renode by pressing :kbd:`CTRL+C`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. + +Renode can serve as a GDB server. For more information, refer to the +`Renode documentation about GDB debugging `_. diff --git a/boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.repl b/boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.repl new file mode 100644 index 00000000000000..2c4c9d4cc6fab6 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.repl @@ -0,0 +1,31 @@ +cpu: CPU.ARMv7R @ sysbus + cpuType: "cortex-r8" + genericInterruptController: gic + numberOfMPURegions: 24 + cpuId: 0 + +scu: Miscellaneous.ArmSnoopControlUnit @ sysbus 0xae000000 + +gic: IRQControllers.ARM_GenericInterruptController @ { + sysbus new Bus.BusMultiRegistration { address: 0xf9001000; size: 0x100; region: "cpuInterface" }; + sysbus new Bus.BusMultiRegistration { address: 0xf9000000; size: 0x1000; region: "distributor" } + } + [0,1] -> cpu@[0,1] + architectureVersion: IRQControllers.ARM_GenericInterruptControllerVersion.GICv1 + supportsTwoSecurityStates: false + +privateTimer0: Timers.ARM_PrivateTimer @ { + sysbus new Bus.BusPointRegistration { address: 0xae000600; cpu: cpu } + } + -> gic#0@29 + frequency: 667000000 + +mem: Memory.MappedMemory @ sysbus 0x0 + size: 0x8000000 + +uart0: UART.Cadence_UART @ sysbus 0xff000000 + -> gic@21 + +ttc0: Timers.Cadence_TTC @ sysbus 0xff110000 + [0-2] -> gic@[36-38] + frequency: 5000000 diff --git a/boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.resc b/boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.resc new file mode 100644 index 00000000000000..6fbf739750a0e8 --- /dev/null +++ b/boards/renode/cortex_r8_virtual/support/cortex_r8_virtual.resc @@ -0,0 +1,18 @@ +:name: Cortex-R8-Virtual +:description: This script is prepared to run Zephyr on a virtual Cortex-R8 board. + +$name?="Cortex-R8-Virtual" + +using sysbus +mach create $name +machine LoadPlatformDescription $ORIGIN/cortex_r8_virtual.repl + + +showAnalyzer uart0 +cpu PerformanceInMips 5 + +macro reset +""" + sysbus LoadELF $elf +""" +runMacro $reset diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake index 8cb777c4769949..6f00283b6b8e4f 100644 --- a/cmake/gcc-m-cpu.cmake +++ b/cmake/gcc-m-cpu.cmake @@ -68,6 +68,15 @@ if("${ARCH}" STREQUAL "arm") else() set(GCC_M_CPU ${GCC_M_CPU}+nofp) endif() + elseif(CONFIG_CPU_CORTEX_R8) + set(GCC_M_CPU cortex-r8) + if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP) + if(NOT CONFIG_VFP_FEATURE_DOUBLE_PRECISION) + set(GCC_M_CPU ${GCC_M_CPU}+nofp.dp) + endif() + else() + set(GCC_M_CPU ${GCC_M_CPU}+nofp) + endif() elseif(CONFIG_CPU_CORTEX_R52) set(GCC_M_CPU cortex-r52) if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP) diff --git a/cmake/gcc-m-fpu.cmake b/cmake/gcc-m-fpu.cmake index a25cdf05679c8d..d1ce9655b46d01 100644 --- a/cmake/gcc-m-fpu.cmake +++ b/cmake/gcc-m-fpu.cmake @@ -7,7 +7,7 @@ if(CONFIG_FPU) if("${ARCH}" STREQUAL "arm") if(CONFIG_CPU_AARCH32_CORTEX_R) - if(CONFIG_CPU_CORTEX_R4 OR CONFIG_CPU_CORTEX_R5) # VFPv3 + if(CONFIG_CPU_CORTEX_R4 OR CONFIG_CPU_CORTEX_R5 OR CONFIG_CPU_CORTEX_R8) # VFPv3 if(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) set(GCC_M_FPU vfpv3-d16) elseif(CONFIG_VFP_FEATURE_SINGLE_PRECISION) diff --git a/dts/arm/cortex_r8_virt.dtsi b/dts/arm/cortex_r8_virt.dtsi new file mode 100644 index 00000000000000..704f17ed8efdcc --- /dev/null +++ b/dts/arm/cortex_r8_virt.dtsi @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-r8f"; + reg = <0>; + }; + }; + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = < &gic >; + flash0: flash@c0000000 { + compatible = "soc-nv-flash"; + reg = < 0xc0000000 0x2000000 >; + }; + sram0: memory@0 { + compatible = "mmio-sram"; + reg = < 0x0 0x4000000 >; + }; + uart0: uart@ff000000 { + compatible = "xlnx,xuartps"; + reg = < 0xff000000 0x4c >; + status = "disabled"; + interrupts = ; + interrupt-names = "irq_0"; + }; + ttc0: timer@ff110000 { + compatible = "xlnx,ttcps"; + status = "okay"; + interrupts = < 0x0 0x24 0x2 0xa0 >, + < 0x0 0x25 0x2 0xa0 >, + < 0x0 0x26 0x2 0xa0 >; + interrupt-names = "irq_0", "irq_1", "irq_2"; + reg = < 0xff110000 0x1000 >; + clock-frequency = < 5000000 >; + }; + gic: interrupt-controller@f9000000 { + compatible = "arm,gic-v1", "arm,gic"; + reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >; + interrupt-controller; + #interrupt-cells = < 0x4 >; + status = "okay"; + phandle = < 0x1 >; + }; + }; +}; diff --git a/include/zephyr/arch/arm/cortex_a_r/mpu.h b/include/zephyr/arch/arm/cortex_a_r/mpu.h index e660247e4aa123..896b73e20a29d8 100644 --- a/include/zephyr/arch/arm/cortex_a_r/mpu.h +++ b/include/zephyr/arch/arm/cortex_a_r/mpu.h @@ -32,7 +32,7 @@ #define MPU_RASR_B_Pos 0 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) -#if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5) +#if defined(CONFIG_CPU_CORTEX_R4) || defined(CONFIG_CPU_CORTEX_R5) || defined(CONFIG_CPU_CORTEX_R8) #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) diff --git a/modules/cmsis/cmsis_core_a_r.h b/modules/cmsis/cmsis_core_a_r.h index 9f4514edb474e8..bef0f60281352e 100644 --- a/modules/cmsis/cmsis_core_a_r.h +++ b/modules/cmsis/cmsis_core_a_r.h @@ -46,6 +46,8 @@ extern "C" { #include #elif defined(CONFIG_CPU_CORTEX_R7) #include +#elif defined(CONFIG_CPU_CORTEX_R8) +#include #elif defined(CONFIG_CPU_CORTEX_R52) #include #elif defined(CONFIG_CPU_AARCH32_CORTEX_A) diff --git a/samples/userspace/prod_consumer/boards/cortex_r8_virtual.conf b/samples/userspace/prod_consumer/boards/cortex_r8_virtual.conf new file mode 100644 index 00000000000000..83bf462b1c59d9 --- /dev/null +++ b/samples/userspace/prod_consumer/boards/cortex_r8_virtual.conf @@ -0,0 +1 @@ +CONFIG_DYNAMIC_OBJECTS=y diff --git a/soc/renode/cortex_r8_virtual/CMakeLists.txt b/soc/renode/cortex_r8_virtual/CMakeLists.txt new file mode 100644 index 00000000000000..2b8f495b04ee89 --- /dev/null +++ b/soc/renode/cortex_r8_virtual/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_sources_ifdef( + CONFIG_ARM_MPU + arm_mpu_regions.c +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renode/cortex_r8_virtual/Kconfig b/soc/renode/cortex_r8_virtual/Kconfig new file mode 100644 index 00000000000000..769ee5e4af80dc --- /dev/null +++ b/soc/renode/cortex_r8_virtual/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_CORTEX_R8_VIRTUAL + select ARM + select CPU_CORTEX_R8 + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_ARM_MPU + select VFP_DP_D16 diff --git a/soc/renode/cortex_r8_virtual/Kconfig.defconfig b/soc/renode/cortex_r8_virtual/Kconfig.defconfig new file mode 100644 index 00000000000000..114978755a9c83 --- /dev/null +++ b/soc/renode/cortex_r8_virtual/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CORTEX_R8_VIRTUAL + +config NUM_IRQS + default 220 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 5000000 + +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_CORTEX_R8_VIRTUAL diff --git a/soc/renode/cortex_r8_virtual/Kconfig.soc b/soc/renode/cortex_r8_virtual/Kconfig.soc new file mode 100644 index 00000000000000..c326279f27bf31 --- /dev/null +++ b/soc/renode/cortex_r8_virtual/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_CORTEX_R8_VIRTUAL + bool + help + Cortex R8 Virtual system implementation + +config SOC + default "cortex_r8_virtual" if SOC_CORTEX_R8_VIRTUAL diff --git a/soc/renode/cortex_r8_virtual/arm_mpu_regions.c b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c new file mode 100644 index 00000000000000..8287a0651d4d00 --- /dev/null +++ b/soc/renode/cortex_r8_virtual/arm_mpu_regions.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2021 Lexmark International, Inc. + * Copyright (c) 2024 Antmicro + */ + +#include +#include + +#define MPUTYPE_READ_ONLY \ + { \ + .rasr = (P_RO_U_RO_Msk \ + | (7 << MPU_RASR_TEX_Pos) \ + | MPU_RASR_C_Msk \ + | MPU_RASR_B_Msk \ + | MPU_RASR_XN_Msk) \ + } + +#define MPUTYPE_READ_ONLY_PRIV \ + { \ + .rasr = (P_RO_U_RO_Msk \ + | (5 << MPU_RASR_TEX_Pos) \ + | MPU_RASR_B_Msk) \ + } + +#define MPUTYPE_PRIV_WBWACACHE_XN \ + { \ + .rasr = (P_RW_U_NA_Msk \ + | (5 << MPU_RASR_TEX_Pos) \ + | MPU_RASR_B_Msk \ + | MPU_RASR_XN_Msk) \ + } + +#define MPUTYPE_PRIV_DEVICE \ + { \ + .rasr = (P_RW_U_NA_Msk \ + | (2 << MPU_RASR_TEX_Pos)) \ + } + +extern uint32_t _image_rom_end_order; +static const struct arm_mpu_region mpu_regions[] = { + MPU_REGION_ENTRY("FLASH0", + 0xc0000000, + REGION_32M, + MPUTYPE_READ_ONLY), + + MPU_REGION_ENTRY("SRAM_PRIV", + 0x00000000, + REGION_2G, + MPUTYPE_PRIV_WBWACACHE_XN), + + MPU_REGION_ENTRY("SRAM", + 0x00000000, + ((uint32_t)&_image_rom_end_order), + MPUTYPE_READ_ONLY_PRIV), + + MPU_REGION_ENTRY("REGISTERS", + 0xf8000000, + REGION_128M, + MPUTYPE_PRIV_DEVICE), +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/renode/cortex_r8_virtual/soc.c b/soc/renode/cortex_r8_virtual/soc.c new file mode 100644 index 00000000000000..b5ec39c810800b --- /dev/null +++ b/soc/renode/cortex_r8_virtual/soc.c @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2019 Lexmark International, Inc. + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include +#include + +#include + +void z_arm_platform_init(void) +{ + /* + * Use normal exception vectors address range (0x0-0x1C). + */ + unsigned int sctlr = __get_SCTLR(); + + sctlr &= ~SCTLR_V_Msk; + __set_SCTLR(sctlr); +} diff --git a/soc/renode/cortex_r8_virtual/soc.h b/soc/renode/cortex_r8_virtual/soc.h new file mode 100644 index 00000000000000..952a91d5e3faf4 --- /dev/null +++ b/soc/renode/cortex_r8_virtual/soc.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#ifndef ZEPHYR_SOC_CORTEX_R8_VIRTUAL_SOC_H_ +#define ZEPHYR_SOC_CORTEX_R8_VIRTUAL_SOC_H_ + +#define __CR_REV 1U + +#define __GIC_PRESENT 0U +#define __TIM_PRESENT 0U + +#endif /* ZEPHYR_SOC_CORTEX_R8_VIRTUAL_SOC_H_ */ diff --git a/soc/renode/cortex_r8_virtual/soc.yml b/soc/renode/cortex_r8_virtual/soc.yml new file mode 100644 index 00000000000000..8d0a0b279da595 --- /dev/null +++ b/soc/renode/cortex_r8_virtual/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: cortex_r8_virtual diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h index 83b2f5987354c0..71dfda7c193114 100644 --- a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h +++ b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h @@ -83,6 +83,16 @@ extern "C" { #else #define PROCESSOR_NAME "cortex-r7+nofp" #endif +#elif defined(CONFIG_CPU_CORTEX_R8) +#if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP) +#if !defined(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) +#define PROCESSOR_NAME "cortex-r8+nofp.dp" +#else +#define PROCESSOR_NAME "cortex-r8" +#endif +#else +#define PROCESSOR_NAME "cortex-r8+nofp" +#endif #elif defined(CONFIG_CPU_CORTEX_R52) #if defined(CONFIG_FPU) && defined(CONFIG_CPU_HAS_VFP) #if !defined(CONFIG_VFP_FEATURE_DOUBLE_PRECISION) diff --git a/tests/kernel/usage/thread_runtime_stats/testcase.yaml b/tests/kernel/usage/thread_runtime_stats/testcase.yaml index 671a01b8a190f3..b96eb0b381601f 100644 --- a/tests/kernel/usage/thread_runtime_stats/testcase.yaml +++ b/tests/kernel/usage/thread_runtime_stats/testcase.yaml @@ -18,3 +18,4 @@ tests: - mps2/an385 platform_exclude: - mr_canhubk3 + - cortex_r8_virtual diff --git a/tests/ztest/error_hook/src/main.c b/tests/ztest/error_hook/src/main.c index 7b1b63466c2af4..e4b05fc3eb0d19 100644 --- a/tests/ztest/error_hook/src/main.c +++ b/tests/ztest/error_hook/src/main.c @@ -121,6 +121,7 @@ __no_optimization static void trigger_fault_divide_zero(void) #if (defined(CONFIG_SOC_SERIES_MPS2) && defined(CONFIG_QEMU_TARGET)) || \ (defined(CONFIG_SOC_SERIES_MPS3) && defined(CONFIG_QEMU_TARGET)) || \ defined(CONFIG_BOARD_QEMU_CORTEX_A53) || defined(CONFIG_SOC_QEMU_ARC) || \ + defined(CONFIG_SOC_CORTEX_R8_VIRTUAL) || \ defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \ defined(CONFIG_BOARD_QEMU_CORTEX_R5) || \ defined(CONFIG_ARMV8_R) || defined(CONFIG_AARCH32_ARMV8_R) || \