diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi
index b85e3d03dc2d73..2fc651230f454d 100644
--- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi
+++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi
@@ -57,5 +57,5 @@
 	reg = <0x20040000 0x30000>;
 };
 
-/* Include shared RAM configuration file */
-#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi"
+/* Include default shared RAM configuration file */
+#include <common/nordic/nrf5340_shared_sram_partition.dtsi>
diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi
index ce2e145d58753c..1f5fc0bb3405a2 100644
--- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi
+++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi
@@ -63,5 +63,5 @@
 	};
 };
 
-/* Include shared RAM configuration file */
-#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi"
+/* Include default shared RAM configuration file */
+#include <common/nordic/nrf5340_shared_sram_partition.dtsi>
diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi
deleted file mode 100644
index fbb059494c36b9..00000000000000
--- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2019 Nordic Semiconductor ASA
- * Copyright (c) 2021 Laird Connectivity
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/* Default shared SRAM planning when building for BL5340 DVK.
- * This file is included by both nRF5340 CPUAPP (Application MCU)
- * and nRF5340 CPUNET (Network MCU).
- * - 64 kB SRAM allocated as Shared memory (sram0_shared)
- * - Region defined after the image SRAM of Application MCU
- */
-
-/ {
-	chosen {
-		/* shared memory reserved for the inter-processor communication */
-		zephyr,ipc_shm = &sram0_shared;
-	};
-
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		sram0_shared: memory@20070000 {
-			/* SRAM allocated to shared memory */
-			reg = <0x20070000 0x10000>;
-		};
-	};
-};
diff --git a/dts/arm/nordic/nrf5340_cpuapp_ipc.dtsi b/dts/arm/nordic/nrf5340_cpuapp_ipc.dtsi
index f5cda20e9613fe..3e2eb310542625 100644
--- a/dts/arm/nordic/nrf5340_cpuapp_ipc.dtsi
+++ b/dts/arm/nordic/nrf5340_cpuapp_ipc.dtsi
@@ -5,12 +5,14 @@
  */
 
 ipc0: ipc0 {
-	compatible = "zephyr,ipc-openamp-static-vrings";
-	memory-region = <&sram0_shared>;
+	compatible = "zephyr,ipc-icbmsg";
+	status = "okay";
 	mboxes = <&mbox 0>, <&mbox 1>;
 	mbox-names = "tx", "rx";
-	role = "host";
-	status = "okay";
+	tx-region = <&cpuapp_cpunet_ipc_shm>;
+	rx-region = <&cpunet_cpuapp_ipc_shm>;
+	tx-blocks = <32>;
+	rx-blocks = <32>;
 
 	bt_hci_ipc0: bt_hci_ipc0 {
 		compatible = "zephyr,bt-hci-ipc";
diff --git a/dts/arm/nordic/nrf5340_cpunet.dtsi b/dts/arm/nordic/nrf5340_cpunet.dtsi
index 77b77759b2205a..d69494ca3803d3 100644
--- a/dts/arm/nordic/nrf5340_cpunet.dtsi
+++ b/dts/arm/nordic/nrf5340_cpunet.dtsi
@@ -347,12 +347,14 @@
 	/* Default IPC description */
 	ipc {
 		ipc0: ipc0 {
-			compatible = "zephyr,ipc-openamp-static-vrings";
-			memory-region = <&sram0_shared>;
+			compatible = "zephyr,ipc-icbmsg";
+			status = "okay";
 			mboxes = <&mbox 0>, <&mbox 1>;
 			mbox-names = "rx", "tx";
-			role = "remote";
-			status = "okay";
+			tx-region = <&cpunet_cpuapp_ipc_shm>;
+			rx-region = <&cpuapp_cpunet_ipc_shm>;
+			tx-blocks = <32>;
+			rx-blocks = <32>;
 		};
 	};
 };
diff --git a/dts/common/nordic/nrf5340_shared_sram_partition.dtsi b/dts/common/nordic/nrf5340_shared_sram_partition.dtsi
index a5dc3489e893ea..8dc217ceae9eab 100644
--- a/dts/common/nordic/nrf5340_shared_sram_partition.dtsi
+++ b/dts/common/nordic/nrf5340_shared_sram_partition.dtsi
@@ -14,7 +14,9 @@
  * the memory range allocated to the non-secure image (sram0_ns).
  *
  * By default the last 64 kB of application core SRAM is allocated as shared
- * memory (sram0_shared).
+ * memory (sram0_shared) which is divided in:
+ * - 32 kB CPUAPP to CPUNET communication (cpuapp_cpunet_ipc_shm)
+ * - 32 kB CPUNET to CPUAPP communication (cpunet_cpuapp_ipc_shm)
  */
 
 / {
@@ -28,8 +30,18 @@
 		ranges;
 
 		sram0_shared: memory@20070000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
 			/* Last 64 kB of sram0 */
 			reg = <0x20070000 0x10000>;
+
+			cpuapp_cpunet_ipc_shm: memory@20070000 {
+				reg = <0x20070000 DT_SIZE_K(32)>;
+			};
+
+			cpunet_cpuapp_ipc_shm: memory@20078000 {
+				reg = <0x20078000 DT_SIZE_K(32)>;
+			};
 		};
 	};
 };