From c48f581ff7b5403a0b0845708acfd68432a41b2d Mon Sep 17 00:00:00 2001 From: Steven Herbst Date: Wed, 17 Apr 2024 14:53:00 -0400 Subject: [PATCH] simplify macro usage --- examples/axi/testbench.sv | 2 +- examples/axil/testbench.sv | 2 +- examples/minimal/testbench.sv | 24 +++--- examples/python/testbench.sv | 24 +++--- examples/router/testbench.sv | 10 ++- examples/stream/testbench.sv | 10 ++- examples/umi_endpoint/testbench.sv | 4 +- examples/umi_fifo/testbench.sv | 4 +- examples/umi_fifo_flex/testbench.sv | 4 +- examples/umi_gpio/testbench.sv | 4 +- examples/umi_splitter/testbench.sv | 6 +- examples/umiram/testbench.sv | 4 +- switchboard/verilog/common/switchboard.vh | 86 +++++++++++++-------- switchboard/verilog/sim/queue_to_sb_sim.sv | 2 + switchboard/verilog/sim/sb_axi_m.sv | 6 +- switchboard/verilog/sim/sb_axil_m.sv | 6 +- switchboard/verilog/sim/sb_to_queue_sim.sv | 2 + switchboard/verilog/sim/umi_to_queue_sim.sv | 11 +-- 18 files changed, 122 insertions(+), 89 deletions(-) diff --git a/examples/axi/testbench.sv b/examples/axi/testbench.sv index faaf7901..63b363eb 100644 --- a/examples/axi/testbench.sv +++ b/examples/axi/testbench.sv @@ -38,7 +38,7 @@ module testbench ( // Instantiate switchboard module - `SB_AXI_M(sb_axi_m_i, axi, clk, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH, "axi"); + `SB_AXI_M(axi, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH); // Initialize RAM to zeros for easy comparison against a behavioral model diff --git a/examples/axil/testbench.sv b/examples/axil/testbench.sv index 0dfbcfaa..98123ab4 100644 --- a/examples/axil/testbench.sv +++ b/examples/axil/testbench.sv @@ -36,7 +36,7 @@ module testbench ( // Instantiate switchboard module - `SB_AXIL_M(sb_axil_m_i, axil, clk, DATA_WIDTH, ADDR_WIDTH, "axil"); + `SB_AXIL_M(axil, DATA_WIDTH, ADDR_WIDTH); // Initialize RAM to zeros for easy comparison against a behavioral model diff --git a/examples/minimal/testbench.sv b/examples/minimal/testbench.sv index 4cde0b99..6dbee578 100644 --- a/examples/minimal/testbench.sv +++ b/examples/minimal/testbench.sv @@ -12,29 +12,31 @@ module testbench ( `SB_CREATE_CLOCK(clk) `endif + localparam integer DW=256; + // SB RX port - `SB_WIRES(sb_rx, 256); - `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "to_rtl.q"); + `SB_WIRES(to_rtl, DW); + `QUEUE_TO_SB_SIM(to_rtl, DW); // SB TX port - `SB_WIRES(sb_tx, 256); - `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "from_rtl.q"); + `SB_WIRES(from_rtl, DW); + `SB_TO_QUEUE_SIM(from_rtl, DW); // custom modification of packet genvar i; generate - for (i=0; i<32; i=i+1) begin - assign sb_tx_data[(i*8) +: 8] = sb_rx_data[(i*8) +: 8] + 8'd1; + for (i=0; i<(DW/8); i=i+1) begin + assign from_rtl_data[(i*8) +: 8] = to_rtl_data[(i*8) +: 8] + 8'd1; end endgenerate - assign sb_tx_dest = sb_rx_dest; - assign sb_tx_last = sb_rx_last; - assign sb_tx_valid = sb_rx_valid; - assign sb_rx_ready = sb_tx_ready; + assign from_rtl_dest = to_rtl_dest; + assign from_rtl_last = to_rtl_last; + assign from_rtl_valid = to_rtl_valid; + assign to_rtl_ready = from_rtl_ready; // Waveforms @@ -43,7 +45,7 @@ module testbench ( // $finish always @(posedge clk) begin - if (sb_rx_valid && ((&sb_rx_data) == 1'b1)) begin + if (to_rtl_valid && ((&to_rtl_data) == 1'b1)) begin $finish; end end diff --git a/examples/python/testbench.sv b/examples/python/testbench.sv index 4cde0b99..5fcbe7d3 100644 --- a/examples/python/testbench.sv +++ b/examples/python/testbench.sv @@ -12,29 +12,31 @@ module testbench ( `SB_CREATE_CLOCK(clk) `endif + localparam DW=256; + // SB RX port - `SB_WIRES(sb_rx, 256); - `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "to_rtl.q"); + `SB_WIRES(to_rtl, DW); + `QUEUE_TO_SB_SIM(to_rtl, DW); // SB TX port - `SB_WIRES(sb_tx, 256); - `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "from_rtl.q"); + `SB_WIRES(from_rtl, DW); + `SB_TO_QUEUE_SIM(from_rtl, DW); // custom modification of packet genvar i; generate - for (i=0; i<32; i=i+1) begin - assign sb_tx_data[(i*8) +: 8] = sb_rx_data[(i*8) +: 8] + 8'd1; + for (i=0; i<(DW/8); i=i+1) begin + assign from_rtl_data[(i*8) +: 8] = to_rtl_data[(i*8) +: 8] + 8'd1; end endgenerate - assign sb_tx_dest = sb_rx_dest; - assign sb_tx_last = sb_rx_last; - assign sb_tx_valid = sb_rx_valid; - assign sb_rx_ready = sb_tx_ready; + assign from_rtl_dest = to_rtl_dest; + assign from_rtl_last = to_rtl_last; + assign from_rtl_valid = to_rtl_valid; + assign to_rtl_ready = from_rtl_ready; // Waveforms @@ -43,7 +45,7 @@ module testbench ( // $finish always @(posedge clk) begin - if (sb_rx_valid && ((&sb_rx_data) == 1'b1)) begin + if (to_rtl_valid && ((&to_rtl_data) == 1'b1)) begin $finish; end end diff --git a/examples/router/testbench.sv b/examples/router/testbench.sv index 85f7b4b9..4f70c0ac 100644 --- a/examples/router/testbench.sv +++ b/examples/router/testbench.sv @@ -12,15 +12,17 @@ module testbench ( `SB_CREATE_CLOCK(clk) `endif + localparam integer DW=256; + // SB RX port - `SB_WIRES(sb_rx, 256); - `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "queue-5557"); + `SB_WIRES(sb_rx, DW); + `QUEUE_TO_SB_SIM(sb_rx, DW, "queue-5557"); // SB TX port - `SB_WIRES(sb_tx, 256); - `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "queue-5558"); + `SB_WIRES(sb_tx, DW); + `SB_TO_QUEUE_SIM(sb_tx, DW, "queue-5558"); // custom modification of packet diff --git a/examples/stream/testbench.sv b/examples/stream/testbench.sv index 66f93dbc..e234252a 100644 --- a/examples/stream/testbench.sv +++ b/examples/stream/testbench.sv @@ -12,15 +12,17 @@ module testbench ( `SB_CREATE_CLOCK(clk) `endif + localparam integer DW=256; + // SB RX port - `SB_WIRES(sb_rx, 256); - `QUEUE_TO_SB_SIM(rx_i, sb_rx, clk, 256, "client2rtl.q"); + `SB_WIRES(sb_rx, DW); + `QUEUE_TO_SB_SIM(sb_rx, DW, "client2rtl.q"); // SB TX port - `SB_WIRES(sb_tx, 256); - `SB_TO_QUEUE_SIM(tx_i, sb_tx, clk, 256, "rtl2client.q"); + `SB_WIRES(sb_tx, DW); + `SB_TO_QUEUE_SIM(sb_tx, DW, "rtl2client.q"); // custom modification of packet diff --git a/examples/umi_endpoint/testbench.sv b/examples/umi_endpoint/testbench.sv index 5692b624..35c82814 100644 --- a/examples/umi_endpoint/testbench.sv +++ b/examples/umi_endpoint/testbench.sv @@ -19,10 +19,10 @@ module testbench ( parameter integer AW=64; `SB_UMI_WIRES(udev_req, DW, CW, AW); - `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q"); + `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q"); `SB_UMI_WIRES(udev_resp, DW, CW, AW); - `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q"); + `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q"); reg nreset = 1'b0; wire [AW-1:0] loc_addr; diff --git a/examples/umi_fifo/testbench.sv b/examples/umi_fifo/testbench.sv index 0706c0c0..683ceeb0 100644 --- a/examples/umi_fifo/testbench.sv +++ b/examples/umi_fifo/testbench.sv @@ -19,10 +19,10 @@ module testbench ( localparam integer CW=32; `SB_UMI_WIRES(udev_req, DW, CW, AW); - `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q"); + `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q"); `SB_UMI_WIRES(udev_resp, DW, CW, AW); - `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q"); + `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q"); reg nreset = 1'b0; diff --git a/examples/umi_fifo_flex/testbench.sv b/examples/umi_fifo_flex/testbench.sv index 8fca9285..ebfe9bd8 100644 --- a/examples/umi_fifo_flex/testbench.sv +++ b/examples/umi_fifo_flex/testbench.sv @@ -20,10 +20,10 @@ module testbench ( parameter integer CW=32; `SB_UMI_WIRES(udev_req, IDW, CW, AW); - `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, IDW, CW, AW, "to_rtl.q"); + `QUEUE_TO_UMI_SIM(udev_req, IDW, CW, AW, "to_rtl.q"); `SB_UMI_WIRES(udev_resp, ODW, CW, AW); - `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, ODW, CW, AW, "from_rtl.q"); + `UMI_TO_QUEUE_SIM(udev_resp, ODW, CW, AW, "from_rtl.q"); reg nreset = 1'b0; diff --git a/examples/umi_gpio/testbench.sv b/examples/umi_gpio/testbench.sv index e298d5b2..0e8846f8 100644 --- a/examples/umi_gpio/testbench.sv +++ b/examples/umi_gpio/testbench.sv @@ -21,10 +21,10 @@ module testbench ( localparam integer OWIDTH=128; `SB_UMI_WIRES(udev_req, DW, CW, AW); - `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q"); + `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q"); `SB_UMI_WIRES(udev_resp, DW, CW, AW); - `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q"); + `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q"); reg nreset = 1'b0; wire [(IWIDTH-1):0] gpio_in; diff --git a/examples/umi_splitter/testbench.sv b/examples/umi_splitter/testbench.sv index 1faa88f1..db2f6e74 100644 --- a/examples/umi_splitter/testbench.sv +++ b/examples/umi_splitter/testbench.sv @@ -21,17 +21,17 @@ module testbench ( // UMI input `SB_UMI_WIRES(umi_in, DW, CW, AW); - `QUEUE_TO_UMI_SIM(rx, umi_in, clk, DW, CW, AW, "in.q"); + `QUEUE_TO_UMI_SIM(umi_in, DW, CW, AW, "in.q"); // UMI output (response) `SB_UMI_WIRES(umi_resp_out, DW, CW, AW); - `UMI_TO_QUEUE_SIM(tx0, umi_resp_out, clk, DW, CW, AW, "out0.q"); + `UMI_TO_QUEUE_SIM(umi_resp_out, DW, CW, AW, "out0.q"); // UMI output (request) `SB_UMI_WIRES(umi_req_out, DW, CW, AW); - `UMI_TO_QUEUE_SIM(tx1, umi_req_out, clk, DW, CW, AW, "out1.q"); + `UMI_TO_QUEUE_SIM(umi_req_out, DW, CW, AW, "out1.q"); // UMI splitter diff --git a/examples/umiram/testbench.sv b/examples/umiram/testbench.sv index 5c98915c..70b108dd 100644 --- a/examples/umiram/testbench.sv +++ b/examples/umiram/testbench.sv @@ -19,10 +19,10 @@ module testbench ( localparam integer CW=32; `SB_UMI_WIRES(udev_req, DW, CW, AW); - `QUEUE_TO_UMI_SIM(rx_i, udev_req, clk, DW, CW, AW, "to_rtl.q"); + `QUEUE_TO_UMI_SIM(udev_req, DW, CW, AW, "to_rtl.q"); `SB_UMI_WIRES(udev_resp, DW, CW, AW); - `UMI_TO_QUEUE_SIM(tx_i, udev_resp, clk, DW, CW, AW, "from_rtl.q"); + `UMI_TO_QUEUE_SIM(udev_resp, DW, CW, AW, "from_rtl.q"); // instantiate module with UMI ports diff --git a/switchboard/verilog/common/switchboard.vh b/switchboard/verilog/common/switchboard.vh index 2a7f5fe9..f767a7ac 100644 --- a/switchboard/verilog/common/switchboard.vh +++ b/switchboard/verilog/common/switchboard.vh @@ -6,6 +6,9 @@ `ifndef SWITCHBOARD_VH_ `define SWITCHBOARD_VH_ +// ref: https://stackoverflow.com/a/15376637 +`define STRINGIFY(x) `"x`" + `define SB_UMI_WIRES(signal, dw, cw, aw) \ wire signal``_valid; \ wire [((cw)-1): 0] signal``_cmd; \ @@ -18,13 +21,18 @@ `define UMI_PORT_WIRES_WIDTHS(prefix, dw, cw, aw) \ `SB_UMI_WIRES(prefix, dw, cw, aw) -`define QUEUE_TO_UMI_SIM(mod, signal, clk_signal, dw, cw, aw, file="") \ +`define QUEUE_TO_UMI_SIM(signal, dw, cw, aw, file=-1, vldmode=1, clk_signal=clk) \ queue_to_umi_sim #( \ + .VALID_MODE_DEFAULT(vldmode), \ .DW(dw), \ .CW(cw), \ .AW(aw), \ - .FILE(file) \ - ) mod ( \ + .FILE( \ + /* verilator lint_off WIDTHEXPAND */ \ + (file == -1) ? {`STRINGIFY(signal), ".q"} : file \ + /* verilator lint_on WIDTHEXPAND */ \ + ) \ + ) signal``_sb_inst ( \ .clk(clk_signal), \ .data(signal``_data), \ .srcaddr(signal``_srcaddr), \ @@ -34,13 +42,18 @@ .valid(signal``_valid) \ ) -`define UMI_TO_QUEUE_SIM(mod, signal, clk_signal, dw, cw, aw, file="") \ +`define UMI_TO_QUEUE_SIM(signal, dw, cw, aw, file=-1, rdymode=1, clk_signal=clk) \ umi_to_queue_sim #( \ + .READY_MODE_DEFAULT(rdymode), \ .DW(dw), \ .CW(cw), \ .AW(aw), \ - .FILE(file) \ - ) mod ( \ + .FILE( \ + /* verilator lint_off WIDTHEXPAND */ \ + (file == -1) ? {`STRINGIFY(signal), ".q"} : file \ + /* verilator lint_on WIDTHEXPAND */ \ + ) \ + ) signal``_sb_inst ( \ .clk(clk_signal), \ .data(signal``_data), \ .srcaddr(signal``_srcaddr), \ @@ -61,19 +74,8 @@ `define SWITCHBOARD_SIM_PORT(prefix, dw) \ `SB_UMI_WIRES(prefix``_req, dw, 32, 64); \ `SB_UMI_WIRES(prefix``_resp, dw, 32, 64); \ - \ - initial begin \ - /* verilator lint_off IGNOREDRETURN */ \ - prefix``_rx.init($sformatf("%s_req.q", `"prefix`")); \ - prefix``_tx.init($sformatf("%s_resp.q", `"prefix`")); \ - /* verilator lint_on IGNOREDRETURN */ \ - end \ - \ - `QUEUE_TO_UMI_SIM( \ - prefix``_rx, prefix``_req, clk, dw, 32, 64); \ - \ - `UMI_TO_QUEUE_SIM( \ - prefix``_tx, prefix``_resp, clk, dw, 32, 64) + `QUEUE_TO_UMI_SIM(prefix``_req, dw, 32, 64); \ + `UMI_TO_QUEUE_SIM(prefix``_resp, dw, 32, 64) `define SB_WIRES(signal, dw) \ wire [((dw)-1):0] signal``_data; \ @@ -82,11 +84,16 @@ wire signal``_valid; \ wire signal``_ready -`define SB_TO_QUEUE_SIM(mod, signal, clk_signal, dw, file="") \ +`define SB_TO_QUEUE_SIM(signal, dw, file=-1, rdymode=1, clk_signal=clk) \ sb_to_queue_sim #( \ + .READY_MODE_DEFAULT(rdymode), \ .DW(dw), \ - .FILE(file) \ - ) mod ( \ + .FILE( \ + /* verilator lint_off WIDTHEXPAND */ \ + (file == -1) ? {`STRINGIFY(signal), ".q"} : file \ + /* verilator lint_on WIDTHEXPAND */ \ + ) \ + ) signal``_sb_inst ( \ .clk(clk_signal), \ .data(signal``_data), \ .dest(signal``_dest), \ @@ -95,11 +102,16 @@ .valid(signal``_valid) \ ) -`define QUEUE_TO_SB_SIM(mod, signal, clk_signal, dw, file="") \ +`define QUEUE_TO_SB_SIM(signal, dw, file=-1, vldmode=1, clk_signal=clk) \ queue_to_sb_sim #( \ + .VALID_MODE_DEFAULT(vldmode), \ .DW(dw), \ - .FILE(file) \ - ) mod ( \ + .FILE( \ + /* verilator lint_off WIDTHEXPAND */ \ + (file == -1) ? {`STRINGIFY(signal), ".q"} : file \ + /* verilator lint_on WIDTHEXPAND */ \ + ) \ + ) signal``_sb_inst ( \ .clk(clk_signal), \ .data(signal``_data), \ .dest(signal``_dest), \ @@ -150,12 +162,18 @@ .a``_rvalid(b``_rvalid), \ .a``_rready(b``_rready) -`define SB_AXIL_M(mod, signal, clk_signal, dw, aw, file="") \ +`define SB_AXIL_M(signal, dw, aw, file=-1, vldmode=1, rdymode=1, clk_signal=clk) \ sb_axil_m #( \ .DATA_WIDTH(dw), \ .ADDR_WIDTH(aw), \ - .FILE(file) \ - ) mod ( \ + .VALID_MODE_DEFAULT(vldmode), \ + .READY_MODE_DEFAULT(rdymode), \ + .FILE( \ + /* verilator lint_off WIDTHEXPAND */ \ + (file == -1) ? `STRINGIFY(signal) : file \ + /* verilator lint_on WIDTHEXPAND */ \ + ) \ + ) signal``_sb_inst ( \ .clk(clk_signal), \ .m_axil_awaddr(signal``_awaddr), \ .m_axil_awprot(signal``_awprot), \ @@ -252,13 +270,19 @@ .a``_rvalid(b``_rvalid), \ .a``_rready(b``_rready) -`define SB_AXI_M(mod, signal, clk_signal, dw, aw, idw, file="") \ +`define SB_AXI_M(signal, dw, aw, idw, file=-1, vldmode=1, rdymode=1, clk_signal=clk) \ sb_axi_m #( \ .DATA_WIDTH(dw), \ .ADDR_WIDTH(aw), \ .ID_WIDTH(idw), \ - .FILE(file) \ - ) mod ( \ + .VALID_MODE_DEFAULT(vldmode), \ + .READY_MODE_DEFAULT(rdymode), \ + .FILE( \ + /* verilator lint_off WIDTHEXPAND */ \ + (file == -1) ? `STRINGIFY(signal) : file \ + /* verilator lint_on WIDTHEXPAND */ \ + ) \ + ) signal``_sb_inst ( \ .clk(clk_signal), \ .m_axi_awid(signal``_awid), \ .m_axi_awaddr(signal``_awaddr), \ diff --git a/switchboard/verilog/sim/queue_to_sb_sim.sv b/switchboard/verilog/sim/queue_to_sb_sim.sv index c85fb0e8..a92f4603 100644 --- a/switchboard/verilog/sim/queue_to_sb_sim.sv +++ b/switchboard/verilog/sim/queue_to_sb_sim.sv @@ -152,7 +152,9 @@ module queue_to_sb_sim #( initial begin if (FILE != "") begin + /* verilator lint_off IGNOREDRETURN */ init(FILE); + /* verilator lint_on IGNOREDRETURN */ end end diff --git a/switchboard/verilog/sim/sb_axi_m.sv b/switchboard/verilog/sim/sb_axi_m.sv index 3f5d2ebf..8b23d8f2 100644 --- a/switchboard/verilog/sim/sb_axi_m.sv +++ b/switchboard/verilog/sim/sb_axi_m.sv @@ -11,8 +11,8 @@ module sb_axi_m #( parameter ID_WIDTH = 8, // Switchboard settings - parameter integer VALID_MODE_DEFAULT=0, - parameter integer READY_MODE_DEFAULT=0, + parameter integer VALID_MODE_DEFAULT=1, + parameter integer READY_MODE_DEFAULT=1, parameter FILE="" ) ( input wire clk, @@ -177,7 +177,9 @@ module sb_axi_m #( initial begin if (FILE != "") begin + /* verilator lint_off IGNOREDRETURN */ init(FILE); + /* verilator lint_on IGNOREDRETURN */ end end diff --git a/switchboard/verilog/sim/sb_axil_m.sv b/switchboard/verilog/sim/sb_axil_m.sv index 71ade913..d5ac2ab4 100644 --- a/switchboard/verilog/sim/sb_axil_m.sv +++ b/switchboard/verilog/sim/sb_axil_m.sv @@ -10,8 +10,8 @@ module sb_axil_m #( parameter STRB_WIDTH = (DATA_WIDTH/8), // Switchboard settings - parameter integer VALID_MODE_DEFAULT=0, - parameter integer READY_MODE_DEFAULT=0, + parameter integer VALID_MODE_DEFAULT=1, + parameter integer READY_MODE_DEFAULT=1, parameter FILE="" ) ( input wire clk, @@ -158,7 +158,9 @@ module sb_axil_m #( initial begin if (FILE != "") begin + /* verilator lint_off IGNOREDRETURN */ init(FILE); + /* verilator lint_on IGNOREDRETURN */ end end diff --git a/switchboard/verilog/sim/sb_to_queue_sim.sv b/switchboard/verilog/sim/sb_to_queue_sim.sv index b869d385..57fac59a 100644 --- a/switchboard/verilog/sim/sb_to_queue_sim.sv +++ b/switchboard/verilog/sim/sb_to_queue_sim.sv @@ -172,7 +172,9 @@ module sb_to_queue_sim #( initial begin if (FILE != "") begin + /* verilator lint_off IGNOREDRETURN */ init(FILE); + /* verilator lint_on IGNOREDRETURN */ end end diff --git a/switchboard/verilog/sim/umi_to_queue_sim.sv b/switchboard/verilog/sim/umi_to_queue_sim.sv index 2802298c..ab873801 100644 --- a/switchboard/verilog/sim/umi_to_queue_sim.sv +++ b/switchboard/verilog/sim/umi_to_queue_sim.sv @@ -23,7 +23,8 @@ module umi_to_queue_sim #( sb_to_queue_sim #( .READY_MODE_DEFAULT(READY_MODE_DEFAULT), - .DW(DW+AW+AW+CW) + .DW(DW+AW+AW+CW), + .FILE(FILE) ) tx_i ( .clk(clk), .data({data, srcaddr, dstaddr, cmd}), @@ -55,14 +56,6 @@ module umi_to_queue_sim #( /* verilator lint_on IGNOREDRETURN */ `SB_END_FUNC - // initialize - - initial begin - if (FILE != "") begin - init(FILE); - end - end - // clean up macros `undef SB_START_FUNC