diff --git a/examples/args/testbench.sv b/examples/args/testbench.sv index 39a2ecc7..55535543 100644 --- a/examples/args/testbench.sv +++ b/examples/args/testbench.sv @@ -1,23 +1,15 @@ // Copyright (c) 2024 Zero ASIC Corporation // This code is licensed under Apache License 2.0 (see LICENSE for details) +`include "switchboard.vh" + module testbench ( `ifdef VERILATOR input clk `endif ); - // clock - `ifndef VERILATOR - - reg clk; - always begin - clk = 1'b0; - #5; - clk = 1'b1; - #5; - end - + `SB_CREATE_CLOCK(clk) `endif integer a=0, b=0; diff --git a/examples/axi/testbench.sv b/examples/axi/testbench.sv index 607f3ecd..5addb23a 100644 --- a/examples/axi/testbench.sv +++ b/examples/axi/testbench.sv @@ -66,7 +66,7 @@ module testbench ( // Set up waveform probing - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/axil/testbench.sv b/examples/axil/testbench.sv index 63ba4b1a..ec4465e6 100644 --- a/examples/axil/testbench.sv +++ b/examples/axil/testbench.sv @@ -64,7 +64,7 @@ module testbench ( // Set up waveform probing - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/minimal/testbench.sv b/examples/minimal/testbench.sv index 48660edd..8cbbf2ae 100644 --- a/examples/minimal/testbench.sv +++ b/examples/minimal/testbench.sv @@ -45,7 +45,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES // $finish diff --git a/examples/python/testbench.sv b/examples/python/testbench.sv index 48660edd..8cbbf2ae 100644 --- a/examples/python/testbench.sv +++ b/examples/python/testbench.sv @@ -45,7 +45,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES // $finish diff --git a/examples/router/testbench.sv b/examples/router/testbench.sv index 39134ead..ae55e94a 100644 --- a/examples/router/testbench.sv +++ b/examples/router/testbench.sv @@ -44,6 +44,6 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/stream/testbench.sv b/examples/stream/testbench.sv index 0901466c..da824755 100644 --- a/examples/stream/testbench.sv +++ b/examples/stream/testbench.sv @@ -43,7 +43,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES // $finish diff --git a/examples/umi_endpoint/testbench.sv b/examples/umi_endpoint/testbench.sv index 4b5f7af9..a6406aef 100644 --- a/examples/umi_endpoint/testbench.sv +++ b/examples/umi_endpoint/testbench.sv @@ -72,7 +72,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/umi_fifo/testbench.sv b/examples/umi_fifo/testbench.sv index 7cfd4c46..69584d8a 100644 --- a/examples/umi_fifo/testbench.sv +++ b/examples/umi_fifo/testbench.sv @@ -60,7 +60,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/umi_fifo_flex/testbench.sv b/examples/umi_fifo_flex/testbench.sv index 48064093..ba64b76a 100644 --- a/examples/umi_fifo_flex/testbench.sv +++ b/examples/umi_fifo_flex/testbench.sv @@ -61,7 +61,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/umi_gpio/testbench.sv b/examples/umi_gpio/testbench.sv index f9a918da..6b4102f1 100644 --- a/examples/umi_gpio/testbench.sv +++ b/examples/umi_gpio/testbench.sv @@ -61,7 +61,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/umi_splitter/testbench.sv b/examples/umi_splitter/testbench.sv index f5b015ba..233051cb 100644 --- a/examples/umi_splitter/testbench.sv +++ b/examples/umi_splitter/testbench.sv @@ -49,7 +49,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/umiram/testbench.sv b/examples/umiram/testbench.sv index b1c06a24..929dcd40 100644 --- a/examples/umiram/testbench.sv +++ b/examples/umiram/testbench.sv @@ -39,7 +39,7 @@ module testbench ( // Waveforms - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/examples/xyce/testbench.sv b/examples/xyce/testbench.sv index e4a30ef4..102683d4 100644 --- a/examples/xyce/testbench.sv +++ b/examples/xyce/testbench.sv @@ -1,6 +1,8 @@ // Copyright (c) 2024 Zero ASIC Corporation // This code is licensed under Apache License 2.0 (see LICENSE for details) +`include "switchboard.vh" + module testbench ( `ifdef VERILATOR input clk @@ -48,6 +50,6 @@ module testbench ( // Waveform probing - `SB_PROBE + `SB_SETUP_PROBES endmodule diff --git a/switchboard/sbdut.py b/switchboard/sbdut.py index 8d8e965c..ff4113e4 100644 --- a/switchboard/sbdut.py +++ b/switchboard/sbdut.py @@ -203,6 +203,7 @@ def __init__( if trace: self.set('option', 'trace', True) + self.set('option', 'define', 'SB_TRACE') if self.trace_type == 'fst': self.set('option', 'define', 'SB_TRACE_FST') diff --git a/switchboard/verilog/common/switchboard.vh b/switchboard/verilog/common/switchboard.vh index 381893f3..ed56f37f 100644 --- a/switchboard/verilog/common/switchboard.vh +++ b/switchboard/verilog/common/switchboard.vh @@ -318,14 +318,16 @@ `SB_DELAY(0.5 * period); \ end -`define SB_PROBE \ - initial begin \ - if ($test$plusargs("trace")) begin \ - `ifdef SB_TRACE_FST \ - $dumpfile("testbench.fst"); \ - `else \ - $dumpfile("testbench.vcd"); \ - `endif \ - $dumpvars(0, testbench); \ +`define SB_SETUP_PROBES \ + `ifdef SB_TRACE \ + initial begin \ + if ($test$plusargs("trace")) begin \ + `ifdef SB_TRACE_FST \ + $dumpfile("testbench.fst"); \ + `else \ + $dumpfile("testbench.vcd"); \ + `endif \ + $dumpvars(0, testbench); \ + end \ end \ - end + `endif