diff --git a/examples/axi/test.py b/examples/axi/test.py
index d1068b09..60d427eb 100755
--- a/examples/axi/test.py
+++ b/examples/axi/test.py
@@ -100,7 +100,7 @@ def build_testbench():
     dut = SbDut('axi_ram', autowrap=True, cmdline=True, extra_args=extra_args,
         parameters=parameters, interfaces=interfaces, resets=resets)
 
-    dut.register_package_source(
+    dut.register_source(
         'verilog-axi',
         'git+https://github.com/alexforencich/verilog-axi.git',
         '38915fb'
diff --git a/examples/axil/test.py b/examples/axil/test.py
index 0ba973b4..2210c45d 100755
--- a/examples/axil/test.py
+++ b/examples/axil/test.py
@@ -93,7 +93,7 @@ def build_testbench():
     dut = SbDut('axil_ram', autowrap=True, cmdline=True, extra_args=extra_args,
         parameters=parameters, interfaces=interfaces, resets=resets)
 
-    dut.register_package_source(
+    dut.register_source(
         'verilog-axi',
         'git+https://github.com/alexforencich/verilog-axi.git',
         '38915fb'
diff --git a/examples/fpga_loopback/test.py b/examples/fpga_loopback/test.py
index aaf70a6d..772a38b3 100755
--- a/examples/fpga_loopback/test.py
+++ b/examples/fpga_loopback/test.py
@@ -63,7 +63,7 @@ def build_testbench(fast=False):
     dut.set('tool', tool, 'task', 'compile', 'var', 'pins_bv', '2')
 
     # libsystemctlm-soc configuration
-    dut.register_package_source(
+    dut.register_source(
         'libsystemctlm-soc',
         'git+https://github.com/Xilinx/libsystemctlm-soc.git',
         '670d73c'
diff --git a/examples/network/test.py b/examples/network/test.py
index 203c0949..a951b380 100755
--- a/examples/network/test.py
+++ b/examples/network/test.py
@@ -134,7 +134,7 @@ def make_axil_ram(net):
     dut = net.make_dut('axil_ram', parameters=parameters,
         interfaces=interfaces, resets=resets)
 
-    dut.register_package_source(
+    dut.register_source(
         'verilog-axi',
         'git+https://github.com/alexforencich/verilog-axi.git',
         '38915fb'
diff --git a/requirements.txt b/requirements.txt
index 59f5175c..bddb2a1f 100644
--- a/requirements.txt
+++ b/requirements.txt
@@ -10,7 +10,7 @@
 
 numpy
 tqdm
-siliconcompiler <0.24.0
+siliconcompiler >= 0.24.0
 
 # Testing dependencies
 #:test
diff --git a/switchboard/sbdut.py b/switchboard/sbdut.py
index 972b3319..155f2361 100644
--- a/switchboard/sbdut.py
+++ b/switchboard/sbdut.py
@@ -235,6 +235,8 @@ def __init__(
 
         self.set('option', 'builddir', str(Path(builddir).resolve()))
 
+        self.set('option', 'clean', True)  # preserve old behavior
+
         self.set('option', 'mode', 'sim')
 
         if not subcomponent:
@@ -252,7 +254,7 @@ def __init__(
                 self.add('option', opt, sb_path() / 'verilog' / 'common')
 
             if trace:
-                self.set('option', 'trace', True)
+                self.set('tool', 'verilator', 'task', 'compile', 'var', 'trace', True)
                 self.add('option', 'define', 'SB_TRACE')
 
             if self.trace_type == 'fst':
diff --git a/switchboard/sc/morty/uniquify.py b/switchboard/sc/morty/uniquify.py
index 6512127b..08b2dbbb 100644
--- a/switchboard/sc/morty/uniquify.py
+++ b/switchboard/sc/morty/uniquify.py
@@ -2,6 +2,7 @@
 # This code is licensed under Apache License 2.0 (see LICENSE for details)
 
 from .morty import setup as setup_tool
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -13,7 +14,7 @@ def setup(chip):
     tool = 'morty'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    task = chip._get_task(step, index)
+    _, task = get_tool_task(chip, step, index)
 
     chip.set('tool', tool, 'task', task, 'var', 'suffix',
              'suffix to be added to the end of module names',
@@ -28,7 +29,7 @@ def runtime_options(chip):
     tool = 'morty'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    task = chip._get_task(step, index)
+    _, task = get_tool_task(chip, step, index)
     design = chip.top()
 
     cmdlist = []
diff --git a/switchboard/sc/sed/remove.py b/switchboard/sc/sed/remove.py
index 006717e6..8a18a45f 100644
--- a/switchboard/sc/sed/remove.py
+++ b/switchboard/sc/sed/remove.py
@@ -2,6 +2,7 @@
 # This code is licensed under Apache License 2.0 (see LICENSE for details)
 
 from .sed import setup as setup_tool
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
@@ -12,7 +13,7 @@ def setup(chip):
     tool = 'sed'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    task = chip._get_task(step, index)
+    _, task = get_tool_task(chip, step, index)
 
     chip.set('tool', tool, 'task', task, 'var', 'to_remove',
              'strings to remove from the Verilog source file',
@@ -23,7 +24,7 @@ def runtime_options(chip):
     tool = 'sed'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    task = chip._get_task(step, index)
+    _, task = get_tool_task(chip, step, index)
     design = chip.top()
 
     infile = f'inputs/{design}.v'