From eff42f831eadb571806f14bf0d4abf31a42fffcd Mon Sep 17 00:00:00 2001 From: volkamir Date: Wed, 22 Nov 2023 07:21:44 -0800 Subject: [PATCH 1/4] remove old test benches for fifo --- umi/testbench/tb_umi_fifo.v | 223 ----------------------------- umi/testbench/tb_umi_fifo_flex.v | 234 ------------------------------- 2 files changed, 457 deletions(-) delete mode 100644 umi/testbench/tb_umi_fifo.v delete mode 100644 umi/testbench/tb_umi_fifo_flex.v diff --git a/umi/testbench/tb_umi_fifo.v b/umi/testbench/tb_umi_fifo.v deleted file mode 100644 index 86f210f..0000000 --- a/umi/testbench/tb_umi_fifo.v +++ /dev/null @@ -1,223 +0,0 @@ -/******************************************************************************* - * Copyright 2023 Zero ASIC Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -module tb_umi_fifo - #(parameter TARGET = "DEFAULT", // pass through variable for hard macro - parameter TIMEOUT = 5000, // timeout value (cycles) - parameter PERIOD_CLK = 10, // clock period - parameter FIFODEPTH = 4, // fifo depth - parameter CW = 32, // UMI width - parameter AW = 64, // UMI width - parameter DW = 512 // UMI width - ) - (); - - //#################### - // LOCAL PARAMS - //#################### - - localparam STIMDEPTH = 1024; - localparam NUMI = 1; - localparam TCW = 8; - - //##################### - //# SIMCTRL - //##################### - reg umi_dut2check_ready; - - reg [128*8-1:0] memhfile; - reg slowclk; - reg clk; - reg load; - reg nreset; - reg dut_nreset; - reg go; - integer r; - - // reset initialization - initial - begin - #(1) - nreset = 1'b0; - dut_nreset = 1'b0; - clk = 1'b0; - load = 1'b0; - go = 1'b0; - #(PERIOD_CLK) - go = 1'b1; - nreset = 1'b1; - #(PERIOD_CLK * 10) - dut_nreset = 1'b1; -// #(PERIOD_CLK * 10) -// go = 1'b1; - end // initial begin - - // clocks - always - #(PERIOD_CLK/2) clk = ~clk; - - // control block - initial - begin - r = $value$plusargs("MEMHFILE=%s", memhfile); - $readmemh(memhfile, umi_stimulus.ram); - $timeformat(-9, 0, " ns", 20); - $dumpfile("waveform.vcd"); - $dumpvars(); - #(TIMEOUT) - $finish; - end - - always @ (posedge slowclk or negedge nreset) - if(~nreset) - umi_dut2check_ready <= 1'b0; - else - umi_dut2check_ready <= ~umi_dut2check_ready; - - // clock divider - always @ (posedge clk or negedge nreset) - if (~nreset) - slowclk <= 1'b0; - else - slowclk <= ~slowclk; - - la_rsync la_rsync (// Outputs - .nrst_out (slownreset), - // Inputs - .clk (slowclk), - .nrst_in (nreset)); - - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire done; - wire error; - wire [NUMI*CW-1:0] umi_dut2check_cmd; - wire [NUMI*DW-1:0] umi_dut2check_data; - wire [NUMI*AW-1:0] umi_dut2check_dstaddr; - wire [NUMI*AW-1:0] umi_dut2check_srcaddr; - wire [NUMI-1:0] umi_dut2check_valid; - wire [CW-1:0] umi_stim2dut_cmd; - wire [DW-1:0] umi_stim2dut_data; - wire umi_stim2dut_done; - wire [AW-1:0] umi_stim2dut_dstaddr; - wire [NUMI-1:0] umi_stim2dut_ready; - wire [AW-1:0] umi_stim2dut_srcaddr; - wire umi_stim2dut_valid; - // End of automatics - - //################################################ - //# DUT - //################################################# - - /*dut_umi_fifo AUTO_TEMPLATE ( - .clk (clk), - .ctrl (1'b0), - .status (), - .umi_out_clk (slowclk), - .umi_out_nreset (slownreset), - .umi_out_ready (1'b1), - .umi_out_\(.*\) (umi_dut2check_\1[]), - .umi_in_clk (clk), - .umi_in_nreset (nreset), - .umi_in_valid (umi_stim2dut_valid), - .umi_in_\(.*\) (umi_stim2dut_\1[]), - ); - */ - - dut_umi_fifo #(.CW(CW), - .AW(AW), - .DW(DW), - .DEPTH(FIFODEPTH)) - dut_umi_fifo (.umi_out_ready (umi_dut2check_ready), - /*AUTOINST*/ - // Outputs - .error (error), - .done (done), - .status (), // Templated - .umi_in_ready (umi_stim2dut_ready[NUMI-1:0]), // Templated - .umi_out_valid (umi_dut2check_valid[NUMI-1:0]), // Templated - .umi_out_cmd (umi_dut2check_cmd[NUMI*CW-1:0]), // Templated - .umi_out_dstaddr (umi_dut2check_dstaddr[NUMI*AW-1:0]), // Templated - .umi_out_srcaddr (umi_dut2check_srcaddr[NUMI*AW-1:0]), // Templated - .umi_out_data (umi_dut2check_data[NUMI*DW-1:0]), // Templated - // Inputs - .nreset (dut_nreset), - .clk (clk), // Templated - .go (go), - .ctrl (1'b0), // Templated - .umi_in_clk (clk), // Templated - .umi_in_nreset (dut_nreset), // Templated - .umi_in_valid (umi_stim2dut_valid), // Templated - .umi_in_cmd (umi_stim2dut_cmd[NUMI*CW-1:0]), // Templated - .umi_in_dstaddr (umi_stim2dut_dstaddr[NUMI*AW-1:0]), // Templated - .umi_in_srcaddr (umi_stim2dut_srcaddr[NUMI*AW-1:0]), // Templated - .umi_in_data (umi_stim2dut_data[NUMI*DW-1:0]), // Templated - .umi_out_clk (slowclk), // Templated - .umi_out_nreset (slownreset)); // Templated - - //################################################## - //# UMI STIMULUS DRIVER (CLK) - //################################################## - - /*umi_stimulus AUTO_TEMPLATE ( - // Outputs - .stim_\(.*\) (umi_stim2dut_\1[]), - .dut_ready (umi_stim2dut_ready), - .ext_valid (1'b0), - .ext_packet ({(DW+AW+AW+CW+TCW){1'b0}}), - .\(.*\)_clk (clk), - ); - */ - - umi_stimulus #(.DEPTH(STIMDEPTH), - .TARGET(TARGET), - .CW(CW), - .AW(AW), - .DW(DW), - .TCW(TCW)) - umi_stimulus (/*AUTOINST*/ - // Outputs - .stim_valid (umi_stim2dut_valid), // Templated - .stim_cmd (umi_stim2dut_cmd[CW-1:0]), // Templated - .stim_dstaddr (umi_stim2dut_dstaddr[AW-1:0]), // Templated - .stim_srcaddr (umi_stim2dut_srcaddr[AW-1:0]), // Templated - .stim_data (umi_stim2dut_data[DW-1:0]), // Templated - .stim_done (umi_stim2dut_done), // Templated - // Inputs - .nreset (nreset), - .load (load), - .go (go), - .ext_clk (clk), // Templated - .ext_valid (1'b0), // Templated - .ext_packet ({(DW+AW+AW+CW+TCW){1'b0}}), // Templated - .dut_clk (clk), // Templated - .dut_ready (umi_stim2dut_ready)); // Templated - - //################################################### - //# TRAFFIC MONITOR (SLOWCLK) - //################################################### - - always @ (negedge slowclk) - if(umi_dut2check_valid & umi_dut2check_ready) - $display("dut result: data=%h, srcaddr=%h, dstaddr=%h, cmd=%h", umi_dut2check_data[DW-1:0], umi_dut2check_srcaddr[AW-1:0],umi_dut2check_dstaddr[AW-1:0],umi_dut2check_cmd[CW-1:0]); - - -endmodule // testbench -// Local Variables: -// verilog-library-directories:("." "../rtl" "../../submodules/oh/stdlib/rtl/" "../../submodules/oh/stdlib/testbench/") -// End: diff --git a/umi/testbench/tb_umi_fifo_flex.v b/umi/testbench/tb_umi_fifo_flex.v deleted file mode 100644 index cf71534..0000000 --- a/umi/testbench/tb_umi_fifo_flex.v +++ /dev/null @@ -1,234 +0,0 @@ -/******************************************************************************* - * Copyright 2023 Zero ASIC Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -module tb_umi_fifo - #(parameter TARGET = "DEFAULT", // pass through variable for hard macro - parameter TIMEOUT = 5000, // timeout value (cycles) - parameter PERIOD_CLK = 10, // clock period - parameter FIFODEPTH = 4 // fifo depth - ) - (); - - //#################### - // LOCAL PARAMS - //#################### - - localparam STIMDEPTH = 1024; - localparam NUMI = 1; - localparam TCW = 8; - localparam CW = 32; // UMI width - localparam AW = 64; // UMI width - localparam IDW = 512; // UMI width - localparam ODW = 128; // UMI width - localparam DW = IDW; - localparam BYPASS = 0; - - //##################### - //# SIMCTRL - //##################### - reg umi_dut2check_ready; - - reg [128*8-1:0] memhfile; - reg slowclk; - reg clk; - reg load; - reg nreset; - reg early_nreset; - reg go; - integer r; - - // reset initialization - initial - begin - #(1) - nreset = 1'b0; - early_nreset = 1'b0; - clk = 1'b0; - load = 1'b0; - go = 1'b0; - #(PERIOD_CLK * 5) - early_nreset = 1'b1; - #(PERIOD_CLK * 10) - nreset = 1'b1; - #(PERIOD_CLK * 10) - go = 1'b1; - end // initial begin - - // clocks - always - #(PERIOD_CLK/2) clk = ~clk; - - // control block - initial - begin - r = $value$plusargs("MEMHFILE=%s", memhfile); - $readmemh(memhfile, umi_stimulus.ram); - $timeformat(-9, 0, " ns", 20); - $dumpfile("waveform.vcd"); - $dumpvars(); - #(TIMEOUT) - $finish; - end - - always @ (posedge slowclk or negedge nreset) - if(~nreset) - umi_dut2check_ready <= 1'b0; - else - umi_dut2check_ready <= ~umi_dut2check_ready; - - generate if (BYPASS) - always @* - slowclk = clk; - else - // clock divider - always @ (posedge clk or negedge early_nreset) - if (~early_nreset) - slowclk <= 1'b0; - else - slowclk <= ~slowclk; - endgenerate - - la_rsync la_rsync (// Outputs - .nrst_out (slownreset), - // Inputs - .clk (slowclk), - .nrst_in (nreset)); - - - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire done; - wire error; - wire [NUMI*CW-1:0] umi_dut2check_cmd; - wire [NUMI*ODW-1:0] umi_dut2check_data; - wire [NUMI*AW-1:0] umi_dut2check_dstaddr; - wire [NUMI*AW-1:0] umi_dut2check_srcaddr; - wire [NUMI-1:0] umi_dut2check_valid; - wire [CW-1:0] umi_stim2dut_cmd; - wire [DW-1:0] umi_stim2dut_data; - wire umi_stim2dut_done; - wire [AW-1:0] umi_stim2dut_dstaddr; - wire [NUMI-1:0] umi_stim2dut_ready; - wire [AW-1:0] umi_stim2dut_srcaddr; - wire umi_stim2dut_valid; - // End of automatics - - //################################################ - //# DUT - //################################################# - - /*dut_umi_fifo_flex AUTO_TEMPLATE ( - .clk (clk), - .ctrl (1'b0), - .status (), - .bypass (|BYPASS), - .umi_out_clk (slowclk), - .umi_out_nreset (slownreset), - .umi_out_ready (1'b1), - .umi_out_\(.*\) (umi_dut2check_\1[]), - .umi_in_clk (clk), - .umi_in_nreset (nreset), - .umi_in_valid (umi_stim2dut_valid), - .umi_in_\(.*\) (umi_stim2dut_\1[]), - ); - */ - - dut_umi_fifo_flex #(.CW(CW), - .IDW(IDW), - .AW(AW), - .ODW(ODW), - .DEPTH(FIFODEPTH), - .BYPASS(BYPASS)) - dut_umi_fifo_flex (.umi_out_ready (umi_dut2check_ready), - /*AUTOINST*/ - // Outputs - .error (error), - .done (done), - .status (), // Templated - .umi_in_ready (umi_stim2dut_ready[NUMI-1:0]), // Templated - .umi_out_valid (umi_dut2check_valid[NUMI-1:0]), // Templated - .umi_out_cmd (umi_dut2check_cmd[NUMI*CW-1:0]), // Templated - .umi_out_dstaddr (umi_dut2check_dstaddr[NUMI*AW-1:0]), // Templated - .umi_out_srcaddr (umi_dut2check_srcaddr[NUMI*AW-1:0]), // Templated - .umi_out_data (umi_dut2check_data[NUMI*ODW-1:0]), // Templated - // Inputs - .nreset (nreset), - .clk (clk), // Templated - .go (go), - .ctrl (1'b0), // Templated - .bypass (|BYPASS), // Templated - .umi_in_clk (clk), // Templated - .umi_in_nreset (nreset), // Templated - .umi_in_valid (umi_stim2dut_valid), // Templated - .umi_in_cmd (umi_stim2dut_cmd[NUMI*CW-1:0]), // Templated - .umi_in_dstaddr (umi_stim2dut_dstaddr[NUMI*AW-1:0]), // Templated - .umi_in_srcaddr (umi_stim2dut_srcaddr[NUMI*AW-1:0]), // Templated - .umi_in_data (umi_stim2dut_data[NUMI*IDW-1:0]), // Templated - .umi_out_clk (slowclk), // Templated - .umi_out_nreset (slownreset)); // Templated - - //################################################## - //# UMI STIMULUS DRIVER (CLK) - //################################################## - - /*umi_stimulus AUTO_TEMPLATE ( - // Outputs - .stim_\(.*\) (umi_stim2dut_\1[]), - .dut_ready (umi_stim2dut_ready[]), - .ext_valid (1'b0), - .ext_packet ({(IDW+AW+AW+CW+TCW){1'b0}}), - .\(.*\)_clk (clk), - ); - */ - - umi_stimulus #(.DEPTH(STIMDEPTH), - .TARGET(TARGET), - .CW(CW), - .AW(AW), - .DW(IDW), - .TCW(TCW)) - umi_stimulus (/*AUTOINST*/ - // Outputs - .stim_valid (umi_stim2dut_valid), // Templated - .stim_cmd (umi_stim2dut_cmd[CW-1:0]), // Templated - .stim_dstaddr (umi_stim2dut_dstaddr[AW-1:0]), // Templated - .stim_srcaddr (umi_stim2dut_srcaddr[AW-1:0]), // Templated - .stim_data (umi_stim2dut_data[DW-1:0]), // Templated - .stim_done (umi_stim2dut_done), // Templated - // Inputs - .nreset (nreset), - .load (load), - .go (go), - .ext_clk (clk), // Templated - .ext_valid (1'b0), // Templated - .ext_packet ({(IDW+AW+AW+CW+TCW){1'b0}}), // Templated - .dut_clk (clk), // Templated - .dut_ready (umi_stim2dut_ready)); // Templated - - //################################################### - //# TRAFFIC MONITOR (SLOWCLK) - //################################################### - - always @ (negedge slowclk) - if(umi_dut2check_valid & umi_dut2check_ready) - $display("dut result: data=%h, srcaddr=%h, dstaddr=%h, cmd=%h", umi_dut2check_data[DW-1:0], umi_dut2check_srcaddr[AW-1:0],umi_dut2check_dstaddr[AW-1:0],umi_dut2check_cmd[CW-1:0]); - - -endmodule // testbench -// Local Variables: -// verilog-library-directories:("." "../rtl" "../../submodules/oh/stdlib/rtl/" "../../submodules/oh/stdlib/testbench/") -// End: From efb9475c290ba644a4a4c9982729172951484e8f Mon Sep 17 00:00:00 2001 From: volkamir Date: Wed, 22 Nov 2023 07:21:59 -0800 Subject: [PATCH 2/4] remove old build script --- umi/testbench/build_local.sh | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100755 umi/testbench/build_local.sh diff --git a/umi/testbench/build_local.sh b/umi/testbench/build_local.sh deleted file mode 100755 index 8398072..0000000 --- a/umi/testbench/build_local.sh +++ /dev/null @@ -1,14 +0,0 @@ -\rm -f a.out - -iverilog tb_umi_fifo_flex.v \ - -y . \ - -y ../rtl \ - -I . \ - -I ../rtl \ - -y ../../submodules/lambdalib/stdlib/rtl \ - -y ../../submodules/lambdalib/vectorlib/rtl \ - -y ../../submodules/lambdalib/ramlib/rtl - -#./a.out -#./a.out +MEMHFILE=./hello.memh -./a.out +MEMHFILE=./buffer.memh From 7cfab75d4643c0b076d4c4ab269efa13185f6d27 Mon Sep 17 00:00:00 2001 From: volkamir Date: Wed, 22 Nov 2023 07:22:25 -0800 Subject: [PATCH 3/4] rm unused tb --- umi/testbench/verilog/umi_testbench.sv | 95 -------------------------- 1 file changed, 95 deletions(-) delete mode 100644 umi/testbench/verilog/umi_testbench.sv diff --git a/umi/testbench/verilog/umi_testbench.sv b/umi/testbench/verilog/umi_testbench.sv deleted file mode 100644 index e7f18d6..0000000 --- a/umi/testbench/verilog/umi_testbench.sv +++ /dev/null @@ -1,95 +0,0 @@ -/******************************************************************************* - * Copyright 2020 Zero ASIC Corporation - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * ---- - * - * Documentation: - * - Testbench driver wrapper for switchboard - * - ******************************************************************************/ - -module umi_testbench ( - input clk, - input nreset -); - // UMI RX port - - wire [255:0] umi_packet_rx; - wire umi_valid_rx; - wire umi_ready_rx; - - // UMI TX port - - wire [255:0] umi_packet_tx; - wire umi_valid_tx; - wire umi_ready_tx; - - umi_rx_sim rx_i ( - .clk(clk), - .ready(umi_ready_rx), // input - .packet(umi_packet_rx), // output - .valid(umi_valid_rx) // output - ); - - umi_tx_sim tx_i ( - .clk(clk), - .ready(umi_ready_tx), // output - .packet(umi_packet_tx), // input - .valid(umi_valid_tx) // input - ); - - `MOD_UNDER_TEST uut ( - .clk(clk), - .nreset(nreset), - - .rx0_umi_valid(umi_valid_rx), - .rx0_umi_packet(umi_packet_rx), - .rx0_umi_ready(umi_ready_rx), - - .tx0_umi_valid(umi_valid_tx), - .tx0_umi_packet(umi_packet_tx), - .tx0_umi_ready(umi_ready_tx) - ); - - string rx_port; - string tx_port; - -`ifdef TRACE - initial begin - $dumpfile("umi_testbench.vcd"); - $dumpvars; - end -`endif - - initial begin - // read command-line arguments, setting defaults as needed - - if (!$value$plusargs("rx_port=%s", rx_port)) begin - rx_port = "queue-5555"; - end - - if (!$value$plusargs("tx_port=%s", tx_port)) begin - tx_port = "queue-5556"; - end - - // initialize UMI according to command-line arguments - - /* verilator lint_off IGNOREDRETURN */ - rx_i.init(rx_port); - tx_i.init(tx_port); - /* verilator lint_on IGNOREDRETURN */ - end - -endmodule From 2aaf64ce10acd875da75eb2abb7ac0e72efdaf20 Mon Sep 17 00:00:00 2001 From: volkamir Date: Wed, 22 Nov 2023 07:43:17 -0800 Subject: [PATCH 4/4] rm old examples --- examples/umi_mem/.gitignore | 2 - examples/umi_mem/README.md | 43 -------------------- examples/umi_mem/test_umi_mem.py | 36 ----------------- examples/umi_mem/tests/expect1.memh | 1 - examples/umi_mem/tests/expect2.memh | 2 - examples/umi_mem/tests/stimulus1.memh | 2 - examples/umi_mem/tests/stimulus2.memh | 4 -- examples/umi_mem/umi_mem.py | 14 ------- examples/umi_mem/umi_mem.v | 58 --------------------------- 9 files changed, 162 deletions(-) delete mode 100644 examples/umi_mem/.gitignore delete mode 100644 examples/umi_mem/README.md delete mode 100644 examples/umi_mem/test_umi_mem.py delete mode 100644 examples/umi_mem/tests/expect1.memh delete mode 100644 examples/umi_mem/tests/expect2.memh delete mode 100644 examples/umi_mem/tests/stimulus1.memh delete mode 100644 examples/umi_mem/tests/stimulus2.memh delete mode 100644 examples/umi_mem/umi_mem.py delete mode 100644 examples/umi_mem/umi_mem.v diff --git a/examples/umi_mem/.gitignore b/examples/umi_mem/.gitignore deleted file mode 100644 index 6fdd538..0000000 --- a/examples/umi_mem/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -# SC build directory -build/ diff --git a/examples/umi_mem/README.md b/examples/umi_mem/README.md deleted file mode 100644 index 799a55a..0000000 --- a/examples/umi_mem/README.md +++ /dev/null @@ -1,43 +0,0 @@ -# UMI Memory Example - -This example is a small test of `umi_endpoint` that wires it up to a generic -memory. It is meant to demonstrate how to use a common testbench to write unit -tests for a block that uses UMI. - -We use pytest for managing tests, which provides useful functionality for -automatic test discovery and running. To run the tests in this example, install -pytest: - -```shell -pip install pytest -``` - -Next, clone switchboard, compile its umidriver executable, and set an env -variable pointing to it: - -```shell -cd /path/to/switchboard/cpp -make umidriver -export SBDIR=/path/to/switchboard -``` - -Then, simply execute pytest to run the tests: - -```shell -pytest -``` - -By default, pytest will look for and run any Python functions whose names begin -with test_ in Python files whose names begin with test_. We've placed the -example tests in `test_umi_mem.py.` - -## pytest tricks - -pytest has a variety of command line flags to control how and which tests are -run. Here are some useful ones: - -- `pytest -s`: displays live output (pytest usually swallows it, and only prints -on failure) -- `pytest --collect-only`: display test names, but do not execute them (dry-run) -- `pytest -k `: run specific test(s), e.g. `pytest -k test_basic` -(`-k` supports fuzzy matching as well) diff --git a/examples/umi_mem/test_umi_mem.py b/examples/umi_mem/test_umi_mem.py deleted file mode 100644 index 091f58f..0000000 --- a/examples/umi_mem/test_umi_mem.py +++ /dev/null @@ -1,36 +0,0 @@ -import sys - -sys.path.append('../../umi/testbench') -import umi_testbench - -import pytest - -import umi_mem - -@pytest.fixture(scope='module') -def chip_tb(): - '''Setup/compile the testbench. - - The decorator above this method ensures that this code executes once per - test session, making it faster to run multiple tests at once. - ''' - chip = umi_mem.setup() - - # Uncomment to enable VCD dumps for each test. - #chip.set('option', 'trace', True) - - # Set a timeout for test execution in seconds. Useful since tests will - # otherwise hang if the expected # of transactions are not received. - chip.set('flowgraph', 'verification', 'execute', '0', 'timeout', 2) - - return umi_testbench.compile_tb(chip, 'umi_mem') - -def test_1(chip_tb): - chip_tb.set('input', 'txfile', 'tests/stimulus1.memh') - chip_tb.set('input', 'rxfile', 'tests/expect1.memh') - umi_testbench.run_tb(chip_tb, 'test_1') - -def test_2(chip_tb): - chip_tb.set('input', 'txfile', 'tests/stimulus2.memh') - chip_tb.set('input', 'rxfile', 'tests/expect2.memh') - umi_testbench.run_tb(chip_tb, 'test_2') diff --git a/examples/umi_mem/tests/expect1.memh b/examples/umi_mem/tests/expect1.memh deleted file mode 100644 index 0d45011..0000000 --- a/examples/umi_mem/tests/expect1.memh +++ /dev/null @@ -1 +0,0 @@ -00000000_00000000_00000000_00000000_DEADBEEF_00000000_00000000_00000208 diff --git a/examples/umi_mem/tests/expect2.memh b/examples/umi_mem/tests/expect2.memh deleted file mode 100644 index 75a5a0b..0000000 --- a/examples/umi_mem/tests/expect2.memh +++ /dev/null @@ -1,2 +0,0 @@ -00000000_00000000_00000000_00000000_DEADBEEF_00000000_00000000_00000208 -00000000_00000000_00000000_00000000_BEEFDEAD_00000000_00000000_00000208 diff --git a/examples/umi_mem/tests/stimulus1.memh b/examples/umi_mem/tests/stimulus1.memh deleted file mode 100644 index 5c6bb1d..0000000 --- a/examples/umi_mem/tests/stimulus1.memh +++ /dev/null @@ -1,2 +0,0 @@ -00000000_00000000_00000000_00000000_DEADBEEF_00000000_00000000_00000201 -00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000208 diff --git a/examples/umi_mem/tests/stimulus2.memh b/examples/umi_mem/tests/stimulus2.memh deleted file mode 100644 index 7534b1a..0000000 --- a/examples/umi_mem/tests/stimulus2.memh +++ /dev/null @@ -1,4 +0,0 @@ -00000000_00000000_00000000_00000000_DEADBEEF_00000000_00000000_00000201 -00000000_00000000_00000000_00000000_BEEFDEAD_00000000_00000040_00000201 -00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000208 -00000000_00000000_00000000_00000000_00000000_00000000_00000040_00000208 diff --git a/examples/umi_mem/umi_mem.py b/examples/umi_mem/umi_mem.py deleted file mode 100644 index fa21730..0000000 --- a/examples/umi_mem/umi_mem.py +++ /dev/null @@ -1,14 +0,0 @@ -import os - -import siliconcompiler - -umi_root = os.path.join(os.path.dirname(os.path.abspath(__file__)), '..', '..') - -def setup(): - '''Generic setup for ASIC build and verification.''' - chip = siliconcompiler.Chip('umi_mem') - chip.set('input', 'verilog', 'umi_mem.v') - chip.add('option', 'ydir', f'{umi_root}/umi/rtl') - # May load entire target here instead, but only flow required for verif. - chip.load_flow('verification') - return chip diff --git a/examples/umi_mem/umi_mem.v b/examples/umi_mem/umi_mem.v deleted file mode 100644 index 384d8d7..0000000 --- a/examples/umi_mem/umi_mem.v +++ /dev/null @@ -1,58 +0,0 @@ -module umi_mem #( - parameter AW = 16, - parameter DW = 64 -) ( - input clk, - input nreset, - - input rx0_umi_valid, - input [255:0] rx0_umi_packet, - output rx0_umi_ready, - - output tx0_umi_valid, - output [255:0] tx0_umi_packet, - input tx0_umi_ready -); - - wire [AW-1:0] addr; - wire write; - wire read; - wire [DW-1:0] write_data; - wire [DW-1:0] read_data; - - reg [DW-1:0] mem[1 << (AW - $clog2(DW))]; - - umi_endpoint #( - .DW(DW) - ) endpoint( - .clk(clk), - .nreset(nreset), - - .valid_in(rx0_umi_valid), - .packet_in(rx0_umi_packet), - .ready_out(rx0_umi_ready), - - .valid_out(tx0_umi_valid), - .packet_out(tx0_umi_packet), - .ready_in(tx0_umi_ready), - - .addr(addr), - .write(write), - .read(read), - .write_data(write_data), - .read_data(read_data) - ); - - // Truncate address - mem only supports DW-aligned accesses. - wire [AW-1-$clog2(DW):0] mem_addr; - assign mem_addr = addr[AW-1:$clog2(DW)]; - - always @(posedge clk) begin - if (write) begin - mem[mem_addr] <= write_data; - end - end - - assign read_data = mem[mem_addr]; - -endmodule